internal-fn: Avoid dropping the lhs of some calls [PR94941]
create_output_operand coerces an output operand to the insn's predicates, using a suggested rtx location if convenient. But if that rtx location is actually required rather than optional, the builder of the insn has to emit a move afterwards. (We could instead add a new interface that does this automatically, but that's future work.) This PR shows that we were failing to emit the move for some of the vector load internal functions. I think there are other routines in internal-fn.c that potentially have the same problem, but this patch is supposed to be a conservative subset suitable for backporting to GCC 10. 2020-05-04 Richard Sandiford <richard.sandiford@arm.com> gcc/ PR middle-end/94941 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the chosen lhs is different from the gcall lhs. (expand_mask_load_optab_fn): Likewise. (expand_gather_load_optab_fn): Likewise. gcc/testsuite/ PR middle-end/94941 * gcc.target/aarch64/sve/acle/general/unoptimized_1.c: New test.
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@ -1,3 +1,11 @@
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2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
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PR middle-end/94941
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* internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
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chosen lhs is different from the gcall lhs.
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(expand_mask_load_optab_fn): Likewise.
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(expand_gather_load_optab_fn): Likewise.
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2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
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PR target/94795
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@ -167,6 +167,8 @@ expand_load_lanes_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
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create_output_operand (&ops[0], target, TYPE_MODE (type));
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create_fixed_operand (&ops[1], mem);
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expand_insn (get_multi_vector_move (type, optab), 2, ops);
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if (!rtx_equal_p (target, ops[0].value))
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emit_move_insn (target, ops[0].value);
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}
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/* Expand STORE_LANES call STMT using optab OPTAB. */
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@ -2507,6 +2509,8 @@ expand_mask_load_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
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create_fixed_operand (&ops[1], mem);
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create_input_operand (&ops[2], mask, TYPE_MODE (TREE_TYPE (maskt)));
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expand_insn (icode, 3, ops);
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if (!rtx_equal_p (target, ops[0].value))
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emit_move_insn (target, ops[0].value);
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}
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#define expand_mask_load_lanes_optab_fn expand_mask_load_optab_fn
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@ -2827,6 +2831,8 @@ expand_gather_load_optab_fn (internal_fn, gcall *stmt, direct_optab optab)
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insn_code icode = convert_optab_handler (optab, TYPE_MODE (TREE_TYPE (lhs)),
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TYPE_MODE (TREE_TYPE (offset)));
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expand_insn (icode, i, ops);
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if (!rtx_equal_p (lhs_rtx, ops[0].value))
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emit_move_insn (lhs_rtx, ops[0].value);
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}
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/* Expand DIVMOD() using:
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@ -1,3 +1,8 @@
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2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
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PR middle-end/94941
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* gcc.target/aarch64/sve/acle/general/unoptimized_1.c: New test.
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2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
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PR target/94795
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@ -0,0 +1,21 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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#include <arm_sve.h>
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svfloat32_t
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foo (float *ptr)
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{
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svbool_t pg = svptrue_pat_b32 (SV_VL1);
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svfloat32_t res = svld1 (pg, ptr);
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return res;
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}
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int
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main (void)
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{
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svbool_t pg = svptrue_pat_b32 (SV_VL1);
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float x[1] = { 1 };
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if (svptest_any (pg, svcmpne (pg, foo (x), 1.0)))
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__builtin_abort ();
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return 0;
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}
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