amdgcn: Align VGPR pairs
Aligning the registers is not needed by the architecture, but doing so allows us to remove the requirement for bug-prone early-clobber constraints from many split patterns (and avoid adding more in future). 2020-02-21 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs. * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber. (addv64di3_exec): Likewise. (subv64di3): Likewise. (subv64di3_exec): Likewise. (addv64di3_zext): Likewise. (addv64di3_zext_exec): Likewise. (addv64di3_zext_dup): Likewise. (addv64di3_zext_dup_exec): Likewise. (addv64di3_zext_dup2): Likewise. (addv64di3_zext_dup2_exec): Likewise. (addv64di3_sext_dup2): Likewise. (addv64di3_sext_dup2_exec): Likewise. (<expander>v64di3): Likewise. (<expander>v64di3_exec): Likewise. (*<reduc_op>_dpp_shr_v64di): Likewise. (*plus_carry_dpp_shr_v64di): Likewise. * config/gcn/gcn.md (adddi3): Likewise. (addptrdi3): Likewise. (<expander>di3): Likewise.
This commit is contained in:
Andrew Stubbs
parent
2291d1fd85
commit
3abfd4f341
4 changed files with 98 additions and 74 deletions
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@ -1,3 +1,26 @@
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2020-02-21 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
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* config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
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(addv64di3_exec): Likewise.
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(subv64di3): Likewise.
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(subv64di3_exec): Likewise.
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(addv64di3_zext): Likewise.
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(addv64di3_zext_exec): Likewise.
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(addv64di3_zext_dup): Likewise.
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(addv64di3_zext_dup_exec): Likewise.
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(addv64di3_zext_dup2): Likewise.
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(addv64di3_zext_dup2_exec): Likewise.
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(addv64di3_sext_dup2): Likewise.
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(addv64di3_sext_dup2_exec): Likewise.
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(<expander>v64di3): Likewise.
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(<expander>v64di3_exec): Likewise.
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(*<reduc_op>_dpp_shr_v64di): Likewise.
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(*plus_carry_dpp_shr_v64di): Likewise.
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* config/gcn/gcn.md (adddi3): Likewise.
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(addptrdi3): Likewise.
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(<expander>di3): Likewise.
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2020-02-21 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
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@ -1171,10 +1171,10 @@
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(set_attr "length" "4,8,4,8")])
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(define_insn_and_split "addv64di3"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(plus:V64DI
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(match_operand:V64DI 1 "register_operand" "%vDb,vDb0")
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb0, vDb")))
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(match_operand:V64DI 1 "register_operand" "%vDb")
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(match_operand:V64DI 2 "gcn_alu_operand" " vDb")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1200,14 +1200,13 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_exec"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(vec_merge:V64DI
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(plus:V64DI
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(match_operand:V64DI 1 "register_operand" "%vDb,vDb0,vDb")
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb0, vDb,vDb"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand"
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" U, U, 0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e, e")))
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(match_operand:V64DI 1 "register_operand" "%vDb")
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(match_operand:V64DI 2 "gcn_alu_operand" " vDb"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1238,10 +1237,10 @@
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(set_attr "length" "8")])
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(define_insn_and_split "subv64di3"
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[(set (match_operand:V64DI 0 "register_operand" "=&v, &v, &v, &v")
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vDb,vDb0, v, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vDb0,vDb")))
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vDb, v")
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(match_operand:V64DI 2 "gcn_alu_operand" " v,vDb")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1267,14 +1266,13 @@
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(set_attr "length" "8")])
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(define_insn_and_split "subv64di3_exec"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(vec_merge:V64DI
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB,vSvB0, v, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vSvB0,vSvB"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand"
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" U0, U0, U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e, e, e")))
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB, v")
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(match_operand:V64DI 2 "gcn_alu_operand" " v,vSvB"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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(clobber (reg:DI VCC_REG))]
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"register_operand (operands[1], VOIDmode)
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|| register_operand (operands[2], VOIDmode)"
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@ -1306,11 +1304,11 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext"
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[(set (match_operand:V64DI 0 "register_operand" "=&v, &v, &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(plus:V64DI
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(zero_extend:V64DI
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(match_operand:V64SI 1 "gcn_alu_operand" "0vA,0vB, vA, vB"))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb,vDA,0vDb,0vDA")))
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(match_operand:V64SI 1 "gcn_alu_operand" " vA, vB"))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb,vDA")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1334,15 +1332,14 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext_exec"
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[(set (match_operand:V64DI 0 "register_operand" "=&v, &v, &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(vec_merge:V64DI
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(plus:V64DI
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(zero_extend:V64DI
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(match_operand:V64SI 1 "gcn_alu_operand" "0vA, vA,0vB, vB"))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb,0vDb,vDA,0vDA"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand"
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" U0, U0, U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e, e, e")))
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(match_operand:V64SI 1 "gcn_alu_operand" " vA, vB"))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb,vDA"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1371,12 +1368,12 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext_dup"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(plus:V64DI
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(zero_extend:V64DI
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(vec_duplicate:V64SI
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(match_operand:SI 1 "gcn_alu_operand" " BSv, ASv")))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDA0,vDb0")))
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(match_operand:SI 1 "gcn_alu_operand" "BSv,ASv")))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDA,vDb")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1400,15 +1397,15 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext_dup_exec"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v, v")
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(vec_merge:V64DI
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(plus:V64DI
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(zero_extend:V64DI
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(vec_duplicate:V64SI
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(match_operand:SI 1 "gcn_alu_operand" " ASv, BSv")))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb0,vDA0"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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(match_operand:SI 1 "gcn_alu_operand" "ASv,BSv")))
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(match_operand:V64DI 2 "gcn_alu_operand" "vDb,vDA"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1437,7 +1434,7 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext_dup2"
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[(set (match_operand:V64DI 0 "register_operand" "= &v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(plus:V64DI
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(zero_extend:V64DI (match_operand:V64SI 1 "gcn_alu_operand" " vA"))
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(vec_duplicate:V64DI (match_operand:DI 2 "gcn_alu_operand" "DbSv"))))
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@ -1463,7 +1460,7 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_zext_dup2_exec"
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[(set (match_operand:V64DI 0 "register_operand" "=&v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(vec_merge:V64DI
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(plus:V64DI
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(zero_extend:V64DI (match_operand:V64SI 1 "gcn_alu_operand"
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@ -1500,7 +1497,7 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_sext_dup2"
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[(set (match_operand:V64DI 0 "register_operand" "=&v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(plus:V64DI
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(sign_extend:V64DI (match_operand:V64SI 1 "gcn_alu_operand" " vA"))
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(vec_duplicate:V64DI (match_operand:DI 2 "gcn_alu_operand" "BSv"))))
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@ -1528,7 +1525,7 @@
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_sext_dup2_exec"
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[(set (match_operand:V64DI 0 "register_operand" "=&v")
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[(set (match_operand:V64DI 0 "register_operand" "= v")
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(vec_merge:V64DI
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(plus:V64DI
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(sign_extend:V64DI (match_operand:V64SI 1 "gcn_alu_operand"
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@ -1935,10 +1932,10 @@
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(set_attr "length" "8,8")])
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(define_insn_and_split "<expander>v64di3"
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[(set (match_operand:V64DI 0 "gcn_valu_dst_operand" "=&v,RD")
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[(set (match_operand:V64DI 0 "gcn_valu_dst_operand" "= v,RD")
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(bitop:V64DI
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(match_operand:V64DI 1 "gcn_valu_src0_operand" "% v,RD")
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(match_operand:V64DI 2 "gcn_valu_src1com_operand" "vSvB, v")))]
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(match_operand:V64DI 1 "gcn_valu_src0_operand" "% v,RD")
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(match_operand:V64DI 2 "gcn_valu_src1com_operand" "vSvB, v")))]
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""
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"@
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#
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@ -1960,7 +1957,7 @@
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(set_attr "length" "16,8")])
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(define_insn_and_split "<expander>v64di3_exec"
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[(set (match_operand:V64DI 0 "gcn_valu_dst_operand" "=&v,RD")
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[(set (match_operand:V64DI 0 "gcn_valu_dst_operand" "= v,RD")
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(vec_merge:V64DI
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(bitop:V64DI
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(match_operand:V64DI 1 "gcn_valu_src0_operand" "% v,RD")
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(set_attr "length" "8")])
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(define_insn_and_split "*<reduc_op>_dpp_shr_v64di"
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[(set (match_operand:V64DI 0 "register_operand" "=&v")
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[(set (match_operand:V64DI 0 "register_operand" "=v")
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(unspec:V64DI
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[(match_operand:V64DI 1 "register_operand" "v0")
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(match_operand:V64DI 2 "register_operand" "v0")
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(match_operand:SI 3 "const_int_operand" "n")]
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[(match_operand:V64DI 1 "register_operand" "v")
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(match_operand:V64DI 2 "register_operand" "v")
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(match_operand:SI 3 "const_int_operand" "n")]
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REDUC_2REG_UNSPEC))]
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""
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"#"
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(set_attr "length" "8")])
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(define_insn_and_split "*plus_carry_dpp_shr_v64di"
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[(set (match_operand:V64DI 0 "register_operand" "=&v")
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[(set (match_operand:V64DI 0 "register_operand" "=v")
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(unspec:V64DI
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[(match_operand:V64DI 1 "register_operand" "v0")
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(match_operand:V64DI 2 "register_operand" "v0")
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(match_operand:SI 3 "const_int_operand" "n")]
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[(match_operand:V64DI 1 "register_operand" "v")
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(match_operand:V64DI 2 "register_operand" "v")
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_PLUS_CARRY_DPP_SHR))
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(clobber (reg:DI VCC_REG))]
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""
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@ -458,7 +458,15 @@ gcn_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
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|| (!((regno - FIRST_SGPR_REG) & 1) && sgpr_2reg_mode_p (mode))
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|| (((regno - FIRST_SGPR_REG) & 3) == 0 && mode == TImode));
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if (VGPR_REGNO_P (regno))
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return (vgpr_1reg_mode_p (mode) || vgpr_2reg_mode_p (mode)
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/* Vector instructions do not care about the alignment of register
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pairs, but where there is no 64-bit instruction, many of the
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define_split do not work if the input and output registers partially
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overlap. We tried to fix this with early clobber and match
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constraints, but it was bug prone, added complexity, and conflicts
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with the 'U0' constraints on vec_merge.
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Therefore, we restrict ourselved to aligned registers. */
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return (vgpr_1reg_mode_p (mode)
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|| (!((regno - FIRST_VGPR_REG) & 1) && vgpr_2reg_mode_p (mode))
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/* TImode is used by DImode compare_and_swap. */
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|| mode == TImode);
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return false;
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@ -1065,22 +1065,16 @@
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; through some RTL optimisation passes, and means the CC reg we set isn't
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; dependent on the constraint alternative (which doesn't seem to work well).
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; There's an early clobber in the case where "v[0:1]=v[1:2]+?" but
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; "v[0:1]=v[0:1]+?" is fine (as is "v[1:2]=v[0:1]+?", but that's trickier).
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; If v_addc_u32 is used to add with carry, a 32-bit literal constant cannot be
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; used as an operand due to the read of VCC, so we restrict constants to the
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; inlinable range for that alternative.
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(define_insn_and_split "adddi3"
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[(set (match_operand:DI 0 "register_operand"
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"=&Sg,&Sg,&Sg,&Sg,&v,&v,&v,&v")
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(plus:DI (match_operand:DI 1 "register_operand"
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" Sg, 0, 0, Sg, v, 0, 0, v")
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(match_operand:DI 2 "nonmemory_operand"
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" 0,SgB, 0,SgB, 0,vA, 0,vA")))
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(clobber (match_scratch:BI 3 "= cs, cs, cs, cs, X, X, X, X"))
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(clobber (match_scratch:DI 4 "= X, X, X, X,cV,cV,cV,cV"))]
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[(set (match_operand:DI 0 "register_operand" "=Sg, v")
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(plus:DI (match_operand:DI 1 "register_operand" " Sg, v")
|
||||
(match_operand:DI 2 "nonmemory_operand" "SgB,vA")))
|
||||
(clobber (match_scratch:BI 3 "=cs, X"))
|
||||
(clobber (match_scratch:DI 4 "= X,cV"))]
|
||||
""
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
|
|
@ -1109,7 +1103,7 @@
|
|||
cc));
|
||||
DONE;
|
||||
}
|
||||
[(set_attr "type" "mult,mult,mult,mult,vmult,vmult,vmult,vmult")
|
||||
[(set_attr "type" "mult,vmult")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_expand "adddi3_scc"
|
||||
|
|
@ -1196,11 +1190,14 @@
|
|||
; for this, so we use a custom VOP3 add with CC_SAVE_REG as a temp.
|
||||
; Note that it is not safe to save/clobber/restore SCC because doing so will
|
||||
; break data-flow analysis, so this must use vector registers.
|
||||
;
|
||||
; The "v0" should be just "v", but somehow the "0" helps LRA not loop forever
|
||||
; on testcase pr54713-2.c with -O0. It's only an optimization hint anyway.
|
||||
|
||||
(define_insn "addptrdi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "= &v")
|
||||
(plus:DI (match_operand:DI 1 "register_operand" " v0")
|
||||
(match_operand:DI 2 "nonmemory_operand" "vDA0")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "= v")
|
||||
(plus:DI (match_operand:DI 1 "register_operand" " v0")
|
||||
(match_operand:DI 2 "nonmemory_operand" "vDA")))]
|
||||
""
|
||||
{
|
||||
rtx new_operands[4] = { operands[0], operands[1], operands[2],
|
||||
|
|
@ -1470,15 +1467,14 @@
|
|||
(define_code_iterator vec_and_scalar64_com [and ior xor])
|
||||
|
||||
(define_insn_and_split "<expander>di3"
|
||||
[(set (match_operand:DI 0 "register_operand" "= Sg, &v, &v")
|
||||
[(set (match_operand:DI 0 "register_operand" "= Sg, v")
|
||||
(vec_and_scalar64_com:DI
|
||||
(match_operand:DI 1 "gcn_alu_operand" "%SgA,vSvDB,vSvDB")
|
||||
(match_operand:DI 2 "gcn_alu_operand" " SgC, v, 0")))
|
||||
(clobber (match_scratch:BI 3 "= cs, X, X"))]
|
||||
(match_operand:DI 1 "gcn_alu_operand" "%SgA,vSvDB")
|
||||
(match_operand:DI 2 "gcn_alu_operand" " SgC, v")))
|
||||
(clobber (match_scratch:BI 3 "= cs, X"))]
|
||||
""
|
||||
"@
|
||||
s_<mnemonic>0\t%0, %1, %2
|
||||
#
|
||||
#"
|
||||
"reload_completed && gcn_vgpr_register_operand (operands[0], DImode)"
|
||||
[(parallel [(set (match_dup 4)
|
||||
|
|
@ -1495,7 +1491,7 @@
|
|||
operands[8] = gcn_operand_part (DImode, operands[1], 1);
|
||||
operands[9] = gcn_operand_part (DImode, operands[2], 1);
|
||||
}
|
||||
[(set_attr "type" "sop2,vop2,vop2")
|
||||
[(set_attr "type" "sop2,vop2")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn "<expander>di3"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue