aarch64: Add support for GCS system registers with the +gcs modifier
Given the introduction of system registers associated with the Guarded Control Stack extension to Armv9.4-a in Binutils and their reliance on the `+gcs' modifier, we implement the necessary changes in GCC to allow for them to be recognized by the compiler. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (gcs): New. * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New. (TARGET_THE): Likewise. * doc/invoke.texi (AArch64 Options): Describe GCS.
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@ -163,4 +163,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
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AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
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AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
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#undef AARCH64_OPT_EXTENSION
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@ -265,6 +265,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
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#define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
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#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
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#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
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#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS)
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/* The current function is a normal non-streaming function. */
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#define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF)
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@ -465,6 +466,11 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
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enabled through +the. */
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#define TARGET_THE (AARCH64_ISA_THE)
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/* Armv9.4-A Guarded Control Stack extension system registers are
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enabled through +gcs. */
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#define TARGET_GCS (AARCH64_ISA_GCS)
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/* Standard register usage. */
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/* 31 64-bit general purpose registers R0-R30:
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@ -21363,6 +21363,8 @@ Enable the FEAT_SME_F64F64 extension to SME.
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Enable the Scalable Matrix Extension 2. This also enables SME instructions.
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@item d128
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Enable support for 128-bit system register read/write instructions.
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@item gcs
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Enable support for Armv9.4-a Guarded Control Stack extension.
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@item the
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Enable support for Armv8.9-a/9.4-a translation hardening extension.
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