i386.c: Tidy processor feature bitmasks.
* config/i386/i386.c: Tidy processor feature bitmasks. (m_P4_NOCONA): New. From-SVN: r176215
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
10b75750f2
commit
3a4ffde68c
3 changed files with 62 additions and 70 deletions
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@ -1,3 +1,8 @@
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2011-07-12 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c: Tidy processor feature bitmasks.
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(m_P4_NOCONA): New.
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2011-07-12 Andrew Pinski <pinskia@gmail.com>
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PR rtl-opt/49474
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@ -1880,30 +1880,31 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_486 (1<<PROCESSOR_I486)
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#define m_PENT (1<<PROCESSOR_PENTIUM)
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#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
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#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
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#define m_NOCONA (1<<PROCESSOR_NOCONA)
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#define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
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#define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
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#define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
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#define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
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#define m_COREI7 (m_COREI7_32 | m_COREI7_64)
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#define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
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#define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
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#define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
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#define m_ATOM (1<<PROCESSOR_ATOM)
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#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
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#define m_NOCONA (1<<PROCESSOR_NOCONA)
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#define m_P4_NOCONA (m_PENT4 | m_NOCONA)
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#define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
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#define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
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#define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
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#define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
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#define m_COREI7 (m_COREI7_32 | m_COREI7_64)
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#define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
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#define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
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#define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
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#define m_ATOM (1<<PROCESSOR_ATOM)
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#define m_GEODE (1<<PROCESSOR_GEODE)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K8 (1<<PROCESSOR_K8)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
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#define m_BDVER1 (1<<PROCESSOR_BDVER1)
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#define m_BDVER2 (1<<PROCESSOR_BDVER2)
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#define m_BTVER1 (1<<PROCESSOR_BTVER1)
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#define m_BDVER (m_BDVER1 | m_BDVER2)
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#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1)
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#define m_GEODE (1<<PROCESSOR_GEODE)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K8 (1<<PROCESSOR_K8)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
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#define m_BDVER1 (1<<PROCESSOR_BDVER1)
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#define m_BDVER2 (1<<PROCESSOR_BDVER2)
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#define m_BDVER (m_BDVER1 | m_BDVER2)
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#define m_BTVER1 (1<<PROCESSOR_BTVER1)
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#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1)
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#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
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#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
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@ -1922,18 +1923,16 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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negatively, so enabling for Generic64 seems like good code size
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tradeoff. We can't enable it for 32bit generic because it does not
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work well with PPro base chips. */
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m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2I7_64 | m_GENERIC64,
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m_386 | m_CORE2I7_64 | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC64,
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/* X86_TUNE_PUSH_MEMORY */
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m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
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| m_NOCONA | m_CORE2I7 | m_GENERIC,
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m_386 | m_P4_NOCONA | m_CORE2I7 | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_ZERO_EXTEND_WITH_AND */
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m_486 | m_PENT,
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/* X86_TUNE_UNROLL_STRLEN */
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m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
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| m_CORE2I7 | m_GENERIC,
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m_486 | m_PENT | m_PPRO | m_ATOM | m_CORE2I7 | m_K6 | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
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on simulation result. But after P4 was made, no performance benefit
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@ -1945,13 +1944,11 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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~m_386,
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/* X86_TUNE_USE_SAHF */
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m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1
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| m_PENT4 | m_NOCONA | m_CORE2I7 | m_GENERIC,
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m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC,
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/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
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partial dependencies. */
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m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
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| m_CORE2I7 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
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m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GEODE | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
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register stalls on Generic32 compilation setting as well. However
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@ -1970,13 +1967,13 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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m_386 | m_486 | m_K6_GEODE,
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/* X86_TUNE_USE_SIMODE_FIOP */
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~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2I7 | m_GENERIC),
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~(m_PENT | m_PPRO | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC),
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/* X86_TUNE_USE_MOV0 */
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m_K6,
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/* X86_TUNE_USE_CLTD */
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~(m_PENT | m_ATOM | m_K6 | m_CORE2I7 | m_GENERIC),
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~(m_PENT | m_CORE2I7 | m_ATOM | m_K6 | m_GENERIC),
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/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
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m_PENT4,
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@ -1991,14 +1988,13 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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~(m_PENT | m_PPRO),
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/* X86_TUNE_PROMOTE_QIMODE */
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m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
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| m_CORE2I7 | m_GENERIC /* | m_PENT4 ? */,
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m_386 | m_486 | m_PENT | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_FAST_PREFIX */
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~(m_PENT | m_486 | m_386),
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~(m_386 | m_486 | m_PENT),
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/* X86_TUNE_SINGLE_STRINGOP */
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m_386 | m_PENT4 | m_NOCONA,
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m_386 | m_P4_NOCONA,
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/* X86_TUNE_QIMODE_MATH */
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~0,
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@ -2033,11 +2029,10 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
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for DFmode copies */
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~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2I7
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| m_GENERIC | m_GEODE),
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~(m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GEODE | m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
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/* X86_TUNE_PARTIAL_REG_DEPENDENCY */
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m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2I7 | m_GENERIC,
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m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
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conflict here in between PPro/Pentium4 based chips that thread 128bit
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@ -2048,14 +2043,13 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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shows that disabling this option on P4 brings over 20% SPECfp regression,
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while enabling it on K8 brings roughly 2.4% regression that can be partly
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masked by careful scheduling of moves. */
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m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2I7 | m_GENERIC | m_AMDFAM10
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| m_BDVER,
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m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMDFAM10 | m_BDVER | m_GENERIC,
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/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
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m_AMDFAM10 | m_BDVER | m_BTVER1 | m_COREI7,
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m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER1,
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/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
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m_BDVER | m_COREI7,
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m_COREI7 | m_BDVER,
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/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
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m_BDVER ,
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@ -2070,16 +2064,16 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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m_AMD_MULTIPLE,
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/* X86_TUNE_SSE_LOAD0_BY_PXOR */
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m_PPRO | m_PENT4 | m_NOCONA,
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m_PPRO | m_P4_NOCONA,
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/* X86_TUNE_MEMORY_MISMATCH_STALL */
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m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2I7 | m_GENERIC,
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m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_PROLOGUE_USING_MOVE */
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m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2I7 | m_GENERIC,
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m_PPRO | m_CORE2I7 | m_ATOM | m_ATHLON_K8 | m_GENERIC,
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/* X86_TUNE_EPILOGUE_USING_MOVE */
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m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2I7 | m_GENERIC,
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m_PPRO | m_CORE2I7 | m_ATOM | m_ATHLON_K8 | m_GENERIC,
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/* X86_TUNE_SHIFT1 */
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~m_486,
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@ -2095,34 +2089,31 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
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than 4 branch instructions in the 16 byte window. */
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m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2I7
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| m_GENERIC,
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m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_SCHEDULE */
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m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2I7
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| m_GENERIC,
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m_PENT | m_PPRO | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_USE_BT */
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m_AMD_MULTIPLE | m_ATOM | m_CORE2I7 | m_GENERIC,
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m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_USE_INCDEC */
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~(m_PENT4 | m_NOCONA | m_CORE2I7 | m_GENERIC | m_ATOM),
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~(m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_GENERIC),
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/* X86_TUNE_PAD_RETURNS */
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m_AMD_MULTIPLE | m_CORE2I7 | m_GENERIC,
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m_CORE2I7 | m_AMD_MULTIPLE | m_GENERIC,
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/* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
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m_ATOM,
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/* X86_TUNE_EXT_80387_CONSTANTS */
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m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
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| m_CORE2I7 | m_GENERIC,
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m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC,
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/* X86_TUNE_SHORTEN_X87_SSE */
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~m_K8,
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/* X86_TUNE_AVOID_VECTOR_DECODE */
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m_K8 | m_CORE2I7_64 | m_GENERIC64,
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m_CORE2I7_64 | m_K8 | m_GENERIC64,
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/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
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and SImode multiply, but 386 and 486 do HImode multiply faster. */
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@ -2130,11 +2121,11 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
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vector path on AMD machines. */
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m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER | m_BTVER1,
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m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64,
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/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
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machines. */
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m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER | m_BTVER1,
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m_CORE2I7_64 | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1 | m_GENERIC64,
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/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
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than a MOV. */
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@ -2151,7 +2142,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
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from FP to FP. */
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m_AMDFAM10 | m_CORE2I7 | m_GENERIC,
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m_CORE2I7 | m_AMDFAM10 | m_GENERIC,
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/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
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from integer to FP. */
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@ -2160,7 +2151,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
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with a subsequent conditional jump instruction into a single
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compare-and-branch uop. */
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m_BDVER ,
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m_BDVER,
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/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
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will impact LEA instruction selection. */
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@ -2203,12 +2194,10 @@ static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
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};
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static const unsigned int x86_accumulate_outgoing_args
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= m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2I7
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| m_GENERIC;
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= m_PPRO | m_P4_NOCONA | m_ATOM | m_CORE2I7 | m_AMD_MULTIPLE | m_GENERIC;
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static const unsigned int x86_arch_always_fancy_math_387
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= m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
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| m_NOCONA | m_CORE2I7 | m_GENERIC;
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= m_PENT | m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC;
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static const unsigned int x86_avx256_split_unaligned_load
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= m_COREI7 | m_GENERIC;
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@ -10963,9 +10963,7 @@
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(set_attr "modrm" "0")])
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(define_expand "indirect_jump"
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[(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
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""
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"")
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[(set (pc) (match_operand 0 "nonimmediate_operand" ""))])
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(define_insn "*indirect_jump"
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[(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))]
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