config.gcc (sparc*-*-*): Accept leon3 processor.
* config.gcc (sparc*-*-*): Accept leon3 processor. (sparc-leon*-*): Merge with sparc*-*-* and add leon3 support. * doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry. * config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3. * config/sparc/sparc.opt (enum processor_type): Add leon3. (mfix-ut699): Adjust comment. * config/sparc/sparc.h (TARGET_CPU_leon3): New define. (CPP_CPU32_DEFAULT_SPEC): Add leon3 support. (CPP_CPU_SPEC): Likewise. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (leon3_cost): New constant. (sparc_option_override): Add leon3 support. (mem_ref): New function. (sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled. (sparc_do_work_around_errata): Look into the instruction in the delay slot and adjust accordingly. Add fix for the data cache nullify issues of the UT699. Change insertion position for the NOP. * config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete. (leon3_load): New reservation. (leon_store): Bump latency to 2. (grfpu): New automaton. (grfpu_alu): New unit. (grfpu_ds): Likewise. (leon_fp_alu): Adjust. (leon_fp_mult): Delete. (leon_fp_div): Split into leon_fp_divs and leon_fp_divd. (leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd. * config/sparc/sparc.md (cpu): Add leon3. * config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699. (swapsi): Likewise. (atomic_test_and_set): Likewise. (ldstub): Likewise. From-SVN: r201147
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
16a1d8fe29
commit
38ae58ca9f
10 changed files with 225 additions and 72 deletions
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@ -1,3 +1,38 @@
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2013-07-22 Eric Botcazou <ebotcazou@adacore.com>
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* config.gcc (sparc*-*-*): Accept leon3 processor.
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(sparc-leon*-*): Merge with sparc*-*-* and add leon3 support.
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* doc/invoke.texi (SPARC Options): Adjust -mfix-ut699 entry.
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* config/sparc/sparc-opts.h (enum processor_type): Add PROCESSOR_LEON3.
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* config/sparc/sparc.opt (enum processor_type): Add leon3.
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(mfix-ut699): Adjust comment.
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* config/sparc/sparc.h (TARGET_CPU_leon3): New define.
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(CPP_CPU32_DEFAULT_SPEC): Add leon3 support.
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(CPP_CPU_SPEC): Likewise.
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(ASM_CPU_SPEC): Likewise.
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* config/sparc/sparc.c (leon3_cost): New constant.
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(sparc_option_override): Add leon3 support.
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(mem_ref): New function.
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(sparc_gate_work_around_errata): Return true if -mfix-ut699 is enabled.
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(sparc_do_work_around_errata): Look into the instruction in the delay
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slot and adjust accordingly. Add fix for the data cache nullify issues
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of the UT699. Change insertion position for the NOP.
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* config/sparc/leon.md (leon_fpalu, leon_fpmds, write_buf): Delete.
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(leon3_load): New reservation.
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(leon_store): Bump latency to 2.
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(grfpu): New automaton.
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(grfpu_alu): New unit.
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(grfpu_ds): Likewise.
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(leon_fp_alu): Adjust.
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(leon_fp_mult): Delete.
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(leon_fp_div): Split into leon_fp_divs and leon_fp_divd.
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(leon_fp_sqrt): Split into leon_fp_sqrts and leon_fp_sqrtd.
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* config/sparc/sparc.md (cpu): Add leon3.
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* config/sparc/sync.md (atomic_exchangesi): Disable if -mfix-ut699.
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(swapsi): Likewise.
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(atomic_test_and_set): Likewise.
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(ldstub): Likewise.
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2013-07-22 Jürgen Urban <JuergenUrban@gmx.de>
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* config.gcc (mips*-*-*): Add --with-fpu support. Make single the
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@ -3662,7 +3662,7 @@ case "${target}" in
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case ${val} in
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"" | sparc | sparcv9 | sparc64 \
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| v7 | cypress \
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| v8 | supersparc | hypersparc | leon \
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| v8 | supersparc | hypersparc | leon | leon3 \
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| sparclite | f930 | f934 | sparclite86x \
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| sparclet | tsc701 \
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| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
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@ -3819,15 +3819,6 @@ case ${target} in
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cxx_target_objs="${cxx_target_objs} sh-c.o"
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;;
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sparc-leon*-*)
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if test x$with_tune = x ; then
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with_tune=leon;
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fi
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# The SPARC port checks this value at compile-time.
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target_cpu_default2="TARGET_CPU_$with_cpu"
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;;
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sparc*-*-*)
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# Some standard aliases.
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case x$with_cpu in
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@ -3839,6 +3830,17 @@ case ${target} in
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;;
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esac
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if test x$with_tune = x ; then
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case ${target} in
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*-leon-*)
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with_tune=leon
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;;
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*-leon[3-9]*)
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with_tune=leon3
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;;
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esac
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fi
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# The SPARC port checks this value at compile-time.
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target_cpu_default2="TARGET_CPU_$with_cpu"
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;;
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@ -17,40 +17,48 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Leon is a single-issue processor.
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(define_automaton "leon")
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(define_cpu_unit "leon_memory, leon_fpalu" "leon")
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(define_cpu_unit "leon_fpmds" "leon")
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(define_cpu_unit "write_buf" "leon")
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(define_cpu_unit "leon_memory" "leon")
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(define_insn_reservation "leon_load" 1
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "load,sload,fpload"))
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(and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))
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"leon_memory")
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(define_insn_reservation "leon_store" 1
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "store,fpstore"))
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"leon_memory+write_buf")
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(define_insn_reservation "leon_fp_alu" 1
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "fp,fpmove"))
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"leon_fpalu, nothing")
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;; Use a double reservation to work around the load pipeline hazard on UT699.
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(define_insn_reservation "leon3_load" 1
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(and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
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"leon_memory*2")
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(define_insn_reservation "leon_fp_mult" 1
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "fpmul"))
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"leon_fpmds, nothing")
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(define_insn_reservation "leon_store" 2
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
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"leon_memory*2")
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(define_insn_reservation "leon_fp_div" 16
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "fpdivs,fpdivd"))
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"leon_fpmds, nothing*15")
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;; This describes Gaisler Research's FPU
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(define_insn_reservation "leon_fp_sqrt" 23
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(and (eq_attr "cpu" "leon")
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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"leon_fpmds, nothing*21")
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(define_automaton "grfpu")
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(define_cpu_unit "grfpu_alu" "grfpu")
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(define_cpu_unit "grfpu_ds" "grfpu")
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(define_insn_reservation "leon_fp_alu" 4
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
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"grfpu_alu, nothing*3")
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(define_insn_reservation "leon_fp_divs" 16
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
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"grfpu_ds*14, nothing*2")
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(define_insn_reservation "leon_fp_divd" 17
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
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"grfpu_ds*15, nothing*2")
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(define_insn_reservation "leon_fp_sqrts" 24
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
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"grfpu_ds*22, nothing*2")
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(define_insn_reservation "leon_fp_sqrtd" 25
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(and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
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"grfpu_ds*23, nothing*2")
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@ -30,6 +30,7 @@ enum processor_type {
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PROCESSOR_SUPERSPARC,
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PROCESSOR_HYPERSPARC,
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PROCESSOR_LEON,
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PROCESSOR_LEON3,
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PROCESSOR_SPARCLITE,
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PROCESSOR_F930,
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PROCESSOR_F934,
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@ -226,6 +226,30 @@ struct processor_costs leon_costs = {
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0, /* shift penalty */
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};
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static const
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struct processor_costs leon3_costs = {
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COSTS_N_INSNS (1), /* int load */
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COSTS_N_INSNS (1), /* int signed load */
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COSTS_N_INSNS (1), /* int zeroed load */
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COSTS_N_INSNS (1), /* float load */
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COSTS_N_INSNS (1), /* fmov, fneg, fabs */
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COSTS_N_INSNS (1), /* fadd, fsub */
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COSTS_N_INSNS (1), /* fcmp */
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COSTS_N_INSNS (1), /* fmov, fmovr */
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COSTS_N_INSNS (1), /* fmul */
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COSTS_N_INSNS (14), /* fdivs */
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COSTS_N_INSNS (15), /* fdivd */
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COSTS_N_INSNS (22), /* fsqrts */
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COSTS_N_INSNS (23), /* fsqrtd */
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COSTS_N_INSNS (5), /* imul */
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COSTS_N_INSNS (5), /* imulX */
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0, /* imul bit factor */
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COSTS_N_INSNS (35), /* idiv */
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COSTS_N_INSNS (35), /* idivX */
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COSTS_N_INSNS (1), /* movcc/movr */
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0, /* shift penalty */
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};
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static const
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struct processor_costs sparclet_costs = {
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COSTS_N_INSNS (3), /* int load */
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@ -805,17 +829,31 @@ char sparc_hard_reg_printed[8];
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Return the memory reference contained in X if any, zero otherwise. */
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static rtx
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mem_ref (rtx x)
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{
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if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND)
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x = XEXP (x, 0);
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if (MEM_P (x))
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return x;
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return NULL_RTX;
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}
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/* We use a machine specific pass to enable workarounds for errata.
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We need to have the (essentially) final form of the insn stream in order
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to properly detect the various hazards. Therefore, this machine specific
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pass runs as late as possible. The pass is inserted in the pass pipeline
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at the end of sparc_options_override. */
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at the end of sparc_option_override. */
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static bool
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sparc_gate_work_around_errata (void)
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{
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/* The only erratum we handle for now is that of the AT697F processor. */
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return sparc_fix_at697f != 0;
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/* The only errata we handle are those of the AT697F and UT699. */
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return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
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}
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static unsigned int
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@ -823,14 +861,22 @@ sparc_do_work_around_errata (void)
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{
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rtx insn, next;
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/* Force all instructions to be split into their final form. */
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split_all_insns_noflow ();
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/* Now look for specific patterns in the insn stream. */
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for (insn = get_insns (); insn; insn = next)
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{
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bool insert_nop = false;
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rtx set;
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/* Look into the instruction in a delay slot. */
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if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
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insn = XVECEXP (PATTERN (insn), 0, 1);
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/* Look for a single-word load into an odd-numbered FP register. */
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if (NONJUMP_INSN_P (insn)
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if (sparc_fix_at697f
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&& NONJUMP_INSN_P (insn)
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&& (set = single_set (insn)) != NULL_RTX
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&& GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
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&& MEM_P (SET_SRC (set))
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@ -845,13 +891,13 @@ sparc_do_work_around_errata (void)
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/* If the insn has a delay slot, then it cannot be problematic. */
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next = next_active_insn (insn);
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if (!next)
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break;
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if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
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code = -1;
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else
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{
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extract_insn (next);
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code = INSN_CODE (next);
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}
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continue;
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extract_insn (next);
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code = INSN_CODE (next);
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switch (code)
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{
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@ -897,12 +943,60 @@ sparc_do_work_around_errata (void)
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break;
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}
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}
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/* Look for a single-word load into an integer register. */
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else if (sparc_fix_ut699
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&& NONJUMP_INSN_P (insn)
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&& (set = single_set (insn)) != NULL_RTX
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&& GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
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&& mem_ref (SET_SRC (set)) != NULL_RTX
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&& REG_P (SET_DEST (set))
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&& REGNO (SET_DEST (set)) < 32)
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{
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/* There is no problem if the second memory access has a data
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dependency on the first single-cycle load. */
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rtx x = SET_DEST (set);
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/* If the insn has a delay slot, then it cannot be problematic. */
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next = next_active_insn (insn);
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if (!next)
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break;
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if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
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continue;
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/* Look for a second memory access to/from an integer register. */
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if ((set = single_set (next)) != NULL_RTX)
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{
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rtx src = SET_SRC (set);
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rtx dest = SET_DEST (set);
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rtx mem;
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/* LDD is affected. */
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if ((mem = mem_ref (src)) != NULL_RTX
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&& REG_P (dest)
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&& REGNO (dest) < 32
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&& !reg_mentioned_p (x, XEXP (mem, 0)))
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insert_nop = true;
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/* STD is *not* affected. */
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else if ((mem = mem_ref (dest)) != NULL_RTX
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&& GET_MODE_SIZE (GET_MODE (mem)) <= 4
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&& (src == const0_rtx
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|| (REG_P (src)
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&& REGNO (src) < 32
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&& REGNO (src) != REGNO (x)))
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&& !reg_mentioned_p (x, XEXP (mem, 0)))
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insert_nop = true;
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}
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}
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else
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next = NEXT_INSN (insn);
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if (insert_nop)
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emit_insn_after (gen_nop (), insn);
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emit_insn_before (gen_nop (), next);
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}
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return 0;
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}
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@ -1019,6 +1113,7 @@ sparc_option_override (void)
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{ TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
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{ TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
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{ TARGET_CPU_leon, PROCESSOR_LEON },
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{ TARGET_CPU_leon3, PROCESSOR_LEON3 },
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{ TARGET_CPU_sparclite, PROCESSOR_F930 },
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{ TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
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{ TARGET_CPU_sparclet, PROCESSOR_TSC701 },
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@ -1033,7 +1128,7 @@ sparc_option_override (void)
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};
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const struct cpu_default *def;
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/* Table of values for -m{cpu,tune}=. This must match the order of
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the PROCESSOR_* enumeration. */
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the enum processor_type in sparc-opts.h. */
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static struct cpu_table {
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const char *const name;
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const int disable;
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@ -1047,6 +1142,7 @@ sparc_option_override (void)
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{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
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/* LEON */
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{ "leon", MASK_ISA, MASK_V8|MASK_FPU },
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{ "leon3", MASK_ISA, MASK_V8|MASK_FPU },
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{ "sparclite", MASK_ISA, MASK_SPARCLITE },
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/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
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{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
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@ -1295,6 +1391,9 @@ sparc_option_override (void)
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case PROCESSOR_LEON:
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sparc_costs = &leon_costs;
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break;
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case PROCESSOR_LEON3:
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sparc_costs = &leon3_costs;
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break;
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case PROCESSOR_SPARCLET:
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case PROCESSOR_TSC701:
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sparc_costs = &sparclet_costs;
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|
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@ -136,21 +136,22 @@ extern enum cmodel sparc_cmodel;
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#define TARGET_CPU_supersparc 2
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#define TARGET_CPU_hypersparc 3
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#define TARGET_CPU_leon 4
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#define TARGET_CPU_sparclite 5
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#define TARGET_CPU_f930 5 /* alias */
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#define TARGET_CPU_f934 5 /* alias */
|
||||
#define TARGET_CPU_sparclite86x 6
|
||||
#define TARGET_CPU_sparclet 7
|
||||
#define TARGET_CPU_tsc701 7 /* alias */
|
||||
#define TARGET_CPU_v9 8 /* generic v9 implementation */
|
||||
#define TARGET_CPU_sparcv9 8 /* alias */
|
||||
#define TARGET_CPU_sparc64 8 /* alias */
|
||||
#define TARGET_CPU_ultrasparc 9
|
||||
#define TARGET_CPU_ultrasparc3 10
|
||||
#define TARGET_CPU_niagara 11
|
||||
#define TARGET_CPU_niagara2 12
|
||||
#define TARGET_CPU_niagara3 13
|
||||
#define TARGET_CPU_niagara4 14
|
||||
#define TARGET_CPU_leon3 5
|
||||
#define TARGET_CPU_sparclite 6
|
||||
#define TARGET_CPU_f930 6 /* alias */
|
||||
#define TARGET_CPU_f934 6 /* alias */
|
||||
#define TARGET_CPU_sparclite86x 7
|
||||
#define TARGET_CPU_sparclet 8
|
||||
#define TARGET_CPU_tsc701 8 /* alias */
|
||||
#define TARGET_CPU_v9 9 /* generic v9 implementation */
|
||||
#define TARGET_CPU_sparcv9 9 /* alias */
|
||||
#define TARGET_CPU_sparc64 9 /* alias */
|
||||
#define TARGET_CPU_ultrasparc 10
|
||||
#define TARGET_CPU_ultrasparc3 11
|
||||
#define TARGET_CPU_niagara 12
|
||||
#define TARGET_CPU_niagara2 13
|
||||
#define TARGET_CPU_niagara3 14
|
||||
#define TARGET_CPU_niagara4 15
|
||||
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|
||||
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
|
||||
|
|
@ -232,7 +233,8 @@ extern enum cmodel sparc_cmodel;
|
|||
#define ASM_CPU32_DEFAULT_SPEC ""
|
||||
#endif
|
||||
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_leon
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
|
||||
|| TARGET_CPU_DEFAULT == TARGET_CPU_leon3
|
||||
#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
|
||||
#define ASM_CPU32_DEFAULT_SPEC ""
|
||||
#endif
|
||||
|
|
@ -282,6 +284,7 @@ extern enum cmodel sparc_cmodel;
|
|||
%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
|
||||
%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
|
||||
%{mcpu=leon:-D__leon__ -D__sparc_v8__} \
|
||||
%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
|
||||
%{mcpu=v9:-D__sparc_v9__} \
|
||||
%{mcpu=ultrasparc:-D__sparc_v9__} \
|
||||
%{mcpu=ultrasparc3:-D__sparc_v9__} \
|
||||
|
|
@ -330,6 +333,7 @@ extern enum cmodel sparc_cmodel;
|
|||
%{mcpu=supersparc:-Av8} \
|
||||
%{mcpu=hypersparc:-Av8} \
|
||||
%{mcpu=leon:-Av8} \
|
||||
%{mcpu=leon3:-Av8} \
|
||||
%{mv8plus:-Av8plus} \
|
||||
%{mcpu=v9:-Av9} \
|
||||
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
|
||||
|
|
|
|||
|
|
@ -206,7 +206,7 @@
|
|||
;; 'f' for all DF/TFmode values, including those that are specific to the v8.
|
||||
|
||||
;; Attribute for cpu type.
|
||||
;; These must match the values for enum processor_type in sparc.h.
|
||||
;; These must match the values of the enum processor_type in sparc-opts.h.
|
||||
(define_attr "cpu"
|
||||
"v7,
|
||||
cypress,
|
||||
|
|
@ -214,6 +214,7 @@
|
|||
supersparc,
|
||||
hypersparc,
|
||||
leon,
|
||||
leon3,
|
||||
sparclite,
|
||||
f930,
|
||||
f934,
|
||||
|
|
|
|||
|
|
@ -145,6 +145,9 @@ Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
|
|||
EnumValue
|
||||
Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
|
||||
|
||||
EnumValue
|
||||
Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
|
||||
|
||||
EnumValue
|
||||
Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
|
||||
|
||||
|
|
@ -203,7 +206,7 @@ Enable workaround for single erratum of AT697F processor
|
|||
|
||||
mfix-ut699
|
||||
Target Report RejectNegative Var(sparc_fix_ut699)
|
||||
Enable workarounds for the FP errata of the UT699 processor
|
||||
Enable workarounds for the errata of the UT699 processor
|
||||
|
||||
Mask(LONG_DOUBLE_128)
|
||||
;; Use 128-bit long double
|
||||
|
|
|
|||
|
|
@ -220,7 +220,7 @@
|
|||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")
|
||||
(match_operand:SI 3 "const_int_operand" "")]
|
||||
"TARGET_V8 || TARGET_V9"
|
||||
"(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
|
||||
{
|
||||
enum memmodel model = (enum memmodel) INTVAL (operands[3]);
|
||||
|
||||
|
|
@ -236,7 +236,7 @@
|
|||
UNSPECV_SWAP))
|
||||
(set (match_dup 1)
|
||||
(match_operand:SI 2 "register_operand" "0"))]
|
||||
"TARGET_V8 || TARGET_V9"
|
||||
"(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
|
||||
"swap\t%1, %0"
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
|
|
@ -244,7 +244,7 @@
|
|||
[(match_operand:QI 0 "register_operand" "")
|
||||
(match_operand:QI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" "")]
|
||||
""
|
||||
"!sparc_fix_ut699"
|
||||
{
|
||||
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
|
||||
rtx ret;
|
||||
|
|
@ -268,6 +268,6 @@
|
|||
(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
|
||||
UNSPECV_LDSTUB))
|
||||
(set (match_dup 1) (const_int -1))]
|
||||
""
|
||||
"!sparc_fix_ut699"
|
||||
"ldstub\t%1, %0"
|
||||
[(set_attr "type" "multi")])
|
||||
|
|
|
|||
|
|
@ -19491,8 +19491,8 @@ processor (which corresponds to erratum #13 of the AT697E processor).
|
|||
|
||||
@item -mfix-ut699
|
||||
@opindex mfix-ut699
|
||||
Enable the documented workarounds for the floating-point errata of the UT699
|
||||
processor.
|
||||
Enable the documented workarounds for the floating-point errata and the data
|
||||
cache nullify errata of the UT699 processor.
|
||||
@end table
|
||||
|
||||
These @samp{-m} options are supported in addition to the above
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue