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RISC-V: Vector pesudoinsns with x0 operand to use imm 0

Browse source 
A couple of Vector pseudoinstructions use x0 scalar which could be
inefficient on wider uarches due to regfile crossing.

Instead use the imm 0 form, which should be functionally equivalent.

 pseudoinsn            orig insn with x0     this patch
 --------------------  --------------------  -------------------
 vneg.v vd,vs          vrsub.vx vd,vs,x0     vrsub.vi vd,vs,0
 vncvt.x.x.w vd,vs,vm  vnsrl.wx vd,vs,x0,vm  vnsrl.wi vd,vs,0,vm
 vwcvt.x.x.v vd,vs,vm  vwadd.vx vd,vs,x0,vm  (imm not supported)

gcc/ChangeLog:
	* config/riscv/vector.md: vncvt substitute vnsrl.
	vnsrl with x0 replace with immediate 0.
	vneg substitute vrsub.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Change
	expected pattern.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
This commit is contained in:
Vineet Gupta 2025-02-05 16:46:48 +05:30
parent 580f571be6
commit 3880271e94
37 changed files with 80 additions and 70 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
gcc/config/riscv/vector.md
View file

@ -3904,7 +3904,10 @@
(match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
(match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.v\t%0,%3%p1"
{
/* vneg.v = vrsub vd,vs,x0 = vrsub vd,vs,0. */
return (<CODE> == NEG) ? "vrsub.vi\t%0,%3,0%p1" : "v<insn>.v\t%0,%3%p1";
}
[(set_attr "type" "vialu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
@ -4258,7 +4261,13 @@
(match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vn<insn>.w%o4\t%0,%3,%4%p1"
{
/* vnsrl vd,vs,x0 = vnsrl vd,vs,0. */
if (REG_P (operands[4]) && REGNO (operands[4]) == 0)
return "vn<insn>.wi\t%0,%3,0%p1";
return "vn<insn>.w%o4\t%0,%3,%4%p1";
}
[(set_attr "type" "vnshift")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set_attr "spec_restriction" "none,none,thv,thv,none,none")])
@ -4279,7 +4288,8 @@
(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
(match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vncvt.x.x.w\t%0,%3%p1"
;; vncvt.x.x.w = vnsrl vd,vs,x0 = vnsrl vd,vs,0
"vnsrl.wi\t%0,%3,0%p1";
[(set_attr "type" "vnshift")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set_attr "vl_op_idx" "4")

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
View file

@ -10,8 +10,8 @@
/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
View file

@ -10,8 +10,8 @@
/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
View file

@ -10,8 +10,8 @@
/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
View file

@ -10,8 +10,8 @@
/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0,v0\.t} 12 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wi\tv[0-9]+,v[0-9]+,0\n} 8 } } */
/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
/* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
View file

@ -36,10 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
View file

@ -39,10 +39,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
View file

@ -36,10 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
View file

@ -36,10 +36,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 8 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
View file

@ -31,10 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
View file

@ -34,10 +34,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
View file

@ -31,10 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
View file

@ -31,10 +31,10 @@
TEST_ALL (DEF_LOOP)
/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } } */
/* NOTE: int abs operator is converted to vneg.v (or vsrub.vi) + vmax.vv */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi\tv[0-9]+,v[0-9]+,0,v0\.t} 6 } } */
/* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6 } } */
/* NOTE: int abs operator cannot combine the vmerge. */
/* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
View file

@ -3,4 +3,4 @@
#include "vncvt-template.h"
/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
View file

@ -3,4 +3,4 @@
#include "vncvt-template.h"
/* { dg-final { scan-assembler-times {\tvncvt.x.x.w} 10 } } */
/* { dg-final { scan-assembler-times {\tvnsrl.wi} 10 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
View file

@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
View file

@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
View file

@ -7,4 +7,4 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
View file

@ -4,6 +4,6 @@
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
View file

@ -4,6 +4,6 @@
#include "abs-template.h"
/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 } } */
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
View file

@ -3,5 +3,5 @@
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
View file

@ -3,5 +3,5 @@
#include "vneg-template.h"
/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
/* { dg-final { scan-assembler-times {\tvrsub\.vi} 4 } } */
/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
View file

@ -45,7 +45,7 @@ DEF_OP_V (neg, 128, int64_t, __builtin_abs)
DEF_OP_V (neg, 256, int64_t, __builtin_abs)
DEF_OP_V (neg, 512, int64_t, __builtin_abs)
/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 38 } } */
/* { dg-final { scan-assembler-times {vmax\.vv} 38 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
View file

@ -37,7 +37,7 @@ DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 128)
DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 256)
DEF_COND_FP_CONVERT (fncvt, df, uhi, uint16_t, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
View file

@ -19,7 +19,7 @@ DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 128)
DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 256)
DEF_COND_FP_CONVERT (fncvt, df, uqi, uint8_t, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
View file

@ -45,7 +45,7 @@ DEF_COND_UNOP (cond_neg, 128, v128di, -)
DEF_COND_UNOP (cond_neg, 256, v256di, -)
DEF_COND_UNOP (cond_neg, 512, v512di, -)
/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 38 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 38 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
View file

@ -55,7 +55,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128usi, 128)
DEF_COND_CONVERT (trunc, v256udi, v256usi, 256)
DEF_COND_CONVERT (trunc, v512udi, v512usi, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 46 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 46 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
View file

@ -37,7 +37,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128uhi, 128)
DEF_COND_CONVERT (trunc, v256udi, v256uhi, 256)
DEF_COND_CONVERT (trunc, v512udi, v512uhi, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 30 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
View file

@ -19,7 +19,7 @@ DEF_COND_CONVERT (trunc, v128udi, v128uqi, 128)
DEF_COND_CONVERT (trunc, v256udi, v256uqi, 256)
DEF_COND_CONVERT (trunc, v512udi, v512uqi, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 14 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi\s+v[0-9]+,\s*v[0-9]+,0,\s*v0.t} 14 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-assembler-not {vmerge} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
View file

@ -38,7 +38,7 @@ DEF_CONVERT (fncvt, double, uint16_t, 256)
DEF_CONVERT (fncvt, double, uint16_t, 512)
/* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 30 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 30 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
View file

@ -20,7 +20,7 @@ DEF_CONVERT (fncvt, double, uint8_t, 256)
DEF_CONVERT (fncvt, double, uint8_t, 512)
/* { dg-final { scan-assembler-times {vfncvt\.rtz\.x\.f.w} 14 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 28 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 28 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
View file

@ -53,5 +53,5 @@ DEF_OP_V (neg, 128, int64_t, -)
DEF_OP_V (neg, 256, int64_t, -)
DEF_OP_V (neg, 512, int64_t, -)
/* { dg-final { scan-assembler-times {vneg\.v\s+v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,\s*0} 42 } } */
/* { dg-final { scan-assembler-not {csrr} } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
View file

@ -55,7 +55,7 @@ DEF_CONVERT (trunc, uint64_t, uint32_t, 64)
DEF_CONVERT (trunc, uint64_t, uint32_t, 128)
DEF_CONVERT (trunc, uint64_t, uint32_t, 256)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 46 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 46 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
View file

@ -37,7 +37,7 @@ DEF_CONVERT (trunc, uint64_t, uint16_t, 128)
DEF_CONVERT (trunc, uint64_t, uint16_t, 256)
DEF_CONVERT (trunc, uint64_t, uint16_t, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 60 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 60 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
View file

@ -19,7 +19,7 @@ DEF_CONVERT (trunc, uint64_t, uint8_t, 128)
DEF_CONVERT (trunc, uint64_t, uint8_t, 256)
DEF_CONVERT (trunc, uint64_t, uint8_t, 512)
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 42 } } */
/* { dg-final { scan-assembler-times {vnsrl\.wi} 42 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */

2
gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
View file

@ -15,4 +15,4 @@
VDIV_WITH_LMUL (1, 16)
VDIV_WITH_LMUL (1, 32)
/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 2 } } */

24
gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
View file

@ -8,8 +8,8 @@
** ...
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/
@ -28,8 +28,8 @@ void f1 (void * in, void *out)
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
** ...
** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/
@ -51,8 +51,8 @@ void f2 (void * in, void *out)
** ...
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/
@ -72,8 +72,8 @@ void f3 (void * in, void *out)
** ...
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/
@ -92,8 +92,8 @@ void f4 (void * in, void *out)
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
** ...
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/
@ -115,8 +115,8 @@ void f5 (void * in, void *out)
** ...
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vneg\.v\tv[0-9]+,\s*v[0-9]+
** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0
** vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*0,\s*v0.t
** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
*/