PR target/105791: Add V1TI to V_128_256 for xop_pcmov_v1ti on x86_64.
This patch resolves PR target/105791 which is a regression that was accidentally introduced for my workaround to PR tree-optimization/10566. (a deeper problem in GCC's vectorizer creating VEC_COND_EXPR when it shouldn't). The latest issues is that by providing a vcond_mask_v1tiv1ti pattern in sse.md, the backend now calls ix86_expand_sse_movcc with V1TImode operands, which has a special case for TARGET_XOP to generate a vpcmov instruction. Unfortunately, there wasn't previously a V1TImode variant, xop_pcmov_v1ti, so we'd ICE. This is easily fixed by adding V1TImode (and V2TImode) to V_128_256 which is only used for defining XOP's vpcmov instruction. This in turn requires V1TI (and V2TI) to be supported by <avxsizesuffix> (though the use if <avxsizesuffix> in the names xop_pcmov_<mode><avxsizesuffix> seems unnecessary; the mode makes the name unique). 2022-06-02 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR target/105791 * config/i386/sse.md (V_128_256):Add V1TI and V2TI. (define_mode_attr avxsizesuffix): Add support for V1TI and V2TI. gcc/testsuite/ChangeLog PR target/105791 * gcc.target/i386/pr105791.c: New test case.
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2 changed files with 18 additions and 4 deletions
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@ -301,7 +301,8 @@
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;; All 128bit and 256bit vector modes
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(define_mode_iterator V_128_256
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[V32QI V16QI V16HI V8HI V8SI V4SI V4DI V2DI V16HF V8HF V8SF V4SF V4DF V2DF])
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[V32QI V16QI V16HI V8HI V8SI V4SI V4DI V2DI V2TI V1TI
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V16HF V8HF V8SF V4SF V4DF V2DF])
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;; All 512bit vector modes
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(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF])
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@ -897,9 +898,9 @@
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(V8HI "sse4_1") (V16HI "avx")])
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(define_mode_attr avxsizesuffix
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[(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512")
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(V32QI "256") (V16HI "256") (V8SI "256") (V4DI "256")
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(V16QI "") (V8HI "") (V4SI "") (V2DI "")
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[(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512") (V4TI "512")
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(V32QI "256") (V16HI "256") (V8SI "256") (V4DI "256") (V2TI "256")
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(V16QI "") (V8HI "") (V4SI "") (V2DI "") (V1TI "")
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(V32HF "512") (V16SF "512") (V8DF "512")
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(V16HF "256") (V8SF "256") (V4DF "256")
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(V8HF "") (V4SF "") (V2DF "")])
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13
gcc/testsuite/gcc.target/i386/pr105791.c
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13
gcc/testsuite/gcc.target/i386/pr105791.c
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@ -0,0 +1,13 @@
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2 -mxop" } */
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typedef __int128 __attribute__((__vector_size__ (sizeof (__int128)))) U;
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typedef int __attribute__((__vector_size__ (sizeof (int)))) V;
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U u;
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V v;
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U
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foo (void)
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{
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return (0 != __builtin_convertvector (v, U)) <= (0 != u);
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}
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