From 37d9074e12082132ae62c12fbe958c697f638c0a Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 29 Mar 2021 11:52:24 +0100 Subject: [PATCH] aarch64: PR target/99037 Fix RTL represntation in move_lo_quad patterns This patch fixes the RTL representation of the move_lo_quad patterns to use aarch64_simd_or_scalar_imm_zero for the zero part rather than a vec_duplicate of zero or a const_int 0. The expander that generates them is also adjusted so that we use and match the correct const_vector forms throughout. Co-Authored-By: Jakub Jelinek gcc/ChangeLog: PR target/99037 * config/aarch64/aarch64-simd.md (move_lo_quad_internal_): Use aarch64_simd_or_scalar_imm_zero to match zeroes. Remove pattern matching const_int 0. (move_lo_quad_internal_be_): Likewise. (move_lo_quad_): Update for the above. * config/aarch64/iterators.md (VQ_2E): Delete. gcc/testsuite/ChangeLog: PR target/99808 * gcc.target/aarch64/pr99808.c: New test. --- gcc/config/aarch64/aarch64-simd.md | 49 +++++----------------- gcc/config/aarch64/iterators.md | 3 -- gcc/testsuite/gcc.target/aarch64/pr99808.c | 14 +++++++ 3 files changed, 24 insertions(+), 42 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr99808.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 348a43d835d..d86e8e72f18 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1586,25 +1586,10 @@ ;; On big-endian this is { zeroes, operand } (define_insn "move_lo_quad_internal_" - [(set (match_operand:VQMOV_NO2E 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV_NO2E + [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") + (vec_concat:VQMOV (match_operand: 1 "register_operand" "w,r,r") - (vec_duplicate: (const_int 0))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - -(define_insn "move_lo_quad_internal_" - [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") - (vec_concat:VQ_2E - (match_operand: 1 "register_operand" "w,r,r") - (const_int 0)))] + (match_operand: 2 "aarch64_simd_or_scalar_imm_zero")))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" "@ dup\\t%d0, %1.d[0] @@ -1616,24 +1601,9 @@ ) (define_insn "move_lo_quad_internal_be_" - [(set (match_operand:VQMOV_NO2E 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV_NO2E - (vec_duplicate: (const_int 0)) - (match_operand: 1 "register_operand" "w,r,r")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - -(define_insn "move_lo_quad_internal_be_" - [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") - (vec_concat:VQ_2E - (const_int 0) + [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") + (vec_concat:VQMOV + (match_operand: 2 "aarch64_simd_or_scalar_imm_zero") (match_operand: 1 "register_operand" "w,r,r")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" "@ @@ -1647,13 +1617,14 @@ (define_expand "move_lo_quad_" [(match_operand:VQMOV 0 "register_operand") - (match_operand:VQMOV 1 "register_operand")] + (match_operand: 1 "register_operand")] "TARGET_SIMD" { + rtx zs = CONST0_RTX (mode); if (BYTES_BIG_ENDIAN) - emit_insn (gen_move_lo_quad_internal_be_ (operands[0], operands[1])); + emit_insn (gen_move_lo_quad_internal_be_ (operands[0], operands[1], zs)); else - emit_insn (gen_move_lo_quad_internal_ (operands[0], operands[1])); + emit_insn (gen_move_lo_quad_internal_ (operands[0], operands[1], zs)); DONE; } ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index fb6e228651e..5f5abd60525 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -125,9 +125,6 @@ ;; VQ without 2 element modes. (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF]) -;; Quad vector with only 2 element modes. -(define_mode_iterator VQ_2E [V2DI V2DF]) - ;; BFmode vector modes. (define_mode_iterator VBF [V4BF V8BF]) diff --git a/gcc/testsuite/gcc.target/aarch64/pr99808.c b/gcc/testsuite/gcc.target/aarch64/pr99808.c new file mode 100644 index 00000000000..4d7edab5c37 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr99808.c @@ -0,0 +1,14 @@ +/* PR target/99808 */ +/* PR target/99037 */ +/* { dg-do compile } */ +/* { dg-options "-Og -fweb -fno-forward-propagate -g" } */ + +#include + +float32x4_t +foo (void) +{ + float64x2_t arg2 = vcombine_f64 ((float64x1_t) 0UL, (float64x1_t) 1UL); + return vcvt_high_f32_f64 ((float32x2_t) 1UL, arg2); +} +