aarch64: Make use of RTL predicates
2020-11-10 Andrea Corallo <andrea.corallo@arm.com> * config/aarch64/aarch64.c (tls_symbolic_operand_type) (aarch64_load_symref_appropriately, aarch64_mov128_immediate) (aarch64_expand_mov_immediate) (aarch64_maybe_expand_sve_subreg_move) (aarch64_tls_referenced_p, aarch64_cannot_force_const_mem) (aarch64_base_register_rtx_p, aarch64_classify_index) (aarch64_classify_address, aarch64_symbolic_address_p) (aarch64_reinterpret_float_as_int, aarch64_float_const_rtx_p) (aarch64_can_const_movi_rtx_p, aarch64_select_cc_mode) (aarch64_print_operand, aarch64_label_mentioned_p) (aarch64_secondary_reload, aarch64_preferred_reload_class) (aarch64_address_cost, aarch64_tls_symbol_p) (aarch64_classify_symbol, aarch64_legitimate_pic_operand_p) (aarch64_legitimate_constant_p) (aarch64_sve_float_arith_immediate_p) (aarch64_sve_float_mul_immediate_p, aarch64_mov_operand_p) (fusion_load_store): Use RTL operands where possible.
This commit is contained in:
Andrea Corallo
parent
8c4e33d203
commit
3793ecc10f
1 changed files with 40 additions and 40 deletions
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@ -2985,7 +2985,7 @@ tls_symbolic_operand_type (rtx addr)
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enum tls_model tls_kind = TLS_MODEL_NONE;
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poly_int64 offset;
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addr = strip_offset_and_salt (addr, &offset);
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if (GET_CODE (addr) == SYMBOL_REF)
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if (SYMBOL_REF_P (addr))
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tls_kind = SYMBOL_REF_TLS_MODEL (addr);
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return tls_kind;
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@ -3126,7 +3126,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
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/* The operand is expected to be MEM. Whenever the related insn
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pattern changed, above code which calculate mem should be
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updated. */
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gcc_assert (GET_CODE (mem) == MEM);
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gcc_assert (MEM_P (mem));
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MEM_READONLY_P (mem) = 1;
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MEM_NOTRAP_P (mem) = 1;
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emit_insn (insn);
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@ -3169,7 +3169,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
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mem = XVECEXP (XEXP (SET_SRC (insn), 0), 0, 0);
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}
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gcc_assert (GET_CODE (mem) == MEM);
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gcc_assert (MEM_P (mem));
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MEM_READONLY_P (mem) = 1;
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MEM_NOTRAP_P (mem) = 1;
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emit_insn (insn);
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@ -4235,7 +4235,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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bool
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aarch64_mov128_immediate (rtx imm)
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{
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if (GET_CODE (imm) == CONST_INT)
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if (CONST_INT_P (imm))
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return true;
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gcc_assert (CONST_WIDE_INT_NUNITS (imm) == 2);
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@ -5099,8 +5099,8 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
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/* Check on what type of symbol it is. */
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scalar_int_mode int_mode;
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if ((GET_CODE (imm) == SYMBOL_REF
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|| GET_CODE (imm) == LABEL_REF
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if ((SYMBOL_REF_P (imm)
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|| LABEL_REF_P (imm)
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|| GET_CODE (imm) == CONST
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|| GET_CODE (imm) == CONST_POLY_INT)
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&& is_a <scalar_int_mode> (mode, &int_mode))
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@ -5390,9 +5390,9 @@ bool
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aarch64_maybe_expand_sve_subreg_move (rtx dest, rtx src)
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{
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gcc_assert (BYTES_BIG_ENDIAN);
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if (GET_CODE (dest) == SUBREG)
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if (SUBREG_P (dest))
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dest = SUBREG_REG (dest);
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if (GET_CODE (src) == SUBREG)
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if (SUBREG_P (src))
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src = SUBREG_REG (src);
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/* The optimization handles two single SVE REGs with different element
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@ -8536,7 +8536,7 @@ aarch64_tls_referenced_p (rtx x)
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FOR_EACH_SUBRTX (iter, array, x, ALL)
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{
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const_rtx x = *iter;
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if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
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if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
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return true;
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/* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
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TLS offsets, not real symbol references. */
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@ -8762,7 +8762,7 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
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poly_int64 offset;
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rtx base = strip_offset_and_salt (x, &offset);
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if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF)
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if (SYMBOL_REF_P (base) || LABEL_REF_P (base))
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{
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/* We checked for POLY_INT_CST offsets above. */
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if (aarch64_classify_symbol (base, offset.to_constant ())
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@ -8848,7 +8848,7 @@ static bool
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aarch64_base_register_rtx_p (rtx x, bool strict_p)
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{
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if (!strict_p
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&& GET_CODE (x) == SUBREG
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&& SUBREG_P (x)
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&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (x))])
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x = SUBREG_REG (x);
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@ -8867,7 +8867,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
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int shift;
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/* (reg:P) */
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if ((REG_P (x) || GET_CODE (x) == SUBREG)
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if ((REG_P (x) || SUBREG_P (x))
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&& GET_MODE (x) == Pmode)
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{
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type = ADDRESS_REG_REG;
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@ -8965,7 +8965,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
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return false;
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if (!strict_p
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&& GET_CODE (index) == SUBREG
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&& SUBREG_P (index)
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&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (index))])
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index = SUBREG_REG (index);
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@ -9261,8 +9261,8 @@ aarch64_classify_address (struct aarch64_address_info *info,
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{
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poly_int64 offset;
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rtx sym = strip_offset_and_salt (x, &offset);
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return ((GET_CODE (sym) == LABEL_REF
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|| (GET_CODE (sym) == SYMBOL_REF
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return ((LABEL_REF_P (sym)
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|| (SYMBOL_REF_P (sym)
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&& CONSTANT_POOL_ADDRESS_P (sym)
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&& aarch64_pcrelative_literal_loads)));
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}
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@ -9278,7 +9278,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
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poly_int64 offset;
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HOST_WIDE_INT const_offset;
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rtx sym = strip_offset_and_salt (info->offset, &offset);
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if (GET_CODE (sym) == SYMBOL_REF
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if (SYMBOL_REF_P (sym)
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&& offset.is_constant (&const_offset)
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&& (aarch64_classify_symbol (sym, const_offset)
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== SYMBOL_SMALL_ABSOLUTE))
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@ -9340,7 +9340,7 @@ aarch64_symbolic_address_p (rtx x)
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{
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poly_int64 offset;
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x = strip_offset_and_salt (x, &offset);
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return GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF;
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return SYMBOL_REF_P (x) || LABEL_REF_P (x);
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}
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/* Classify the base of symbolic expression X. */
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@ -9465,7 +9465,7 @@ aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *intval)
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}
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scalar_float_mode mode;
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if (GET_CODE (value) != CONST_DOUBLE
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if (!CONST_DOUBLE_P (value)
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|| !is_a <scalar_float_mode> (GET_MODE (value), &mode)
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|| GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
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/* Only support up to DF mode. */
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@ -9505,7 +9505,7 @@ aarch64_float_const_rtx_p (rtx x)
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mov/movk pairs over ldr/adrp pairs. */
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unsigned HOST_WIDE_INT ival;
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if (GET_CODE (x) == CONST_DOUBLE
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if (CONST_DOUBLE_P (x)
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&& SCALAR_FLOAT_MODE_P (mode)
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&& aarch64_reinterpret_float_as_int (x, &ival))
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{
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@ -9544,7 +9544,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode)
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scalar_int_mode imode;
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unsigned HOST_WIDE_INT ival;
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if (GET_CODE (x) == CONST_DOUBLE
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if (CONST_DOUBLE_P (x)
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&& SCALAR_FLOAT_MODE_P (mode))
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{
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if (!aarch64_reinterpret_float_as_int (x, &ival))
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@ -9556,7 +9556,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode)
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imode = int_mode_for_mode (mode).require ();
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}
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else if (GET_CODE (x) == CONST_INT
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else if (CONST_INT_P (x)
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&& is_a <scalar_int_mode> (mode, &imode))
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ival = INTVAL (x);
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else
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@ -9707,7 +9707,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
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the comparison will have to be swapped when we emit the assembly
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code. */
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if ((mode_x == SImode || mode_x == DImode)
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&& (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
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&& (REG_P (y) || SUBREG_P (y) || y == const0_rtx)
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&& (code_x == ASHIFT || code_x == ASHIFTRT
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|| code_x == LSHIFTRT
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|| code_x == ZERO_EXTEND || code_x == SIGN_EXTEND))
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@ -9716,7 +9716,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
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/* Similarly for a negated operand, but we can only do this for
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equalities. */
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if ((mode_x == SImode || mode_x == DImode)
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&& (REG_P (y) || GET_CODE (y) == SUBREG)
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&& (REG_P (y) || SUBREG_P (y))
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&& (code == EQ || code == NE)
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&& code_x == NEG)
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return CC_Zmode;
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@ -10510,7 +10510,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
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{
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machine_mode mode = GET_MODE (x);
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if (GET_CODE (x) != MEM
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if (!MEM_P (x)
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|| (code == 'y' && maybe_ne (GET_MODE_SIZE (mode), 16)))
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{
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output_operand_lossage ("invalid operand for '%%%c'", code);
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@ -10673,7 +10673,7 @@ aarch64_label_mentioned_p (rtx x)
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const char *fmt;
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int i;
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if (GET_CODE (x) == LABEL_REF)
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if (LABEL_REF_P (x))
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return true;
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/* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
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@ -10855,7 +10855,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
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/* If we have to disable direct literal pool loads and stores because the
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function is too big, then we need a scratch register. */
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if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
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if (MEM_P (x) && SYMBOL_REF_P (x) && CONSTANT_POOL_ADDRESS_P (x)
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&& (SCALAR_FLOAT_MODE_P (GET_MODE (x))
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|| targetm.vector_mode_supported_p (GET_MODE (x)))
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&& !aarch64_pcrelative_literal_loads)
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@ -11086,7 +11086,7 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
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rtx lhs = XEXP (x, 0);
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/* Look through a possible SUBREG introduced by ILP32. */
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if (GET_CODE (lhs) == SUBREG)
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if (SUBREG_P (lhs))
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lhs = SUBREG_REG (lhs);
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gcc_assert (REG_P (lhs));
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@ -11546,7 +11546,7 @@ aarch64_address_cost (rtx x,
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if (!aarch64_classify_address (&info, x, mode, false))
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{
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if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF)
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if (GET_CODE (x) == CONST || SYMBOL_REF_P (x))
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{
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/* This is a CONST or SYMBOL ref which will be split
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in a different way depending on the code model in use.
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@ -15947,7 +15947,7 @@ aarch64_tls_symbol_p (rtx x)
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return false;
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x = strip_salt (x);
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if (GET_CODE (x) != SYMBOL_REF)
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if (!SYMBOL_REF_P (x))
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return false;
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return SYMBOL_REF_TLS_MODEL (x) != 0;
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@ -16004,7 +16004,7 @@ aarch64_classify_symbol (rtx x, HOST_WIDE_INT offset)
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{
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x = strip_salt (x);
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if (GET_CODE (x) == LABEL_REF)
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if (LABEL_REF_P (x))
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{
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switch (aarch64_cmodel)
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{
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@ -16025,7 +16025,7 @@ aarch64_classify_symbol (rtx x, HOST_WIDE_INT offset)
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}
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}
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if (GET_CODE (x) == SYMBOL_REF)
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if (SYMBOL_REF_P (x))
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{
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if (aarch64_tls_symbol_p (x))
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return aarch64_classify_tls_symbol (x);
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@ -16105,7 +16105,7 @@ aarch64_legitimate_pic_operand_p (rtx x)
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{
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poly_int64 offset;
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x = strip_offset_and_salt (x, &offset);
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if (GET_CODE (x) == SYMBOL_REF)
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if (SYMBOL_REF_P (x))
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return false;
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return true;
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@ -16166,7 +16166,7 @@ aarch64_legitimate_constant_p (machine_mode mode, rtx x)
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return true;
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/* Label references are always constant. */
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if (GET_CODE (x) == LABEL_REF)
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if (LABEL_REF_P (x))
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return true;
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return false;
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@ -17609,7 +17609,7 @@ aarch64_sve_float_arith_immediate_p (rtx x, bool negate_p)
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REAL_VALUE_TYPE r;
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if (!const_vec_duplicate_p (x, &elt)
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|| GET_CODE (elt) != CONST_DOUBLE)
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|| !CONST_DOUBLE_P (elt))
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return false;
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r = *CONST_DOUBLE_REAL_VALUE (elt);
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@ -17633,7 +17633,7 @@ aarch64_sve_float_mul_immediate_p (rtx x)
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rtx elt;
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return (const_vec_duplicate_p (x, &elt)
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&& GET_CODE (elt) == CONST_DOUBLE
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&& CONST_DOUBLE_P (elt)
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&& (real_equal (CONST_DOUBLE_REAL_VALUE (elt), &dconsthalf)
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|| real_equal (CONST_DOUBLE_REAL_VALUE (elt), &dconst2)));
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}
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@ -18052,7 +18052,7 @@ aarch64_mov_operand_p (rtx x, machine_mode mode)
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}
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x = strip_salt (x);
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if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x))
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if (SYMBOL_REF_P (x) && mode == DImode && CONSTANT_ADDRESS_P (x))
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return true;
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if (TARGET_SVE && aarch64_sve_cnt_immediate_p (x))
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@ -22083,20 +22083,20 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset)
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{
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fusion = SCHED_FUSION_LD_SIGN_EXTEND;
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src = XEXP (src, 0);
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if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
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if (!MEM_P (src) || GET_MODE (src) != SImode)
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return SCHED_FUSION_NONE;
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}
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else if (GET_CODE (src) == ZERO_EXTEND)
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{
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fusion = SCHED_FUSION_LD_ZERO_EXTEND;
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src = XEXP (src, 0);
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if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
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if (!MEM_P (src) || GET_MODE (src) != SImode)
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return SCHED_FUSION_NONE;
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}
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if (GET_CODE (src) == MEM && REG_P (dest))
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if (MEM_P (src) && REG_P (dest))
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extract_base_offset_in_addr (src, base, offset);
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else if (GET_CODE (dest) == MEM && (REG_P (src) || src == const0_rtx))
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else if (MEM_P (dest) && (REG_P (src) || src == const0_rtx))
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{
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fusion = SCHED_FUSION_ST;
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extract_base_offset_in_addr (dest, base, offset);
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