From 35dd9a0e6d9491ee708c2d75ecf8d74aa40cbb39 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Fri, 11 May 2007 08:40:52 +0000 Subject: [PATCH] s390.md (GPR0_REGNUM, [...]): Constants added. 2007-05-11 Andreas Krebbel * config/s390/s390.md (GPR0_REGNUM, FPR0_REGNUM, FPR2_REGNUM, PFPO_CONVERT, PFPO_OP_TYPE_SF, PFPO_OP_TYPE_DF, PFPO_OP_TYPE_TF, PFPO_OP_TYPE_SD, PFPO_OP_TYPE_DD, PFPO_OP_TYPE_TD, PFPO_OP0_TYPE_SHIFT, PFPO_OP1_TYPE_SHIFT): Constants added. (DFP_ALL): Mode macro defined. ("*trunc2", "*trunc2", "*extend2", "*extend2"): Insn definitions added. ("trunc2", "trunc2", "extend2", "extend2"): Expanders added. From-SVN: r124614 --- gcc/ChangeLog | 14 ++++ gcc/config/s390/s390.md | 158 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 40867e98cdf..50e69eb1621 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2007-05-11 Andreas Krebbel + + * config/s390/s390.md (GPR0_REGNUM, FPR0_REGNUM, FPR2_REGNUM, + PFPO_CONVERT, PFPO_OP_TYPE_SF, PFPO_OP_TYPE_DF, PFPO_OP_TYPE_TF, + PFPO_OP_TYPE_SD, PFPO_OP_TYPE_DD, PFPO_OP_TYPE_TD, PFPO_OP0_TYPE_SHIFT, + PFPO_OP1_TYPE_SHIFT): Constants added. + (DFP_ALL): Mode macro defined. + ("*trunc2", "*trunc2", + "*extend2", "*extend2"): + Insn definitions added. + ("trunc2", "trunc2", + "extend2", "extend2"): + Expanders added. + 2007-05-10 Zdenek Dvorak PR tree-optimization/31885 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index c4ce3f46d68..3fac610c543 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -137,6 +137,8 @@ ;; Registers ;; +; Registers with special meaning + (define_constants [ ; Sibling call register. @@ -151,6 +153,37 @@ (TP_REGNUM 36) ]) +; Hardware register names + +(define_constants + [ + ; General purpose registers + (GPR0_REGNUM 0) + ; Floating point registers. + (FPR0_REGNUM 16) + (FPR2_REGNUM 18) + ]) + +;; +;; PFPO GPR0 argument format +;; + +(define_constants + [ + ; PFPO operation type + (PFPO_CONVERT 0x1000000) + ; PFPO operand types + (PFPO_OP_TYPE_SF 0x5) + (PFPO_OP_TYPE_DF 0x6) + (PFPO_OP_TYPE_TF 0x7) + (PFPO_OP_TYPE_SD 0x8) + (PFPO_OP_TYPE_DD 0x9) + (PFPO_OP_TYPE_TD 0xa) + ; Bitposition of operand types + (PFPO_OP0_TYPE_SHIFT 16) + (PFPO_OP1_TYPE_SHIFT 8) + ]) + ;; Instruction operand type as used in the Principles of Operation. ;; Used to determine defaults for length and other attribute values. @@ -221,6 +254,7 @@ (define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) (define_mode_macro BFP [TF DF SF]) (define_mode_macro DFP [TD DD]) +(define_mode_macro DFP_ALL [TD DD SD]) (define_mode_macro DSF [DF SF]) (define_mode_macro SD_SF [SF SD]) (define_mode_macro DD_DF [DF DD]) @@ -3437,6 +3471,130 @@ [(set_attr "op_type" "RRF") (set_attr "type" "fsimptf")]) +; Binary <-> Decimal floating point trunc patterns +; + +(define_insn "*trunc2" + [(set (reg:DFP_ALL FPR0_REGNUM) + (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP" + "pfpo") + +(define_insn "*trunc2" + [(set (reg:BFP FPR0_REGNUM) + (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP" + "pfpo") + +(define_expand "trunc2" + [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) + (set (reg:SI GPR0_REGNUM) (match_dup 2)) + (parallel + [(set (reg:DFP_ALL FPR0_REGNUM) + (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))]) + (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") + (reg:DFP_ALL FPR0_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" +{ + HOST_WIDE_INT flags; + + flags = (PFPO_CONVERT | + PFPO_OP_TYPE_ << PFPO_OP0_TYPE_SHIFT | + PFPO_OP_TYPE_ << PFPO_OP1_TYPE_SHIFT); + + operands[2] = GEN_INT (flags); +}) + +(define_expand "trunc2" + [(set (reg:DFP_ALL FPR2_REGNUM) + (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) + (set (reg:SI GPR0_REGNUM) (match_dup 2)) + (parallel + [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))]) + (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP + && GET_MODE_SIZE (mode) >= GET_MODE_SIZE (mode)" +{ + HOST_WIDE_INT flags; + + flags = (PFPO_CONVERT | + PFPO_OP_TYPE_ << PFPO_OP0_TYPE_SHIFT | + PFPO_OP_TYPE_ << PFPO_OP1_TYPE_SHIFT); + + operands[2] = GEN_INT (flags); +}) + +; +; Binary <-> Decimal floating point extend patterns +; + +(define_insn "*extend2" + [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP" + "pfpo") + +(define_insn "*extend2" + [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP" + "pfpo") + +(define_expand "extend2" + [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) + (set (reg:SI GPR0_REGNUM) (match_dup 2)) + (parallel + [(set (reg:DFP_ALL FPR0_REGNUM) + (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))]) + (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") + (reg:DFP_ALL FPR0_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (mode)" +{ + HOST_WIDE_INT flags; + + flags = (PFPO_CONVERT | + PFPO_OP_TYPE_ << PFPO_OP0_TYPE_SHIFT | + PFPO_OP_TYPE_ << PFPO_OP1_TYPE_SHIFT); + + operands[2] = GEN_INT (flags); +}) + +(define_expand "extend2" + [(set (reg:DFP_ALL FPR2_REGNUM) + (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) + (set (reg:SI GPR0_REGNUM) (match_dup 2)) + (parallel + [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) + (use (reg:SI GPR0_REGNUM)) + (clobber (reg:CC CC_REGNUM))]) + (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] + "TARGET_HARD_FLOAT && TARGET_DFP + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (mode)" +{ + HOST_WIDE_INT flags; + + flags = (PFPO_CONVERT | + PFPO_OP_TYPE_ << PFPO_OP0_TYPE_SHIFT | + PFPO_OP_TYPE_ << PFPO_OP1_TYPE_SHIFT); + + operands[2] = GEN_INT (flags); +}) + + ;; ;; ARITHMETIC OPERATIONS ;;