From 35dad9f1bc59f6615af16d0592ace268a34ea366 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 23 Feb 2002 13:45:36 +0000 Subject: [PATCH] h8300.md (mulqihi3): Tighten predicates to register_operand. * config/h8300/h8300.md (mulqihi3): Tighten predicates to register_operand. (mulhisi3): Likewise. (umulqisi3): Likewise. (umulhisi3): Likewise. From-SVN: r49994 --- gcc/ChangeLog | 8 ++++++++ gcc/config/h8300/h8300.md | 8 ++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6e6db2802c6..bc546ad344e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2002-02-23 Kazu Hirata + + * config/h8300/h8300.md (mulqihi3): Tighten predicates to + register_operand. + (mulhisi3): Likewise. + (umulqisi3): Likewise. + (umulhisi3): Likewise. + 2002-02-23 Neil Booth * cppinit.c (output_deps): Correct test for stdout output. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index b9dc6403222..d99103efa60 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -841,7 +841,7 @@ (define_insn "mulqihi3" [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0")) + (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))] "TARGET_H8300H || TARGET_H8300S" "mulxs.b %X2,%T0" @@ -850,7 +850,7 @@ (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0")) + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] "TARGET_H8300H || TARGET_H8300S" "mulxs.w %T2,%S0" @@ -859,7 +859,7 @@ (define_insn "umulqihi3" [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0")) + (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] "" "mulxu %X2,%T0" @@ -868,7 +868,7 @@ (define_insn "umulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0")) + (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] "TARGET_H8300H || TARGET_H8300S" "mulxu.w %T2,%S0"