aarch64: Add out-of-line functions for LSE atomics
This is the libgcc part of the interface -- providing the functions. Rationale is provided at the top of libgcc/config/aarch64/lse.S. * config/aarch64/lse-init.c: New file. * config/aarch64/lse.S: New file. * config/aarch64/t-lse: New file. * config.host: Add t-lse to all aarch64 tuples. From-SVN: r275967
This commit is contained in:
Richard Henderson
Richard Henderson
parent
b7e560deb3
commit
33befddcb8
5 changed files with 335 additions and 0 deletions
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@ -1,3 +1,10 @@
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2019-09-19 Richard Henderson <richard.henderson@linaro.org>
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* config/aarch64/lse-init.c: New file.
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* config/aarch64/lse.S: New file.
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* config/aarch64/t-lse: New file.
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* config.host: Add t-lse to all aarch64 tuples.
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2019-09-10 Christophe Lyon <christophe.lyon@st.com>
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Mickaël Guêné <mickael.guene@st.com>
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@ -350,12 +350,14 @@ aarch64*-*-elf | aarch64*-*-rtems*)
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extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
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extra_parts="$extra_parts crtfastmath.o"
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tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
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tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
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tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
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md_unwind_header=aarch64/aarch64-unwind.h
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;;
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aarch64*-*-freebsd*)
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extra_parts="$extra_parts crtfastmath.o"
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tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
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tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
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tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
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md_unwind_header=aarch64/freebsd-unwind.h
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;;
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@ -367,12 +369,14 @@ aarch64*-*-netbsd*)
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;;
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aarch64*-*-fuchsia*)
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tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
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tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
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tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
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;;
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aarch64*-*-linux*)
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extra_parts="$extra_parts crtfastmath.o"
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md_unwind_header=aarch64/linux-unwind.h
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tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
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tmake_file="${tmake_file} ${cpu_type}/t-lse t-slibgcc-libgcc"
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tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp t-crtfm"
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;;
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alpha*-*-linux*)
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45
libgcc/config/aarch64/lse-init.c
Normal file
45
libgcc/config/aarch64/lse-init.c
Normal file
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@ -0,0 +1,45 @@
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/* Out-of-line LSE atomics for AArch64 architecture, Init.
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Copyright (C) 2019 Free Software Foundation, Inc.
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Contributed by Linaro Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Define the symbol gating the LSE implementations. */
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_Bool __aarch64_have_lse_atomics
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__attribute__((visibility("hidden"), nocommon));
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/* Disable initialization of __aarch64_have_lse_atomics during bootstrap. */
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#ifndef inhibit_libc
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# include <sys/auxv.h>
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/* Disable initialization if the system headers are too old. */
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# if defined(AT_HWCAP) && defined(HWCAP_ATOMICS)
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static void __attribute__((constructor))
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init_have_lse_atomics (void)
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{
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unsigned long hwcap = getauxval (AT_HWCAP);
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__aarch64_have_lse_atomics = (hwcap & HWCAP_ATOMICS) != 0;
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}
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# endif /* HWCAP */
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#endif /* inhibit_libc */
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235
libgcc/config/aarch64/lse.S
Normal file
235
libgcc/config/aarch64/lse.S
Normal file
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@ -0,0 +1,235 @@
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/* Out-of-line LSE atomics for AArch64 architecture.
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Copyright (C) 2019 Free Software Foundation, Inc.
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Contributed by Linaro Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/*
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* The problem that we are trying to solve is operating system deployment
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* of ARMv8.1-Atomics, also known as Large System Exensions (LSE).
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*
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* There are a number of potential solutions for this problem which have
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* been proposed and rejected for various reasons. To recap:
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*
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* (1) Multiple builds. The dynamic linker will examine /lib64/atomics/
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* if HWCAP_ATOMICS is set, allowing entire libraries to be overwritten.
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* However, not all Linux distributions are happy with multiple builds,
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* and anyway it has no effect on main applications.
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*
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* (2) IFUNC. We could put these functions into libgcc_s.so, and have
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* a single copy of each function for all DSOs. However, ARM is concerned
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* that the branch-to-indirect-branch that is implied by using a PLT,
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* as required by IFUNC, is too much overhead for smaller cpus.
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*
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* (3) Statically predicted direct branches. This is the approach that
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* is taken here. These functions are linked into every DSO that uses them.
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* All of the symbols are hidden, so that the functions are called via a
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* direct branch. The choice of LSE vs non-LSE is done via one byte load
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* followed by a well-predicted direct branch. The functions are compiled
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* separately to minimize code size.
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*/
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/* Tell the assembler to accept LSE instructions. */
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.arch armv8-a+lse
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/* Declare the symbol gating the LSE implementations. */
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.hidden __aarch64_have_lse_atomics
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/* Turn size and memory model defines into mnemonic fragments. */
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#if SIZE == 1
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# define S b
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# define UXT uxtb
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#elif SIZE == 2
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# define S h
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# define UXT uxth
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#elif SIZE == 4 || SIZE == 8 || SIZE == 16
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# define S
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# define UXT mov
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#else
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# error
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#endif
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#if MODEL == 1
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# define SUFF _relax
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# define A
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# define L
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#elif MODEL == 2
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# define SUFF _acq
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# define A a
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# define L
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#elif MODEL == 3
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# define SUFF _rel
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# define A
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# define L l
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#elif MODEL == 4
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# define SUFF _acq_rel
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# define A a
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# define L l
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#else
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# error
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#endif
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/* Concatenate symbols. */
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#define glue2_(A, B) A ## B
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#define glue2(A, B) glue2_(A, B)
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#define glue3_(A, B, C) A ## B ## C
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#define glue3(A, B, C) glue3_(A, B, C)
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#define glue4_(A, B, C, D) A ## B ## C ## D
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#define glue4(A, B, C, D) glue4_(A, B, C, D)
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/* Select the size of a register, given a regno. */
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#define x(N) glue2(x, N)
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#define w(N) glue2(w, N)
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#if SIZE < 8
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# define s(N) w(N)
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#else
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# define s(N) x(N)
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#endif
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#define NAME(BASE) glue4(__aarch64_, BASE, SIZE, SUFF)
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#define LDXR glue4(ld, A, xr, S)
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#define STXR glue4(st, L, xr, S)
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/* Temporary registers used. Other than these, only the return value
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register (x0) and the flags are modified. */
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#define tmp0 16
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#define tmp1 17
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#define tmp2 15
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/* Start and end a function. */
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.macro STARTFN name
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.text
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.balign 16
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.globl \name
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.hidden \name
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.type \name, %function
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.cfi_startproc
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\name:
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.endm
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.macro ENDFN name
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.cfi_endproc
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.size \name, . - \name
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.endm
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/* Branch to LABEL if LSE is disabled. */
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.macro JUMP_IF_NOT_LSE label
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adrp x(tmp0), __aarch64_have_lse_atomics
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ldrb w(tmp0), [x(tmp0), :lo12:__aarch64_have_lse_atomics]
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cbz w(tmp0), \label
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.endm
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#ifdef L_cas
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STARTFN NAME(cas)
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JUMP_IF_NOT_LSE 8f
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#if SIZE < 16
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#define CAS glue4(cas, A, L, S)
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CAS s(0), s(1), [x2]
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ret
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8: UXT s(tmp0), s(0)
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0: LDXR s(0), [x2]
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cmp s(0), s(tmp0)
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bne 1f
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STXR w(tmp1), s(1), [x2]
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cbnz w(tmp1), 0b
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1: ret
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#else
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#define LDXP glue3(ld, A, xp)
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#define STXP glue3(st, L, xp)
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#define CASP glue3(casp, A, L)
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CASP x0, x1, x2, x3, [x4]
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ret
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8: mov x(tmp0), x0
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mov x(tmp1), x1
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0: LDXP x0, x1, [x4]
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cmp x0, x(tmp0)
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ccmp x1, x(tmp1), #0, eq
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bne 1f
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STXP w(tmp2), x(tmp0), x(tmp1), [x4]
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cbnz w(tmp2), 0b
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1: ret
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#endif
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ENDFN NAME(cas)
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#endif
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#ifdef L_swp
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#define SWP glue4(swp, A, L, S)
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STARTFN NAME(swp)
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JUMP_IF_NOT_LSE 8f
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SWP s(0), s(0), [x1]
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ret
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8: mov s(tmp0), s(0)
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0: LDXR s(0), [x1]
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STXR w(tmp1), s(tmp0), [x1]
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cbnz w(tmp1), 0b
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ret
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ENDFN NAME(swp)
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#endif
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#if defined(L_ldadd) || defined(L_ldclr) \
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|| defined(L_ldeor) || defined(L_ldset)
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#ifdef L_ldadd
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#define LDNM ldadd
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#define OP add
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#elif defined(L_ldclr)
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#define LDNM ldclr
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#define OP bic
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#elif defined(L_ldeor)
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#define LDNM ldeor
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#define OP eor
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#elif defined(L_ldset)
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#define LDNM ldset
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#define OP orr
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#else
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#error
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#endif
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#define LDOP glue4(LDNM, A, L, S)
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STARTFN NAME(LDNM)
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JUMP_IF_NOT_LSE 8f
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LDOP s(0), s(0), [x1]
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ret
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8: mov s(tmp0), s(0)
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0: LDXR s(0), [x1]
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OP s(tmp1), s(0), s(tmp0)
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STXR w(tmp1), s(tmp1), [x1]
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cbnz w(tmp1), 0b
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ret
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ENDFN NAME(LDNM)
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#endif
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44
libgcc/config/aarch64/t-lse
Normal file
44
libgcc/config/aarch64/t-lse
Normal file
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@ -0,0 +1,44 @@
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# Out-of-line LSE atomics for AArch64 architecture.
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# Copyright (C) 2019 Free Software Foundation, Inc.
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# Contributed by Linaro Ltd.
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#
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# This file is part of GCC.
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#
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# GCC is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3, or (at your option)
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# any later version.
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#
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# GCC is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with GCC; see the file COPYING3. If not see
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# <http://www.gnu.org/licenses/>.
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# Compare-and-swap has 5 sizes and 4 memory models.
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S0 := $(foreach s, 1 2 4 8 16, $(addsuffix _$(s), cas))
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O0 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S0)))
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# Swap, Load-and-operate have 4 sizes and 4 memory models
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S1 := $(foreach s, 1 2 4 8, $(addsuffix _$(s), swp ldadd ldclr ldeor ldset))
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O1 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S1)))
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LSE_OBJS := $(O0) $(O1)
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libgcc-objects += $(LSE_OBJS) lse-init$(objext)
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empty =
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space = $(empty) $(empty)
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PAT_SPLIT = $(subst _,$(space),$(*F))
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PAT_BASE = $(word 1,$(PAT_SPLIT))
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PAT_N = $(word 2,$(PAT_SPLIT))
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PAT_M = $(word 3,$(PAT_SPLIT))
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lse-init$(objext): $(srcdir)/config/aarch64/lse-init.c
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$(gcc_compile) -c $<
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$(LSE_OBJS): $(srcdir)/config/aarch64/lse.S
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$(gcc_compile) -DL_$(PAT_BASE) -DSIZE=$(PAT_N) -DMODEL=$(PAT_M) -c $<
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