arm.md (all peephole2 patterns): Use predicates that validate register classes as appropriate.
* arm.md (all peephole2 patterns): Use predicates that validate register classes as appropriate. From-SVN: r81860
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2 changed files with 19 additions and 19 deletions
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@ -1,3 +1,8 @@
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2004-05-14 Richard Earnshaw <rearnsha@arm.com>
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* arm.md (all peephole2 patterns): Use predicates that validate
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register classes as appropriate.
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2004-05-14 Steven Bosscher <stevenb@suse.de>
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PR opt/14472
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@ -466,8 +466,8 @@
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; addition.
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(define_peephole2
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[(match_scratch:SI 3 "r")
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(set (match_operand:SI 0 "s_register_operand" "")
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(plus:SI (match_operand:SI 1 "s_register_operand" "")
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(set (match_operand:SI 0 "arm_general_register_operand" "")
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(plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
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(match_operand:SI 2 "const_int_operand" "")))]
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"TARGET_ARM &&
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!(const_ok_for_arm (INTVAL (operands[2]))
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@ -534,15 +534,14 @@
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;; Reloading and elimination of the frame pointer can
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;; sometimes cause this optimization to be missed.
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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[(set (match_operand:SI 0 "arm_general_register_operand" "")
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(match_operand:SI 1 "const_int_operand" ""))
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))]
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(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
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"TARGET_THUMB
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&& REGNO (operands[2]) == STACK_POINTER_REGNUM
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&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
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&& (INTVAL (operands[1]) & 3) == 0"
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[(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
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[(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
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""
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)
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@ -630,8 +629,8 @@
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;; similarly for the beq variant using bcc.
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;; This is a common looping idiom (while (n--))
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(define_peephole2
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[(set (match_operand:SI 0 "s_register_operand" "")
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(plus:SI (match_operand:SI 1 "s_register_operand" "")
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[(set (match_operand:SI 0 "arm_general_register_operand" "")
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(plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
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(const_int -1)))
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(set (match_operand 2 "cc_register" "")
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(compare (match_dup 0) (const_int -1)))
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@ -986,9 +985,9 @@
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(define_peephole2
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[(match_scratch:SI 3 "r")
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(set (match_operand:SI 0 "s_register_operand" "")
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(set (match_operand:SI 0 "arm_general_register_operand" "")
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(minus:SI (match_operand:SI 1 "const_int_operand" "")
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(match_operand:SI 2 "s_register_operand" "")))]
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(match_operand:SI 2 "arm_general_register_operand" "")))]
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"TARGET_ARM
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&& !const_ok_for_arm (INTVAL (operands[1]))
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&& const_ok_for_arm (~INTVAL (operands[1]))"
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@ -2116,8 +2115,8 @@
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(define_peephole2
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[(match_scratch:SI 3 "r")
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(set (match_operand:SI 0 "s_register_operand" "")
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(ior:SI (match_operand:SI 1 "s_register_operand" "")
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(set (match_operand:SI 0 "arm_general_register_operand" "")
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(ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
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(match_operand:SI 2 "const_int_operand" "")))]
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"TARGET_ARM
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&& !const_ok_for_arm (INTVAL (operands[2]))
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@ -9651,15 +9650,11 @@
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; This pattern is never tried by combine, so do it as a peephole
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(define_peephole2
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[(set (match_operand:SI 0 "s_register_operand" "")
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(match_operand:SI 1 "s_register_operand" ""))
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[(set (match_operand:SI 0 "arm_general_register_operand" "")
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(match_operand:SI 1 "arm_general_register_operand" ""))
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(set (reg:CC CC_REGNUM)
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(compare:CC (match_dup 1) (const_int 0)))]
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"TARGET_ARM
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&& (!(TARGET_HARD_FLOAT && TARGET_MAVERICK)
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|| (!cirrus_fp_register (operands[0], SImode)
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&& !cirrus_fp_register (operands[1], SImode)))
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"
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"TARGET_ARM"
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[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
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(set (match_dup 0) (match_dup 1))])]
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""
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