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RISC-V: Fix selection of pipeline model for sifive-7-series

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A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
while now, due to the pipeline model for sifive-7-series not being
selected despite -mtune=sifive-7-series.  The root cause is that the
respective RISCV_TUNE entry points to generic instead.  Fix this.

Fixes 97d1ed67fc ("RISC-V: Support --target-help for -mcpu/-mtune")

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): Update
	sifive-7-series to point to the sifive_7 pipeline description.
This commit is contained in:
Philipp Tomsich 2022-11-10 00:43:05 +01:00
parent 203b127fcc
commit 2f6cb9c51a
1 changed files with 1 additions and 1 deletions
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gcc/config/riscv/riscv-cores.def
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@ -36,7 +36,7 @@
RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)