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[Patch libgcc AArch64 12/17] Enable hfmode soft-float conversions and truncations

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gcc/

	* config/aarch64/aarch64-c.c (aarch64_scalar_mode_supported_p): New.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Define.

libgcc/

	* config/aarch64/sfp-machine.h (_FP_NANFRAC_H): Define.
	(_FP_NANSIGN_H): Likewise.
	* config/aarch64/t-softfp (softfp_extensions): Add hftf.
	(softfp_truncations): Add tfhf.
	(softfp_extras): Add required conversion functions.

From-SVN: r242844
This commit is contained in:
James Greenhalgh 2016-11-24 18:16:55 +00:00 • committed by James Greenhalgh
parent bf1e3646d1
commit 2e5f8203d2
5 changed files with 32 additions and 2 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2016-11-24 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-c.c (aarch64_scalar_mode_supported_p): New.
(TARGET_SCALAR_MODE_SUPPORTED_P): Define.
2016-11-24 James Greenhalgh <james.greenhalgh@arm.com> 2016-11-24 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (<optab>sihf2): Convert to expand. * config/aarch64/aarch64.md (<optab>sihf2): Convert to expand.

14
gcc/config/aarch64/aarch64.c
View file

@ -14265,6 +14265,17 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
} }
} }
/* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
if MODE is HFmode, and punt to the generic implementation otherwise. */
static bool
aarch64_scalar_mode_supported_p (machine_mode mode)
{
return (mode == HFmode
? true
: default_scalar_mode_supported_p (mode));
}
#undef TARGET_ADDRESS_COST #undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST aarch64_address_cost #define TARGET_ADDRESS_COST aarch64_address_cost
@ -14475,6 +14486,9 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
#undef TARGET_RTX_COSTS #undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
#undef TARGET_SCHED_ISSUE_RATE #undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate

8
libgcc/ChangeLog
View file

@ -1,3 +1,11 @@
2016-11-24 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/sfp-machine.h (_FP_NANFRAC_H): Define.
(_FP_NANSIGN_H): Likewise.
* config/aarch64/t-softfp (softfp_extensions): Add hftf.
(softfp_truncations): Add tfhf.
(softfp_extras): Add required conversion functions.
2016-11-23 James Greenhalgh <james.greenhalgh@arm.com> 2016-11-23 James Greenhalgh <james.greenhalgh@arm.com>
Matthew Wahab <matthew.wahab@arm.com> Matthew Wahab <matthew.wahab@arm.com>

2
libgcc/config/aarch64/sfp-machine.h
View file

@ -42,9 +42,11 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)
#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
#define _FP_NANSIGN_H 0
#define _FP_NANSIGN_S 0 #define _FP_NANSIGN_S 0
#define _FP_NANSIGN_D 0 #define _FP_NANSIGN_D 0
#define _FP_NANSIGN_Q 0 #define _FP_NANSIGN_Q 0

5
libgcc/config/aarch64/t-softfp
View file

@ -1,8 +1,9 @@
softfp_float_modes := tf softfp_float_modes := tf
softfp_int_modes := si di ti softfp_int_modes := si di ti
softfp_extensions := sftf dftf softfp_extensions := sftf dftf hftf
softfp_truncations := tfsf tfdf softfp_truncations := tfsf tfdf tfhf
softfp_exclude_libgcc2 := n softfp_exclude_libgcc2 := n
softfp_extras := fixhfti fixunshfti floattihf floatuntihf
TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes