Revert "RISC-V: Support RVV VFMACC rounding mode intrinsic API"

This reverts commit 51e5a5cefb.

gcc/config/riscv/riscv-vector-builtins-bases.cc

@@ -356,29 +356,6 @@ public:
   }
 };
 
-/* Implements below instructions for frm
-   - vfmacc
-*/
-class vfmacc_frm : public function_base
-{
-public:
-  bool has_rounding_mode_operand_p () const override { return true; }
-
-  bool has_merge_operand_p () const override { return false; }
-
-  rtx expand (function_expander &e) const override
-  {
-    if (e.op_info->op == OP_TYPE_vf)
-      return e.use_ternop_insn (true,
-				code_for_pred_mul_scalar (PLUS,
-							  e.vector_mode ()));
-    if (e.op_info->op == OP_TYPE_vv)
-      return e.use_ternop_insn (true,
-				code_for_pred_mul (PLUS, e.vector_mode ()));
-    gcc_unreachable ();
-  }
-};
-
 /* Implements vrsub.  */
 class vrsub : public function_base
 {
@@ -2139,7 +2116,6 @@ static CONSTEXPR const reverse_binop_frm<DIV> vfrdiv_frm_obj;
 static CONSTEXPR const widen_binop<MULT> vfwmul_obj;
 static CONSTEXPR const widen_binop_frm<MULT> vfwmul_frm_obj;
 static CONSTEXPR const vfmacc vfmacc_obj;
-static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
 static CONSTEXPR const vfnmsac vfnmsac_obj;
 static CONSTEXPR const vfmadd vfmadd_obj;
 static CONSTEXPR const vfnmsub vfnmsub_obj;
@@ -2375,7 +2351,6 @@ BASE (vfrdiv_frm)
 BASE (vfwmul)
 BASE (vfwmul_frm)
 BASE (vfmacc)
-BASE (vfmacc_frm)
 BASE (vfnmsac)
 BASE (vfmadd)
 BASE (vfnmsub)

gcc/config/riscv/riscv-vector-builtins-bases.h

@@ -160,7 +160,6 @@ extern const function_base *const vfrdiv_frm;
 extern const function_base *const vfwmul;
 extern const function_base *const vfwmul_frm;
 extern const function_base *const vfmacc;
-extern const function_base *const vfmacc_frm;
 extern const function_base *const vfnmsac;
 extern const function_base *const vfmadd;
 extern const function_base *const vfnmsub;

gcc/config/riscv/riscv-vector-builtins-functions.def

@@ -348,8 +348,6 @@ DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvfv_ops)
 DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
-DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
-DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
 
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)

gcc/config/riscv/riscv-vector-builtins.cc

@@ -3730,29 +3730,17 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
     }
 
   for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-    {
-      if (base->has_rounding_mode_operand_p ()
-	  && argno == call_expr_nargs (exp) - 2)
-	{
-	  /* Since the rounding mode argument position is not consistent with
-	     the instruction pattern, we need to skip rounding mode argument
-	     here.  */
-	  continue;
-	}
-      add_input_operand (argno);
-    }
+    add_input_operand (argno);
 
   add_input_operand (Pmode, get_tail_policy_for_pred (pred));
   add_input_operand (Pmode, get_mask_policy_for_pred (pred));
   add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
 
-  if (base->has_rounding_mode_operand_p ())
-    add_input_operand (call_expr_nargs (exp) - 2);
-
-  /* The RVV floating-point only support dynamic rounding mode in the
-     FRM register.  */
+  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
+     We add default rounding mode for the intrinsics that didn't model rounding
+     mode yet.  */
   if (opno != insn_data[icode].n_generator_args)
-    add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
+    add_input_operand (Pmode, const0_rtx);
 
   return generate_insn (icode);
 }

gcc/config/riscv/vector.md

@@ -866,7 +866,7 @@
 
 ;; Defines rounding mode of an floating-point operation.
 (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
-  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd")
+  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
          (cond
 	   [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
 	    (const_string "rne")

gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c

@@ -1,47 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
-
-#include "riscv_vector.h"
-
-typedef float float32_t;
-
-vfloat32m1_t
-test_riscv_vfmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
-			       vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
-}
-
-vfloat32m1_t
-test_vfmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
-			   vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
-}
-
-vfloat32m1_t
-test_vfmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
-			 size_t vl) {
-  return __riscv_vfmacc_vf_f32m1_rm (vd, op1, op2, 2, vl);
-}
-
-vfloat32m1_t
-test_vfmacc_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
-			   vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfmacc_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
-}
-
-vfloat32m1_t
-test_riscv_vfmacc_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1, vfloat32m1_t op2,
-			    size_t vl) {
-  return __riscv_vfmacc_vv_f32m1 (vd, op1, op2, vl);
-}
-
-vfloat32m1_t
-test_vfmacc_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
-			vfloat32m1_t op2, size_t vl) {
-  return __riscv_vfmacc_vv_f32m1_m (mask, vd, op1, op2, vl);
-}
-
-/* { dg-final { scan-assembler-times {vfmacc\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
-/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
-/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */