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[AArch64] Tweak operand choice for SVE predicate AND

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SVE defines an assembly alias:

   MOV pa.B, pb/Z, pc.B  ->  AND pa.B. pb/Z, pc.B, pc.B

Our and<mode>3 pattern was instead using the functionally-equivalent:

   AND pa.B. pb/Z, pb.B, pc.B
                   ^^^^
This patch duplicates pc.B instead so that the alias can be seen
in disassembly.

I wondered about using the alias in the pattern instead, but using AND
explicitly seems to fit better with the pattern name and surrounding code.

2019-08-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
	operand order match the MOV /Z alias.

From-SVN: r274521
This commit is contained in:
Richard Sandiford 2019-08-15 08:55:00 +00:00 • committed by Richard Sandiford
parent 139df05a29
commit 2d2388f82f
2 changed files with 8 additions and 1 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
operand order match the MOV /Z alias.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take

4
gcc/config/aarch64/aarch64-sve.md
View file

@ -3317,12 +3317,14 @@
;; -------------------------------------------------------------------------
;; Predicate AND. We can reuse one of the inputs as the GP.
;; Doubling the second operand is the preferred implementation
;; of the MOV alias, so we use that instead of %1/z, %1, %2.
(define_insn "and<mode>3"
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand" "Upa")
(match_operand:PRED_ALL 2 "register_operand" "Upa")))]
"TARGET_SVE"
"and\t%0.b, %1/z, %1.b, %2.b"
"and\t%0.b, %1/z, %2.b, %2.b"
)
;; Unpredicated predicate EOR and ORR.