Optimize a < 0 ? -1 : 0 to (signed)a >> 31.
Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
and x < 0 ? 1 : 0 into (unsigned) x >> 31.
Add define_insn_and_split for the optimization did in
ix86_expand_int_vcond.
gcc/ChangeLog:
PR target/115517
* config/i386/sse.md ("*ashr<mode>3_1"): New
define_insn_and_split.
(*avx512_ashr<mode>3_1): Ditto.
(*avx2_lshr<mode>3_1): Ditto.
(*avx2_lshr<mode>3_2): Ditto and add 2 combine splitter after
it.
* config/i386/mmx.md (mmxscalarsize): New mode attribute.
(*mmw_ashr<mode>3_1): New define_insn_and_split.
("mmx_<insn><mode>3): Add a combine spiltter after it.
(*mmx_ashrv2hi3_1): New define_insn_and_plit, also add a
combine splitter after it.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr111023-2.c: Adjust testcase.
* gcc.target/i386/vect-div-1.c: Ditto.
This commit is contained in:
liuhongt
parent
e94e6ee495
commit
2ccdd0f223
4 changed files with 138 additions and 3 deletions
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@ -147,6 +147,14 @@
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(V4HI "hi") (V2HI "hi")
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(V8QI "qi")])
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(define_mode_attr mmxscalarsize
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[(V1DI "64")
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(V2SI "32") (V2SF "32")
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(V4HF "16") (V4BF "16")
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(V2HF "16") (V2BF "16")
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(V4HI "16") (V2HI "16")
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(V8QI "8")])
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(define_mode_attr Yv_Yw
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[(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")])
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@ -3620,6 +3628,17 @@
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(const_string "0")))
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(set_attr "mode" "DI,TI,TI")])
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(define_insn_and_split "*mmx_ashr<mode>3_1"
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[(set (match_operand:MMXMODE24 0 "register_operand")
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(lt:MMXMODE24
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(match_operand:MMXMODE24 1 "register_operand")
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(match_operand:MMXMODE24 2 "const0_operand")))]
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"TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0) (ashiftrt:MMXMODE24 (match_dup 1) (match_dup 3)))]
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"operands[3] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
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(define_expand "ashr<mode>3"
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[(set (match_operand:MMXMODE24 0 "register_operand")
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(ashiftrt:MMXMODE24
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@ -3646,6 +3665,17 @@
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(const_string "0")))
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(set_attr "mode" "DI,TI,TI")])
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(define_split
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[(set (match_operand:MMXMODE248 0 "register_operand")
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(and:MMXMODE248
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(lt:MMXMODE248
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(match_operand:MMXMODE248 1 "register_operand")
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(match_operand:MMXMODE248 2 "const0_operand"))
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(match_operand:MMXMODE248 3 "const1_operand")))]
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"TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
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[(set (match_dup 0) (lshiftrt:MMXMODE248 (match_dup 1) (match_dup 4)))]
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"operands[4] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
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(define_expand "<insn><mode>3"
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[(set (match_operand:MMXMODE24 0 "register_operand")
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(any_lshift:MMXMODE24
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@ -3687,6 +3717,28 @@
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(const_string "0")))
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(set_attr "mode" "TI")])
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(define_insn_and_split "*mmx_ashrv2hi3_1"
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[(set (match_operand:V2HI 0 "register_operand")
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(lt:V2HI
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(match_operand:V2HI 1 "register_operand")
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(match_operand:V2HI 2 "const0_operand")))]
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"TARGET_SSE2 && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0) (ashiftrt:V2HI (match_dup 1) (match_dup 3)))]
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"operands[3] = gen_int_mode (15, DImode);")
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(define_split
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[(set (match_operand:V2HI 0 "register_operand")
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(and:V2HI
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(lt:V2HI
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(match_operand:V2HI 1 "register_operand")
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(match_operand:V2HI 2 "const0_operand"))
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(match_operand:V2HI 3 "const1_operand")))]
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"TARGET_SSE2 && ix86_pre_reload_split ()"
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[(set (match_dup 0) (lshiftrt:V2HI (match_dup 1) (match_dup 4)))]
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"operands[4] = gen_int_mode (15, DImode);")
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(define_expand "<insn>v8qi3"
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[(set (match_operand:V8QI 0 "register_operand")
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(any_shift:V8QI (match_operand:V8QI 1 "register_operand")
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@ -16923,6 +16923,17 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn_and_split "*ashr<mode>3_1"
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[(set (match_operand:VI24_AVX2 0 "register_operand")
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(lt:VI24_AVX2
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(match_operand:VI24_AVX2 1 "register_operand")
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(match_operand:VI24_AVX2 2 "const0_operand")))]
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"TARGET_SSE2 && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0) (ashiftrt:VI24_AVX2 (match_dup 1) (match_dup 3)))]
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"operands[3] = gen_int_mode (<ssescalarsize> - 1, DImode);")
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(define_insn "<mask_codefor>ashr<mode>3<mask_name>"
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[(set (match_operand:VI248_AVX512BW_AVX512VL 0 "register_operand" "=v,v")
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(ashiftrt:VI248_AVX512BW_AVX512VL
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@ -16937,6 +16948,23 @@
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(const_string "0")))
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn_and_split "*avx512_ashr<mode>3_1"
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[(set (match_operand:VI248_AVX512VLBW 0 "register_operand")
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(vec_merge:VI248_AVX512VLBW
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(match_operand:VI248_AVX512VLBW 1 "vector_all_ones_operand")
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(match_operand:VI248_AVX512VLBW 2 "const0_operand")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI248_AVX512VLBW 3 "nonimmediate_operand")
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(match_operand:VI248_AVX512VLBW 4 "const0_operand")
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(const_int 1)]
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UNSPEC_PCMP)))]
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"TARGET_AVX512F && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(ashiftrt:VI248_AVX512VLBW (match_dup 3) (match_dup 5)))]
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"operands[5] = gen_int_mode (<ssescalarsize> - 1, DImode);")
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(define_expand "ashr<mode>3"
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[(set (match_operand:VI248_AVX512BW 0 "register_operand")
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(ashiftrt:VI248_AVX512BW
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@ -17091,6 +17119,61 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn_and_split "*avx2_lshr<mode>3_1"
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[(set (match_operand:VI8_AVX2 0 "register_operand")
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(and:VI8_AVX2
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(gt:VI8_AVX2
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(match_operand:VI8_AVX2 1 "register_operand")
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(match_operand:VI8_AVX2 2 "register_operand"))
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(match_operand:VI8_AVX2 3 "const1_operand")))]
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"TARGET_SSE4_2 && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 5) (gt:VI8_AVX2 (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (lshiftrt:VI8_AVX2 (match_dup 5) (match_dup 4)))]
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{
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operands[4] = gen_int_mode (<ssescalarsize> - 1, DImode);
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operands[5] = gen_reg_rtx (<MODE>mode);
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})
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(define_insn_and_split "*avx2_lshr<mode>3_2"
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[(set (match_operand:VI8_AVX2 0 "register_operand")
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(and:VI8_AVX2
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(lt:VI8_AVX2
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(match_operand:VI8_AVX2 1 "register_operand")
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(match_operand:VI8_AVX2 2 "const0_operand"))
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(match_operand:VI8_AVX2 3 "const1_operand")))]
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"TARGET_SSE2 && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(set (match_dup 0) (lshiftrt:VI8_AVX2 (match_dup 1) (const_int 63)))])
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(define_split
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[(set (match_operand:VI248_AVX2 0 "register_operand")
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(and:VI248_AVX2
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(lt:VI248_AVX2
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(match_operand:VI248_AVX2 1 "register_operand")
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(match_operand:VI248_AVX2 2 "const0_operand"))
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(match_operand:VI248_AVX2 3 "const1_operand")))]
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"TARGET_SSE2 && ix86_pre_reload_split ()"
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[(set (match_dup 0) (lshiftrt:VI248_AVX2 (match_dup 1) (match_dup 4)))]
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"operands[4] = gen_int_mode (<ssescalarsize> - 1, DImode);")
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(define_split
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[(set (match_operand:VI248_AVX512VLBW 0 "register_operand")
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(vec_merge:VI248_AVX512VLBW
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(match_operand:VI248_AVX512VLBW 1 "const1_operand")
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(match_operand:VI248_AVX512VLBW 2 "const0_operand")
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(unspec:<avx512fmaskmode>
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[(match_operand:VI248_AVX512VLBW 3 "nonimmediate_operand")
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(match_operand:VI248_AVX512VLBW 4 "const0_operand")
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(const_int 1)]
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UNSPEC_PCMP)))]
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"TARGET_AVX512F && ix86_pre_reload_split ()"
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[(set (match_dup 0)
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(lshiftrt:VI248_AVX512VLBW (match_dup 3) (match_dup 5)))]
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"operands[5] = gen_int_mode (<ssescalarsize> - 1, DImode);")
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(define_insn "<insn><mode>3<mask_name>"
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[(set (match_operand:VI248_AVX512BW 0 "register_operand" "=v,v")
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(any_lshift:VI248_AVX512BW
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@ -36,7 +36,7 @@ v4si_v4hi (v4si *dst, v8hi src)
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dst[0] = *(v4si *) tem;
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}
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/* { dg-final { scan-assembler "pcmpgtw" } } */
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/* { dg-final { scan-assembler "(?:pcmpgtw|psraw)" } } */
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/* { dg-final { scan-assembler "punpcklwd" } } */
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void
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@ -48,5 +48,5 @@ v2di_v2si (v2di *dst, v4si src)
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dst[0] = *(v2di *) tem;
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}
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/* { dg-final { scan-assembler "pcmpgtd" } } */
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/* { dg-final { scan-assembler "(?:pcmpgtd|psrad)" } } */
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/* { dg-final { scan-assembler "punpckldq" } } */
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -fno-common -msse2" } */
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/* { dg-options "-O2 -ftree-vectorize -fno-common -msse4.1" } */
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unsigned short b[1024] = { 0 };
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int a[1024] = { 0 };
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Add table
Reference in a new issue