re PR rtl-optimization/54739 (FAIL: gcc.dg/lower-subreg-1.c scan-rtl-dump subreg1 "Splitting reg")
PR rtl-optimization/54739 * config/m68k/m68k.md (anddi3, iordi3, xordi3, one_cmpldi2): Remove. From-SVN: r192156
This commit is contained in:
Andreas Schwab
Andreas Schwab
parent
7d11d29699
commit
2aa3b677b1
2 changed files with 6 additions and 226 deletions
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@ -1,3 +1,9 @@
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2012-10-06 Andreas Schwab <schwab@linux-m68k.org>
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PR rtl-optimization/54739
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* config/m68k/m68k.md (anddi3, iordi3, xordi3, one_cmpldi2):
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Remove.
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2012-10-06 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/54760
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@ -3597,72 +3597,6 @@
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;; logical-and instructions
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;; "anddi3" is mainly here to help combine().
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(define_insn "anddi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
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(and:DI (match_operand:DI 1 "general_operand" "%0,0")
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(match_operand:DI 2 "general_operand" "dn,don")))]
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"!TARGET_COLDFIRE"
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{
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CC_STATUS_INIT;
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/* We can get CONST_DOUBLE, but also const1_rtx etc. */
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if (CONSTANT_P (operands[2]))
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{
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rtx hi, lo;
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split_double (operands[2], &hi, &lo);
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switch (INTVAL (hi))
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{
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case 0 :
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output_asm_insn ("clr%.l %0", operands);
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break;
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case -1 :
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break;
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default :
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = hi;
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output_asm_insn (output_andsi3 (xoperands), xoperands);
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}
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}
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if (GET_CODE (operands[0]) == REG)
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operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
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else
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operands[0] = adjust_address (operands[0], SImode, 4);
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switch (INTVAL (lo))
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{
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case 0 :
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output_asm_insn ("clr%.l %0", operands);
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break;
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case -1 :
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break;
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default :
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = lo;
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output_asm_insn (output_andsi3 (xoperands), xoperands);
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}
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}
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return "";
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}
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if (GET_CODE (operands[0]) != REG)
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{
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operands[1] = adjust_address (operands[0], SImode, 4);
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return "and%.l %2,%0\;and%.l %R2,%1";
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}
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if (GET_CODE (operands[2]) != REG)
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{
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operands[1] = adjust_address (operands[2], SImode, 4);
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return "and%.l %2,%0\;and%.l %1,%R0";
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}
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return "and%.l %2,%0\;and%.l %R2,%R0";
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})
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;; Prevent AND from being made with sp. This doesn't exist in the machine
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;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
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;; can't allocate pseudos into it.
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@ -3780,76 +3714,6 @@
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return "or%.w %1,%0";
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})
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;; "iordi3" is mainly here to help combine().
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(define_insn "iordi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
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(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
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(match_operand:DI 2 "general_operand" "dn,don")))]
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"!TARGET_COLDFIRE"
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{
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CC_STATUS_INIT;
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/* We can get CONST_DOUBLE, but also const1_rtx etc. */
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if (CONSTANT_P (operands[2]))
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{
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rtx hi, lo;
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split_double (operands[2], &hi, &lo);
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switch (INTVAL (hi))
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{
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case 0 :
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break;
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case -1 :
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/* FIXME : a scratch register would be welcome here if operand[0]
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is not a register */
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output_asm_insn ("move%.l #-1,%0", operands);
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break;
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default :
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = hi;
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output_asm_insn (output_iorsi3 (xoperands), xoperands);
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}
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}
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if (GET_CODE (operands[0]) == REG)
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operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
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else
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operands[0] = adjust_address (operands[0], SImode, 4);
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switch (INTVAL (lo))
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{
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case 0 :
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break;
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case -1 :
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/* FIXME : a scratch register would be welcome here if operand[0]
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is not a register */
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output_asm_insn ("move%.l #-1,%0", operands);
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break;
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default :
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = lo;
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output_asm_insn (output_iorsi3 (xoperands), xoperands);
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}
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}
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return "";
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}
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if (GET_CODE (operands[0]) != REG)
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{
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operands[1] = adjust_address (operands[0], SImode, 4);
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return "or%.l %2,%0\;or%.l %R2,%1";
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}
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if (GET_CODE (operands[2]) != REG)
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{
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operands[1] = adjust_address (operands[2], SImode, 4);
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return "or%.l %2,%0\;or%.l %1,%R0";
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}
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return "or%.l %2,%0\;or%.l %R2,%R0";
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})
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(define_expand "iorsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(ior:SI (match_operand:SI 1 "general_operand" "")
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@ -3957,79 +3821,6 @@
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;; xor instructions
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;; "xordi3" is mainly here to help combine().
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(define_insn "xordi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=od")
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(xor:DI (match_operand:DI 1 "general_operand" "%0")
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(match_operand:DI 2 "general_operand" "dn")))]
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"!TARGET_COLDFIRE"
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{
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CC_STATUS_INIT;
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/* We can get CONST_DOUBLE, but also const1_rtx etc. */
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if (CONSTANT_P (operands[2]))
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{
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rtx hi, lo;
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split_double (operands[2], &hi, &lo);
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switch (INTVAL (hi))
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{
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case 0 :
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break;
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case -1 :
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output_asm_insn ("not%.l %0", operands);
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break;
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default :
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/* FIXME : a scratch register would be welcome here if
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-128 <= INTVAL (hi) < -1 */
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = hi;
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output_asm_insn (output_xorsi3 (xoperands), xoperands);
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}
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}
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if (GET_CODE (operands[0]) == REG)
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operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
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else
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operands[0] = adjust_address (operands[0], SImode, 4);
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switch (INTVAL (lo))
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{
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case 0 :
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break;
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case -1 :
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output_asm_insn ("not%.l %0", operands);
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break;
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default :
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/* FIXME : a scratch register would be welcome here if
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-128 <= INTVAL (lo) < -1 */
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operands[2] = lo;
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/* FIXME : this should be merged with xorsi3 */
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{
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rtx xoperands[3];
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xoperands[0] = operands[0];
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xoperands[2] = lo;
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output_asm_insn (output_xorsi3 (xoperands), xoperands);
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}
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}
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return "";
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}
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if (GET_CODE (operands[0]) != REG)
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{
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operands[1] = adjust_address (operands[0], SImode, 4);
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return "eor%.l %2,%0\;eor%.l %R2,%1";
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}
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if (GET_CODE (operands[2]) != REG)
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{
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operands[1] = adjust_address (operands[2], SImode, 4);
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return "eor%.l %2,%0\;eor%.l %1,%R0";
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}
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return "eor%.l %2,%0\;eor%.l %R2,%R0";
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})
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(define_expand "xorsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(xor:SI (match_operand:SI 1 "general_operand" "")
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@ -4498,23 +4289,6 @@
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;; one complement instructions
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;; "one_cmpldi2" is mainly here to help combine().
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(define_insn "one_cmpldi2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
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(not:DI (match_operand:DI 1 "general_operand" "0")))]
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"!TARGET_COLDFIRE"
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[0]) == REG)
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operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
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else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
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|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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operands[1] = operands[0];
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else
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operands[1] = adjust_address (operands[0], SImode, 4);
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return "not%.l %1\;not%.l %0";
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})
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(define_expand "one_cmplsi2"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(not:SI (match_operand:SI 1 "general_operand" "")))]
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