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[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand

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Like a previous patch, just add constraints for predicates
not_single_bit_mask_operand and single_bit_mask_operand.

OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.

Thanks,
Andrew Pinski

gcc/ChangeLog:

	* config/riscv/constraints.md (DbS): New constraint.
	(DnS): New constraint.
	* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
	(*bclr<mode>): Likewise.
	(*binvi<mode>): Likewise.
This commit is contained in:
Andrew Pinski 2022-08-15 22:48:25 +00:00
parent 2c721ea947
commit 2a5549f1cc
2 changed files with 13 additions and 3 deletions
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6
gcc/config/riscv/bitmanip.md
View file

@ -324,7 +324,7 @@
(define_insn "*bseti<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(ior:X (match_operand:X 1 "register_operand" "r")
(match_operand 2 "single_bit_mask_operand" "i")))]
(match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
@ -341,7 +341,7 @@
(define_insn "*bclri<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (match_operand:X 1 "register_operand" "r")
(match_operand 2 "not_single_bit_mask_operand" "i")))]
(match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
"TARGET_ZBS"
"bclri\t%0,%1,%T2"
[(set_attr "type" "bitmanip")])
@ -358,7 +358,7 @@
(define_insn "*binvi<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(xor:X (match_operand:X 1 "register_operand" "r")
(match_operand 2 "single_bit_mask_operand" "i")))]
(match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"binvi\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])

10
gcc/config/riscv/constraints.md
View file

@ -72,6 +72,16 @@
(and (match_code "const_int")
(match_test "ival == 63")))
(define_constraint "DbS"
"@internal"
(and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (ival)")))
(define_constraint "DnS"
"@internal"
(and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"