sparc.c (sparc_emit_set_const32): INTVAL is of type HOST_WIDE_INT.
* config/sparc/sparc.c (sparc_emit_set_const32): INTVAL is of type HOST_WIDE_INT. (safe_constDI sparc_emit_set_const64_quick1, sparc_emit_set_const64_quick2, sparc_emit_set_const64_longway, analyze_64bit_constant, const64_is_2insns, create_simple_focus_bits): Fix some bugs when compiled on real 64-bit hosts. (function_arg_record_value_3, function_arg_record_value_2, function_arg_record_value): Add fully prototyped forward decls. * config/sparc/sparc.md (define_insn cmpsi_insn_sp32): Rename back to cmpsi_insn and use on both 64 and 32 bit targets. (define_insn cmpsi_insn_sp64): Remove. (define_expand zero_extendsidi2): Allow for 32-bit target too. (define_insn zero_extendsidi2_insn): Rename to zero_extendsidi2_insn_sp64. (define_insn zero_extendsidi2_insn_sp32): New pattern and assosciated forced split for it. From-SVN: r21662
This commit is contained in:
David S. Miller
David S. Miller
parent
aaa642460c
commit
2a01c93937
3 changed files with 125 additions and 39 deletions
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@ -1,3 +1,23 @@
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Tue Aug 11 04:46:01 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* config/sparc/sparc.c (sparc_emit_set_const32): INTVAL is of
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type HOST_WIDE_INT.
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(safe_constDI sparc_emit_set_const64_quick1,
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sparc_emit_set_const64_quick2, sparc_emit_set_const64_longway,
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analyze_64bit_constant, const64_is_2insns,
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create_simple_focus_bits): Fix some bugs when compiled on real
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64-bit hosts.
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(function_arg_record_value_3, function_arg_record_value_2,
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function_arg_record_value): Add fully prototyped forward decls.
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* config/sparc/sparc.md (define_insn cmpsi_insn_sp32): Rename back
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to cmpsi_insn and use on both 64 and 32 bit targets.
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(define_insn cmpsi_insn_sp64): Remove.
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(define_expand zero_extendsidi2): Allow for 32-bit target too.
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(define_insn zero_extendsidi2_insn): Rename to
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zero_extendsidi2_insn_sp64.
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(define_insn zero_extendsidi2_insn_sp32): New pattern and
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assosciated forced split for it.
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Mon Aug 10 22:57:24 1998 John Carr <jfc@mit.edu>
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* config/sparc/sparc.md (define_insn jump): Output ba,pt not b,pt
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@ -115,6 +115,7 @@ static void sparc_output_addr_vec PROTO((rtx));
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static void sparc_output_addr_diff_vec PROTO((rtx));
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static void sparc_output_deferred_case_vectors PROTO((void));
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#ifdef DWARF2_DEBUGGING_INFO
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extern char *dwarf2out_cfi_label ();
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#endif
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@ -1040,7 +1041,7 @@ sparc_emit_set_const32 (op0, op1)
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if (GET_CODE (op1) == CONST_INT)
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{
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int value = INTVAL (op1);
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HOST_WIDE_INT value = INTVAL (op1);
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if (SPARC_SETHI_P (value)
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|| SPARC_SIMM13_P (value))
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@ -1192,6 +1193,8 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
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}
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/* This avoids problems when cross compiling. */
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static rtx safe_constDI PROTO((HOST_WIDE_INT));
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static rtx
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safe_constDI(val)
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HOST_WIDE_INT val;
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@ -1211,17 +1214,21 @@ safe_constDI(val)
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such values are similar to something required later on.
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Without doing this, the optimizer cannot see such
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opportunities. */
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static void sparc_emit_set_const64_quick1
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PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
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static void
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sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
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rtx op0;
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rtx temp;
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unsigned int low_bits;
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unsigned HOST_WIDE_INT low_bits;
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int is_neg;
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{
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unsigned int high_bits;
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unsigned HOST_WIDE_INT high_bits;
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if (is_neg)
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high_bits = ~low_bits;
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high_bits = (~low_bits) & 0xffffffff;
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else
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high_bits = low_bits;
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@ -1242,12 +1249,16 @@ sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
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}
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}
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static void sparc_emit_set_const64_quick2
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PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
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unsigned HOST_WIDE_INT, int));
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static void
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sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
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rtx op0;
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rtx temp;
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unsigned int high_bits;
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unsigned int low_immediate;
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unsigned HOST_WIDE_INT high_bits;
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unsigned HOST_WIDE_INT low_immediate;
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int shift_count;
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{
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rtx temp2 = op0;
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@ -1283,14 +1294,17 @@ sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
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safe_constDI (low_immediate & 0x3ff))));
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}
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static void sparc_emit_set_const64_longway
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PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
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/* Full 64-bit constant decomposition. Even though this is the
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'worst' case, we still optimize a few things away. */
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static void
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sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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rtx op0;
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rtx temp;
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unsigned int high_bits;
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unsigned int low_bits;
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unsigned HOST_WIDE_INT high_bits;
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unsigned HOST_WIDE_INT low_bits;
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{
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rtx sub_temp;
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@ -1356,7 +1370,7 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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{
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_ASHIFT (DImode, sub_temp,
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GEN_INT(to_shift))));
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GEN_INT (to_shift))));
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emit_insn (gen_rtx_SET (DImode, op0,
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gen_rtx_IOR (DImode, op0, low1)));
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sub_temp = op0;
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@ -1391,9 +1405,14 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
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}
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/* Analyze a 64-bit constant for certain properties. */
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static void analyze_64bit_constant
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PROTO((unsigned HOST_WIDE_INT,
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unsigned HOST_WIDE_INT,
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int *, int *, int *));
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static void
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analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
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unsigned int high_bits, low_bits;
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unsigned HOST_WIDE_INT high_bits, low_bits;
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int *hbsp, *lbsp, *abbasp;
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{
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int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
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@ -1455,14 +1474,17 @@ analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
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*abbasp = all_bits_between_are_set;
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}
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static int const64_is_2insns
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PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
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static int
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const64_is_2insns (high_bits, low_bits)
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unsigned int high_bits, low_bits;
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unsigned HOST_WIDE_INT high_bits, low_bits;
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{
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int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
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if (high_bits == 0
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|| high_bits == -1)
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|| high_bits == 0xffffffff)
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return 1;
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analyze_64bit_constant (high_bits, low_bits,
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@ -1479,12 +1501,16 @@ const64_is_2insns (high_bits, low_bits)
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return 0;
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}
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static unsigned int
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static unsigned HOST_WIDE_INT create_simple_focus_bits
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PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
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int, int, int));
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static unsigned HOST_WIDE_INT
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create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set, shift)
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unsigned int high_bits, low_bits;
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unsigned HOST_WIDE_INT high_bits, low_bits;
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int highest_bit_set, lowest_bit_set, shift;
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{
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unsigned int hi, lo;
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int hi, lo;
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if (lowest_bit_set < 32)
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{
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@ -1510,7 +1536,7 @@ sparc_emit_set_const64 (op0, op1)
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rtx op0;
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rtx op1;
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{
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unsigned int high_bits, low_bits;
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unsigned HOST_WIDE_INT high_bits, low_bits;
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int lowest_bit_set, highest_bit_set;
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int all_bits_between_are_set;
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int i;
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@ -1536,7 +1562,7 @@ sparc_emit_set_const64 (op0, op1)
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if (GET_CODE (op1) == CONST_DOUBLE)
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{
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#if HOST_BITS_PER_WIDE_INT == 64
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high_bits = CONST_DOUBLE_LOW (op1) >> 32;
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high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
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low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
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#else
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high_bits = CONST_DOUBLE_HIGH (op1);
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@ -1546,7 +1572,7 @@ sparc_emit_set_const64 (op0, op1)
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else
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{
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#if HOST_BITS_PER_WIDE_INT == 64
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high_bits = (INTVAL (op1) >> 32);
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high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
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low_bits = (INTVAL (op1) & 0xffffffff);
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#else
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high_bits = ((INTVAL (op1) < 0) ?
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@ -1582,7 +1608,7 @@ sparc_emit_set_const64 (op0, op1)
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if (((highest_bit_set == 63
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|| lowest_bit_set == 0)
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&& all_bits_between_are_set != 0)
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|| ((highest_bit_set - lowest_bit_set) < 13))
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|| ((highest_bit_set - lowest_bit_set) < 12))
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{
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rtx the_const = constm1_rtx;
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int shift = lowest_bit_set;
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@ -1629,9 +1655,9 @@ sparc_emit_set_const64 (op0, op1)
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* 2) sethi %hi(focus_bits), %reg
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* srlx %reg, shift, %reg
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*/
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if ((highest_bit_set - lowest_bit_set) < 22)
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if ((highest_bit_set - lowest_bit_set) < 21)
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{
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unsigned int focus_bits =
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unsigned HOST_WIDE_INT focus_bits =
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create_simple_focus_bits (high_bits, low_bits,
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highest_bit_set, lowest_bit_set, 10);
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emit_insn (gen_rtx_SET (DImode,
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@ -1659,9 +1685,9 @@ sparc_emit_set_const64 (op0, op1)
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* xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
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*/
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if (high_bits == 0
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|| high_bits == -1)
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|| high_bits == 0xffffffff)
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return sparc_emit_set_const64_quick1 (op0, temp, low_bits,
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(high_bits == -1));
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(high_bits == 0xffffffff));
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/* 1) sethi %hi(high_bits), %reg
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* or %reg, %lo(high_bits), %reg
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@ -1669,7 +1695,7 @@ sparc_emit_set_const64 (op0, op1)
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*/
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if (low_bits == 0
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|| (SPARC_SIMM13_P(low_bits)
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&& ((int)low_bits > 0)))
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&& ((HOST_WIDE_INT)low_bits > 0)))
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return sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
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/* Now, try 3-insn sequences. But first we may be able to do something
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@ -1677,7 +1703,7 @@ sparc_emit_set_const64 (op0, op1)
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if (const64_is_2insns ((~high_bits) & 0xffffffff,
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(~low_bits) & 0xfffffc00))
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{
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unsigned int trailing_bits = (~low_bits) & 0x3ff;
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unsigned HOST_WIDE_INT trailing_bits = (~low_bits) & 0x3ff;
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if ((((~high_bits) & 0xffffffff) == 0
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&& ((~low_bits) & 0x80000000) == 0)
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@ -1718,7 +1744,7 @@ sparc_emit_set_const64 (op0, op1)
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*/
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if ((highest_bit_set - lowest_bit_set) < 32)
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{
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unsigned int hi, lo, focus_bits;
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unsigned HOST_WIDE_INT hi, lo, focus_bits;
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/* We can't get here in this state. */
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if (highest_bit_set < 32
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@ -3373,6 +3399,13 @@ struct function_arg_record_value_parms
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int nregs, intoffset;
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};
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static void function_arg_record_value_3
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PROTO((int, struct function_arg_record_value_parms *));
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static void function_arg_record_value_2
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PROTO((tree, int, struct function_arg_record_value_parms *));
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static rtx function_arg_record_value
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PROTO((tree, enum machine_mode, int, int, int));
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static void
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function_arg_record_value_1 (type, startbitpos, parms)
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tree type;
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@ -562,19 +562,11 @@
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;; Now the compare DEFINE_INSNs.
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(define_insn "*cmpsi_insn_sp32"
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(define_insn "*cmpsi_insn"
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[(set (reg:CC 100)
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(compare:CC (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "arith_operand" "rI")))]
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"TARGET_ARCH32"
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"cmp\\t%0, %1"
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[(set_attr "type" "compare")])
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(define_insn "*cmpsi_insn_sp64"
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[(set (reg:CC 100)
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(compare:CC (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "arith_double_operand" "rHI")))]
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"TARGET_ARCH64"
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""
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"cmp\\t%0, %1"
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[(set_attr "type" "compare")])
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@ -2662,7 +2654,7 @@
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/* Now emit using the real source and destination we found, swapping
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the order if we detect overlap. */
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if (REGNO(dest1) == REGNO(src2))
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if (REGNO (dest1) == REGNO (src2))
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{
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emit_insn (gen_movsi (dest2, src2));
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emit_insn (gen_movsi (dest1, src1));
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@ -3809,10 +3801,10 @@ movtf_is_ok:
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(define_expand "zero_extendsidi2"
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
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"TARGET_ARCH64"
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""
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"")
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(define_insn "*zero_extendsidi2_insn"
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(define_insn "*zero_extendsidi2_insn_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
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"TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
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@ -3822,6 +3814,47 @@ movtf_is_ok:
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[(set_attr "type" "unary,load")
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(set_attr "length" "1")])
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(define_insn "*zero_extendsidi2_insn_sp32"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
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"! TARGET_ARCH64"
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"#"
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[(set_attr "type" "unary")
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(set_attr "length" "2")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
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"! TARGET_ARCH64 && reload_completed"
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[(set (match_dup 2) (match_dup 3))
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(set (match_dup 4) (match_dup 5))]
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"
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{
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rtx dest1, dest2;
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if (GET_CODE (operands[0]) == SUBREG)
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operands[0] = alter_subreg (operands[0]);
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dest1 = gen_highpart (SImode, operands[0]);
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dest2 = gen_lowpart (SImode, operands[0]);
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/* Swap the order in case of overlap. */
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if (REGNO (dest1) == REGNO (operands[1]))
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{
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operands[2] = dest2;
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operands[3] = operands[1];
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operands[4] = dest1;
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operands[5] = const0_rtx;
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}
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else
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{
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operands[2] = dest1;
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operands[3] = const0_rtx;
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operands[4] = dest2;
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operands[5] = operands[1];
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}
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}")
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;; Simplify comparisons of extended values.
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(define_insn "*cmp_zero_extendqisi2"
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