re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right away, to be more efficient for Ryzen and Intel)
PR target/80846 * config/i386/i386.c (ix86_expand_vector_init_general): Handle V2TImode and V4TImode. (ix86_expand_vector_extract): Likewise. * config/i386/sse.md (VMOVE): Enable V4TImode even for just TARGET_AVX512F, instead of only for TARGET_AVX512BW. (ssescalarmode): Handle V4TImode and V2TImode. (VEC_EXTRACT_MODE): Add V4TImode and V2TImode. (*vec_extractv2ti, *vec_extractv4ti): New insns. (VEXTRACTI128_MODE): New mode iterator. (splitter for *vec_extractv?ti first element): New. (VEC_INIT_MODE): New mode iterator. (vec_init<mode>): Consolidate 3 expanders into one using VEC_INIT_MODE mode iterator. * gcc.target/i386/avx-pr80846.c: New test. * gcc.target/i386/avx2-pr80846.c: New test. * gcc.target/i386/avx512f-pr80846.c: New test. From-SVN: r250397
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
f0a404561c
commit
2953b72fdd
7 changed files with 155 additions and 22 deletions
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@ -1,3 +1,20 @@
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2017-07-20 Jakub Jelinek <jakub@redhat.com>
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PR target/80846
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* config/i386/i386.c (ix86_expand_vector_init_general): Handle
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V2TImode and V4TImode.
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(ix86_expand_vector_extract): Likewise.
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* config/i386/sse.md (VMOVE): Enable V4TImode even for just
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TARGET_AVX512F, instead of only for TARGET_AVX512BW.
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(ssescalarmode): Handle V4TImode and V2TImode.
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(VEC_EXTRACT_MODE): Add V4TImode and V2TImode.
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(*vec_extractv2ti, *vec_extractv4ti): New insns.
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(VEXTRACTI128_MODE): New mode iterator.
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(splitter for *vec_extractv?ti first element): New.
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(VEC_INIT_MODE): New mode iterator.
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(vec_init<mode>): Consolidate 3 expanders into one using
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VEC_INIT_MODE mode iterator.
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2017-07-20 Alexander Monakov <amonakov@ispras.ru>
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* lra-assigns.c (pseudo_compare_func): Fix comparison step based on
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@ -44118,6 +44118,26 @@ ix86_expand_vector_init_general (bool mmx_ok, machine_mode mode,
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ix86_expand_vector_init_concat (mode, target, ops, n);
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return;
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case V2TImode:
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for (i = 0; i < 2; i++)
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ops[i] = gen_lowpart (V2DImode, XVECEXP (vals, 0, i));
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op0 = gen_reg_rtx (V4DImode);
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ix86_expand_vector_init_concat (V4DImode, op0, ops, 2);
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emit_move_insn (target, gen_lowpart (GET_MODE (target), op0));
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return;
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case V4TImode:
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for (i = 0; i < 4; i++)
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ops[i] = gen_lowpart (V2DImode, XVECEXP (vals, 0, i));
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ops[4] = gen_reg_rtx (V4DImode);
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ix86_expand_vector_init_concat (V4DImode, ops[4], ops, 2);
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ops[5] = gen_reg_rtx (V4DImode);
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ix86_expand_vector_init_concat (V4DImode, ops[5], ops + 2, 2);
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op0 = gen_reg_rtx (V8DImode);
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ix86_expand_vector_init_concat (V8DImode, op0, ops + 4, 2);
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emit_move_insn (target, gen_lowpart (GET_MODE (target), op0));
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return;
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case V32QImode:
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half_mode = V16QImode;
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goto half;
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@ -44659,6 +44679,8 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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case V2DFmode:
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case V2DImode:
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case V2TImode:
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case V4TImode:
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use_vec_extr = true;
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break;
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@ -175,7 +175,7 @@
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(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI
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(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI
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(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI
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(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX") V1TI
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(V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX") V1TI
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(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF
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(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF])
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@ -687,7 +687,8 @@
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(V16SI "SI") (V8SI "SI") (V4SI "SI")
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(V8DI "DI") (V4DI "DI") (V2DI "DI")
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(V16SF "SF") (V8SF "SF") (V4SF "SF")
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(V8DF "DF") (V4DF "DF") (V2DF "DF")])
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(V8DF "DF") (V4DF "DF") (V2DF "DF")
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(V4TI "TI") (V2TI "TI")])
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;; Mapping of vector modes to the 128bit modes
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(define_mode_attr ssexmmmode
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@ -6920,15 +6921,6 @@
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(set_attr "prefix" "orig,maybe_evex,orig,maybe_evex")
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(set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
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(define_expand "vec_init<mode>"
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[(match_operand:V_128 0 "register_operand")
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(match_operand 1)]
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"TARGET_SSE"
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{
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ix86_expand_vector_init (false, operands[0], operands[1]);
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DONE;
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})
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;; Avoid combining registers from different units in a single alternative,
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;; see comment above inline_secondary_memory_needed function in i386.c
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(define_insn "vec_set<mode>_0"
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@ -7886,7 +7878,8 @@
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(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI
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(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI
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(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF
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(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF])
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(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF
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(V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX")])
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(define_expand "vec_extract<mode>"
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[(match_operand:<ssescalarmode> 0 "register_operand")
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@ -13734,6 +13727,50 @@
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operands[1] = adjust_address (operands[1], <ssescalarmode>mode, offs);
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})
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(define_insn "*vec_extractv2ti"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=xm,vm")
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(vec_select:TI
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(match_operand:V2TI 1 "register_operand" "x,v")
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(parallel
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[(match_operand:SI 2 "const_0_to_1_operand")])))]
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"TARGET_AVX"
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"@
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vextract%~128\t{%2, %1, %0|%0, %1, %2}
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vextracti32x4\t{%2, %g1, %0|%0, %g1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "vex,evex")
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(set_attr "mode" "OI")])
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(define_insn "*vec_extractv4ti"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=vm")
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(vec_select:TI
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(match_operand:V4TI 1 "register_operand" "v")
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(parallel
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[(match_operand:SI 2 "const_0_to_3_operand")])))]
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"TARGET_AVX512F"
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"vextracti32x4\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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(set_attr "mode" "XI")])
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(define_mode_iterator VEXTRACTI128_MODE
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[(V4TI "TARGET_AVX512F") V2TI])
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(define_split
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[(set (match_operand:TI 0 "nonimmediate_operand")
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(vec_select:TI
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(match_operand:VEXTRACTI128_MODE 1 "register_operand")
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(parallel [(const_int 0)])))]
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"TARGET_AVX
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&& reload_completed
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&& (TARGET_AVX512VL || !EXT_REX_SSE_REG_P (operands[1]))"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = gen_lowpart (TImode, operands[1]);")
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;; Turn SImode or DImode extraction from arbitrary SSE/AVX/AVX512F
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;; vector modes into vec_extract*.
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(define_split
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@ -18738,19 +18775,20 @@
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<ssehalfvecmode>mode);
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})
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(define_expand "vec_init<mode>"
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[(match_operand:V_256 0 "register_operand")
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(match_operand 1)]
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"TARGET_AVX"
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{
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ix86_expand_vector_init (false, operands[0], operands[1]);
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DONE;
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})
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;; Modes handled by vec_init patterns.
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(define_mode_iterator VEC_INIT_MODE
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[(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI
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(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI
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(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI
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(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI
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(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF
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(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")
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(V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX")])
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(define_expand "vec_init<mode>"
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[(match_operand:VF48_I1248 0 "register_operand")
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[(match_operand:VEC_INIT_MODE 0 "register_operand")
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(match_operand 1)]
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"TARGET_AVX512F"
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"TARGET_SSE"
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{
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ix86_expand_vector_init (false, operands[0], operands[1]);
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DONE;
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@ -1,3 +1,10 @@
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2017-07-20 Jakub Jelinek <jakub@redhat.com>
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PR target/80846
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* gcc.target/i386/avx-pr80846.c: New test.
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* gcc.target/i386/avx2-pr80846.c: New test.
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* gcc.target/i386/avx512f-pr80846.c: New test.
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2017-07-20 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/81388
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39
gcc/testsuite/gcc.target/i386/avx-pr80846.c
Normal file
39
gcc/testsuite/gcc.target/i386/avx-pr80846.c
Normal file
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@ -0,0 +1,39 @@
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/* PR target/80846 */
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2 -mavx -mno-avx2" } */
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typedef __int128 V __attribute__((vector_size (32)));
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typedef long long W __attribute__((vector_size (32)));
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typedef int X __attribute__((vector_size (16)));
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typedef __int128 Y __attribute__((vector_size (64)));
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typedef long long Z __attribute__((vector_size (64)));
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W f1 (__int128 x, __int128 y) { return (W) ((V) { x, y }); }
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__int128 f2 (W x) { return ((V)x)[0]; }
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__int128 f3 (W x) { return ((V)x)[1]; }
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W f4 (X x, X y) { union { X x; __int128 i; } u = { .x = x }, v = { .x = y }; return (W) ((V) { u.i, v.i }); }
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X f5 (W x) { return (X)(((V)x)[0]); }
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X f6 (W x) { return (X)(((V)x)[1]); }
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W f7 (void) { return (W) ((V) { 2, 3 }); }
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W f8 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { u.i, 3 }); }
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W f9 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { 2, u.i }); }
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W f10 (X x) { union { X x; __int128 i; } u = { .x = x }; return (W) ((V) { u.i, u.i }); }
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#ifdef __AVX512F__
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Z f11 (__int128 x, __int128 y, __int128 z, __int128 a) { return (Z) ((Y) { x, y, z, a }); }
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__int128 f12 (Z x) { return ((Y)x)[0]; }
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__int128 f13 (Z x) { return ((Y)x)[1]; }
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__int128 f14 (Z x) { return ((Y)x)[2]; }
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__int128 f15 (Z x) { return ((Y)x)[3]; }
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Z f16 (X x, X y, X z, X a) { union { X x; __int128 i; } u = { .x = x }, v = { .x = y }, w = { .x = z }, t = { .x = a };
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return (Z) ((Y) { u.i, v.i, w.i, t.i }); }
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X f17 (Z x) { return (X)(((Y)x)[0]); }
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X f18 (Z x) { return (X)(((Y)x)[1]); }
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X f19 (Z x) { return (X)(((Y)x)[2]); }
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X f20 (Z x) { return (X)(((Y)x)[3]); }
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Z f21 (void) { return (Z) ((Y) { 2, 3, 4, 5 }); }
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Z f22 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { u.i, 3, 4, 5 }); }
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Z f23 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, u.i, 4, 5 }); }
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Z f24 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, 3, u.i, 5 }); }
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Z f25 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { 2, 3, 4, u.i }); }
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Z f26 (X x) { union { X x; __int128 i; } u = { .x = x }; return (Z) ((Y) { u.i, u.i, u.i, u.i }); }
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#endif
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5
gcc/testsuite/gcc.target/i386/avx2-pr80846.c
Normal file
5
gcc/testsuite/gcc.target/i386/avx2-pr80846.c
Normal file
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@ -0,0 +1,5 @@
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/* PR target/80846 */
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2 -mavx2 -mno-avx512f" } */
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#include "avx-pr80846.c"
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5
gcc/testsuite/gcc.target/i386/avx512f-pr80846.c
Normal file
5
gcc/testsuite/gcc.target/i386/avx512f-pr80846.c
Normal file
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@ -0,0 +1,5 @@
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/* PR target/80846 */
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2 -mavx512f" } */
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#include "avx-pr80846.c"
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