re PR target/35189 (-mno-sse4.2 turns off SSE4a)

gcc/

2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/35189
	* config/i386/i386.c (OPTION_MASK_ISA_MMX_SET): New.
	(OPTION_MASK_ISA_3DNOW_SET): Likewise.
	(OPTION_MASK_ISA_SSE_SET): Likewise.
	(OPTION_MASK_ISA_SSE2_SET): Likewise.
	(OPTION_MASK_ISA_SSE3_SET): Likewise.
	(OPTION_MASK_ISA_SSSE3_SET): Likewise.
	(OPTION_MASK_ISA_SSE4_1_SET): Likewise.
	(OPTION_MASK_ISA_SSE4_2_SET): Likewise.
	(OPTION_MASK_ISA_SSE4_SET): Likewise.
	(OPTION_MASK_ISA_SSE4A_SET): Likewise.
	(OPTION_MASK_ISA_SSE5_SET): Likewise.
	(OPTION_MASK_ISA_3DNOW_A_UNSET): Likewise.
	(OPTION_MASK_ISA_MMX_UNSET): Updated.
	(OPTION_MASK_ISA_3DNOW_UNSET): Updated.
	(OPTION_MASK_ISA_SSE_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE3_UNSET): Likewise.
	(OPTION_MASK_ISA_SSSE3_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE4_1_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE4_2_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE4A_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE5_UNSET): Likewise.
	(OPTION_MASK_ISA_SSE4): Removed.
	(ix86_handle_option): Turn on bits in ix86_isa_flags and
	ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for
	-mXXX.
	(override_options): Don't turn on implied SSE/MMX bits in
	ix86_isa_flags.

gcc/testsuite/

2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/35189
	* gcc.target/i386/isa-1.c: New.
	* gcc.target/i386/isa-2.c: Likewise.
	* gcc.target/i386/isa-3.c: Likewise.
	* gcc.target/i386/isa-4.c: Likewise.
	* gcc.target/i386/isa-5.c: Likewise.
	* gcc.target/i386/isa-6.c: Likewise.
	* gcc.target/i386/isa-7.c: Likewise.
	* gcc.target/i386/isa-8.c: Likewise.
	* gcc.target/i386/isa-9.c: Likewise.
	* gcc.target/i386/isa-10.c: Likewise.
	* gcc.target/i386/isa-11.c: Likewise.
	* gcc.target/i386/isa-12.c: Likewise.
	* gcc.target/i386/isa-13.c: Likewise.
	* gcc.target/i386/isa-14.c: Likewise.

From-SVN: r132403
This commit is contained in:
H.J. Lu 2008-02-19 01:21:03 +00:00 committed by H.J. Lu
parent 2c9e3ddaf9
commit 287a7d41f5
17 changed files with 639 additions and 76 deletions

View file

@ -1,3 +1,34 @@
2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
PR target/35189
* config/i386/i386.c (OPTION_MASK_ISA_MMX_SET): New.
(OPTION_MASK_ISA_3DNOW_SET): Likewise.
(OPTION_MASK_ISA_SSE_SET): Likewise.
(OPTION_MASK_ISA_SSE2_SET): Likewise.
(OPTION_MASK_ISA_SSE3_SET): Likewise.
(OPTION_MASK_ISA_SSSE3_SET): Likewise.
(OPTION_MASK_ISA_SSE4_1_SET): Likewise.
(OPTION_MASK_ISA_SSE4_2_SET): Likewise.
(OPTION_MASK_ISA_SSE4_SET): Likewise.
(OPTION_MASK_ISA_SSE4A_SET): Likewise.
(OPTION_MASK_ISA_SSE5_SET): Likewise.
(OPTION_MASK_ISA_3DNOW_A_UNSET): Likewise.
(OPTION_MASK_ISA_MMX_UNSET): Updated.
(OPTION_MASK_ISA_3DNOW_UNSET): Updated.
(OPTION_MASK_ISA_SSE_UNSET): Likewise.
(OPTION_MASK_ISA_SSE3_UNSET): Likewise.
(OPTION_MASK_ISA_SSSE3_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4_1_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4_2_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4A_UNSET): Likewise.
(OPTION_MASK_ISA_SSE5_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4): Removed.
(ix86_handle_option): Turn on bits in ix86_isa_flags and
ix86_isa_flags_explicit with OPTION_MASK_ISA_XXX_SET for
-mXXX.
(override_options): Don't turn on implied SSE/MMX bits in
ix86_isa_flags.
2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386-modes.def: Use 4 byte alignment on DI for

View file

@ -1768,35 +1768,65 @@ int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
was set or cleared on the command line. */
static int ix86_isa_flags_explicit;
/* Define a set of ISAs which aren't available for a given ISA. MMX
and SSE ISAs are handled separately. */
/* Define a set of ISAs which are available when a given ISA is
enabled. MMX and SSE ISAs are handled separately. */
#define OPTION_MASK_ISA_MMX_UNSET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
#define OPTION_MASK_ISA_3DNOW_UNSET OPTION_MASK_ISA_3DNOW_A
#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
#define OPTION_MASK_ISA_3DNOW_SET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
#define OPTION_MASK_ISA_SSE_UNSET \
(OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE2_UNSET)
#define OPTION_MASK_ISA_SSE2_UNSET \
(OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE3_UNSET)
#define OPTION_MASK_ISA_SSE3_UNSET \
(OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSSE3_UNSET)
#define OPTION_MASK_ISA_SSSE3_UNSET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_1_UNSET)
#define OPTION_MASK_ISA_SSE4_1_UNSET \
(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_2_UNSET)
#define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4A
#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
#define OPTION_MASK_ISA_SSE2_SET \
(OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
#define OPTION_MASK_ISA_SSE3_SET \
(OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
#define OPTION_MASK_ISA_SSSE3_SET \
(OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
#define OPTION_MASK_ISA_SSE4_1_SET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
#define OPTION_MASK_ISA_SSE4_2_SET \
(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.1 -msse4.2. -mno-sse4 should the same as -mno-sse4.1. */
#define OPTION_MASK_ISA_SSE4 \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2)
as -msse4.2. */
#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
#define OPTION_MASK_ISA_SSE4A_SET \
(OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
#define OPTION_MASK_ISA_SSE5_SET \
(OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
/* Define a set of ISAs which aren't available when a given ISA is
disabled. MMX and SSE ISAs are handled separately. */
#define OPTION_MASK_ISA_MMX_UNSET \
(OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
#define OPTION_MASK_ISA_3DNOW_UNSET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
#define OPTION_MASK_ISA_SSE_UNSET \
(OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
#define OPTION_MASK_ISA_SSE2_UNSET \
(OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
#define OPTION_MASK_ISA_SSE3_UNSET \
(OPTION_MASK_ISA_SSE3 \
| OPTION_MASK_ISA_SSSE3_UNSET \
| OPTION_MASK_ISA_SSE4A_UNSET )
#define OPTION_MASK_ISA_SSSE3_UNSET \
(OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
#define OPTION_MASK_ISA_SSE4_1_UNSET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
#define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
#define OPTION_MASK_ISA_SSE4A_UNSET OPTION_MASK_ISA_SSE4
#define OPTION_MASK_ISA_SSE4A_UNSET \
(OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
#define OPTION_MASK_ISA_SSE5_UNSET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
#define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
/* Vectorization library interface and handlers. */
tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
@ -1810,8 +1840,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
switch (code)
{
case OPT_mmmx:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
@ -1819,8 +1853,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_m3dnow:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
@ -1831,8 +1869,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return false;
case OPT_msse:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
@ -1840,8 +1882,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse2:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
@ -1849,8 +1895,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse3:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
@ -1858,8 +1908,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_mssse3:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
@ -1867,8 +1921,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse4_1:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
@ -1876,8 +1934,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse4_2:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
@ -1885,8 +1947,8 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse4:
ix86_isa_flags |= OPTION_MASK_ISA_SSE4;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4;
ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
return true;
case OPT_mno_sse4:
@ -1895,8 +1957,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse4a:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
@ -1904,8 +1970,12 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
return true;
case OPT_msse5:
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5;
if (!value)
if (value)
{
ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
}
else
{
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
@ -2530,34 +2600,6 @@ override_options (void)
if (!TARGET_80387)
target_flags |= MASK_NO_FANCY_MATH_387;
/* Turn on SSE4A bultins for -msse5. */
if (TARGET_SSE5)
ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
/* Turn on SSE4.1 builtins for -msse4.2. */
if (TARGET_SSE4_2)
ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
/* Turn on SSSE3 builtins for -msse4.1. */
if (TARGET_SSE4_1)
ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
/* Turn on SSE3 builtins for -mssse3. */
if (TARGET_SSSE3)
ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
/* Turn on SSE3 builtins for -msse4a. */
if (TARGET_SSE4A)
ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
/* Turn on SSE2 builtins for -msse3. */
if (TARGET_SSE3)
ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
/* Turn on SSE builtins for -msse2. */
if (TARGET_SSE2)
ix86_isa_flags |= OPTION_MASK_ISA_SSE;
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE)
{
@ -2565,10 +2607,6 @@ override_options (void)
x86_prefetch_sse = true;
}
/* Turn on MMX builtins for 3Dnow. */
if (TARGET_3DNOW)
ix86_isa_flags |= OPTION_MASK_ISA_MMX;
/* Turn on popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2 || TARGET_ABM)
x86_popcnt = true;

View file

@ -1,3 +1,21 @@
2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
PR target/35189
* gcc.target/i386/isa-1.c: New.
* gcc.target/i386/isa-2.c: Likewise.
* gcc.target/i386/isa-3.c: Likewise.
* gcc.target/i386/isa-4.c: Likewise.
* gcc.target/i386/isa-5.c: Likewise.
* gcc.target/i386/isa-6.c: Likewise.
* gcc.target/i386/isa-7.c: Likewise.
* gcc.target/i386/isa-8.c: Likewise.
* gcc.target/i386/isa-9.c: Likewise.
* gcc.target/i386/isa-10.c: Likewise.
* gcc.target/i386/isa-11.c: Likewise.
* gcc.target/i386/isa-12.c: Likewise.
* gcc.target/i386/isa-13.c: Likewise.
* gcc.target/i386/isa-14.c: Likewise.
2008-02-18 Joey Ye <joey.ye@intel.com>
H.J. Lu <hongjiu.lu@intel.com>

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if !defined __SSSE3__
abort ();
#endif
#if !defined __SSE4_1__
abort ();
#endif
#if !defined __SSE4_2__
abort ();
#endif
#if defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse5 -mno-sse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse5 -mno-ssse3" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse5 -mno-sse3" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse5 -mno-sse2" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if defined __SSE2__
abort ();
#endif
#if defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse5 -mno-sse" } */
extern void abort (void);
int
main ()
{
#if defined __SSE__
abort ();
#endif
#if defined __SSE2__
abort ();
#endif
#if defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse4 -msse5" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if !defined __SSSE3__
abort ();
#endif
#if !defined __SSE4_1__
abort ();
#endif
#if !defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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@ -0,0 +1,34 @@
/* { dg-do run } */
/* { dg-options "-msse4 -msse5 -msse4a" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if !defined __SSSE3__
abort ();
#endif
#if !defined __SSE4_1__
abort ();
#endif
#if !defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=core2 -msse5 -mno-sse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if !defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=core2 -msse4a -mno-sse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if !defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=amdfam10 -mno-sse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=amdfam10 -msse5 -mno-sse4" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if !defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=amdfam10 -msse5 -mno-sse4a" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}

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/* { dg-do run } */
/* { dg-options "-march=amdfam10 -mno-sse5" } */
extern void abort (void);
int
main ()
{
#if !defined __SSE__
abort ();
#endif
#if !defined __SSE2__
abort ();
#endif
#if !defined __SSE3__
abort ();
#endif
#if defined __SSSE3__
abort ();
#endif
#if defined __SSE4_1__
abort ();
#endif
#if defined __SSE4_2__
abort ();
#endif
#if !defined __SSE4A__
abort ();
#endif
#if defined __SSE5__
abort ();
#endif
return 0;
}