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i386: Fix FAIL of gcc.target/i386/pr91681-1.c

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The recent change in TImode parameter passing on x86_64 results in the
FAIL of pr91681-1.c.  The issue is that with the extra flexibility,
the combine pass is now spoilt for choice between using either the
*add<dwi>3_doubleword_concat or the *add<dwi>3_doubleword_zext
patterns, when one operand is a *concat and the other is a zero_extend.
The solution proposed below is provide an *add<dwi>3_doubleword_concat_zext
define_insn_and_split, that can benefit both from the register allocation
of *concat, and still avoid the xor normally required by zero extension.

I'm investigating a follow-up refinement to improve register allocation
further by avoiding the early clobber in the =&r, and handling (custom)
reloads explicitly, but this piece resolves the testcase failure.

2023-07-12  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	PR target/91681
	* config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): New
	define_insn_and_split derived from *add<dwi>3_doubleword_concat
	and *add<dwi>3_doubleword_zext.
This commit is contained in:
Roger Sayle 2023-07-12 14:14:15 +01:00
parent d2c18b4a16
commit 275a2124e4
1 changed files with 33 additions and 0 deletions
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33
gcc/config/i386/i386.md
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@ -6294,6 +6294,39 @@
(clobber (reg:CC FLAGS_REG))])]
"split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[5]);")
(define_insn_and_split "*add<dwi>3_doubleword_concat_zext"
[(set (match_operand:<DWI> 0 "register_operand" "=&r")
(plus:<DWI>
(any_or_plus:<DWI>
(ashift:<DWI>
(zero_extend:<DWI>
(match_operand:DWIH 2 "nonimmediate_operand" "rm"))
(match_operand:QI 3 "const_int_operand"))
(zero_extend:<DWI>
(match_operand:DWIH 4 "nonimmediate_operand" "rm")))
(zero_extend:<DWI>
(match_operand:DWIH 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))
(set (match_dup 5) (match_dup 2))
(parallel [(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:DWIH (match_dup 0) (match_dup 1))
(match_dup 0)))
(set (match_dup 0)
(plus:DWIH (match_dup 0) (match_dup 1)))])
(parallel [(set (match_dup 5)
(plus:DWIH
(plus:DWIH
(ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
(match_dup 5))
(const_int 0)))
(clobber (reg:CC FLAGS_REG))])]
"split_double_mode (<DWI>mode, &operands[0], 1, &operands[0], &operands[5]);")
(define_insn "*add<mode>_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r")
(plus:SWI48