[AArch64][SVE] Remove unnecessary PTRUEs from integer arithmetic
When using the unpredicated immediate forms of MUL, LSL, LSR and ASR, the rtl patterns would still have the predicate operand we created for the other forms. This patch splits the patterns after reload in order to get rid of the predicate, like we already do for WHILE. 2018-12-07 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (*mul<mode>3, *v<optab><mode>3): Split the patterns after reload if we don't need the predicate operand. (*post_ra_mul<mode>3, *post_ra_v<optab><mode>3): New patterns. gcc/testsuite/ * gcc.target/aarch64/sve/pred_elim_2.c: New test. From-SVN: r266892
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Richard Sandiford
Richard Sandiford
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commit
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4 changed files with 80 additions and 4 deletions
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@ -1,3 +1,10 @@
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2018-12-07 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md (*mul<mode>3, *v<optab><mode>3):
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Split the patterns after reload if we don't need the predicate
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operand.
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(*post_ra_mul<mode>3, *post_ra_v<optab><mode>3): New patterns.
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2018-12-07 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_UNPRED_FP_BINARY): New code
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@ -936,7 +936,7 @@
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;; predicate for the first alternative, but using Upa or X isn't likely
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;; to gain much and would make the instruction seem less uniform to the
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;; register allocator.
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(define_insn "*mul<mode>3"
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(define_insn_and_split "*mul<mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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@ -946,12 +946,30 @@
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UNSPEC_MERGE_PTRUE))]
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"TARGET_SVE"
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"@
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mul\t%0.<Vetype>, %0.<Vetype>, #%3
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#
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mul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;mul\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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; Split the unpredicated form after reload, so that we don't have
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; the unnecessary PTRUE.
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (mult:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,yes")]
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)
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;; Unpredicated multiplications by a constant (post-RA only).
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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(define_insn "*post_ra_mul<mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(mult:SVE_I
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(match_operand:SVE_I 1 "register_operand" "0")
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(match_operand:SVE_I 2 "aarch64_sve_mul_immediate")))]
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"TARGET_SVE && reload_completed"
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"mul\t%0.<Vetype>, %0.<Vetype>, #%2"
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)
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(define_insn "*madd<mode>"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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(plus:SVE_I
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@ -1232,7 +1250,7 @@
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;; actually need the predicate for the first alternative, but using Upa
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;; or X isn't likely to gain much and would make the instruction seem
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;; less uniform to the register allocator.
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(define_insn "*v<optab><mode>3"
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(define_insn_and_split "*v<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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@ -1242,12 +1260,28 @@
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UNSPEC_MERGE_PTRUE))]
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"TARGET_SVE"
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"@
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<shift>\t%0.<Vetype>, %2.<Vetype>, #%3
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#
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<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (ASHIFT:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,yes")]
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)
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;; Unpredicated shift operations by a constant (post-RA only).
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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(define_insn "*post_ra_v<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(ASHIFT:SVE_I
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(match_operand:SVE_I 1 "register_operand" "w")
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(match_operand:SVE_I 2 "aarch64_simd_<lr>shift_imm")))]
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"TARGET_SVE && reload_completed"
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"<shift>\t%0.<Vetype>, %1.<Vetype>, #%2"
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)
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;; LSL, LSR and ASR by a scalar, which expands into one of the vector
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;; shifts above.
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(define_expand "<ASHIFT:optab><mode>3"
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@ -1,3 +1,7 @@
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2018-12-07 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/pred_elim_2.c: New test.
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2018-12-07 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/pred_elim_1.c: New test.
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31
gcc/testsuite/gcc.target/aarch64/sve/pred_elim_2.c
Normal file
31
gcc/testsuite/gcc.target/aarch64/sve/pred_elim_2.c
Normal file
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@ -0,0 +1,31 @@
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define TEST_OP(NAME, TYPE, OP) \
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void \
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NAME##_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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a[i] = b[i] OP; \
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}
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#define TEST_TYPE(TYPE) \
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TEST_OP (shl, TYPE, << 6) \
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TEST_OP (shr, TYPE, >> 6) \
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TEST_OP (mult, TYPE, * 0x2b)
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TEST_TYPE (int8_t)
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TEST_TYPE (int16_t)
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TEST_TYPE (int32_t)
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TEST_TYPE (int64_t)
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TEST_TYPE (uint8_t)
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TEST_TYPE (uint16_t)
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TEST_TYPE (uint32_t)
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TEST_TYPE (uint64_t)
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/* { dg-final { scan-assembler-times {\tlsl\t} 8 } } */
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/* { dg-final { scan-assembler-times {\tlsr\t} 4 } } */
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/* { dg-final { scan-assembler-times {\tasr\t} 4 } } */
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/* { dg-final { scan-assembler-times {\tmul\t} 8 } } */
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/* { dg-final { scan-assembler-not {\tptrue\t} } } */
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