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simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.

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* config/arc/simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.
        (UNSPEC_ARC_SIMD_VLD32WL): Likewise.
        (vld32wh_insn, vld32wl_insn): Delete commented-out old
        versions of these patterns.

From-SVN: r203078
This commit is contained in:
Joern Rennecke 2013-10-01 18:40:27 +00:00 • committed by Joern Rennecke
parent 4167a189f6
commit 25c606cb18
2 changed files with 7 additions and 21 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
* config/arc/simdext.md (UNSPEC_ARC_SIMD_VLD32WH): Delete.
(UNSPEC_ARC_SIMD_VLD32WL): Likewise.
(vld32wh_insn, vld32wl_insn): Delete commented-out old
versions of these patterns.
2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
* config/arc/arc.c (arc_conditional_register_usage):

21
gcc/config/arc/simdext.md
View file

@ -126,9 +126,6 @@
(UNSPEC_ARC_SIMD_VRECRUN 1107)
(UNSPEC_ARC_SIMD_VENDREC 1108)
(UNSPEC_ARC_SIMD_VLD32WH 1110)
(UNSPEC_ARC_SIMD_VLD32WL 1111)
(UNSPEC_ARC_SIMD_VCAST 1200)
(UNSPEC_ARC_SIMD_VINTI 1201)
]
@ -1195,24 +1192,6 @@
(set_attr "length" "4")
(set_attr "cond" "nocond")])
;; Va, [Ib,u8] instructions
;; (define_insn "vld32wh_insn"
;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
;; (vec_concat:V8HI (unspec:V4HI [(match_operand:SI 1 "immediate_operand" "P")
;; (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
;; (parallel [(match_operand:SI 3 "immediate_operand" "L")]))] UNSPEC_ARC_SIMD_VLD32WH)
;; (vec_select:V4HI (match_dup 0)
;; (parallel[(const_int 0)]))))]
;; (define_insn "vld32wl_insn"
;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
;; (unspec:V8HI [(match_operand:SI 1 "immediate_operand" "L")
;; (match_operand:SI 2 "immediate_operand" "P")
;; (match_operand:V8HI 3 "vector_register_operand" "v")
;; (match_dup 0)] UNSPEC_ARC_SIMD_VLD32WL))]
;; "TARGET_SIMD_SET"
;; "vld32wl %0, [I%1,%2]"
;; [(set_attr "length" "4")
;; (set_attr "cond" "nocond")])
(define_insn "vld32wh_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")