rs6000: Add vclrlb and vclrrb
Add new vector instructions to clear leftmost and rightmost bytes. [gcc] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.h (vec_clrl): New #define. (vec_clrr): Likewise. * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant. (UNSPEC_VCLRRB): Likewise. (vclrlb): New insn. (vclrrb): Likewise. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New built-in function. (__builtin_altivec_vclrrb): Likewise. (__builtin_vec_clrl): New overloaded built-in function. (__builtin_vec_clrr): Likewise. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Define overloaded forms of __builtin_vec_clrl and __builtin_vec_clrr. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add descriptions of vec_clrl and vec_clrr. [gcc/testsuite] 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-clrl-0.c: New. * gcc.target/powerpc/vec-clrl-1.c: New. * gcc.target/powerpc/vec-clrr-0.c: New. * gcc.target/powerpc/vec-clrr-1.c: New.
This commit is contained in:
Kelvin Nilsen
Bill Schmidt
parent
0e47fe3ab5
commit
25bf7d32c3
15 changed files with 309 additions and 0 deletions
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@ -1,3 +1,23 @@
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2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* config/rs6000/altivec.h (vec_clrl): New #define.
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(vec_clrr): Likewise.
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* config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
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(UNSPEC_VCLRRB): Likewise.
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(vclrlb): New insn.
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(vclrrb): Likewise.
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* config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
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built-in function.
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(__builtin_altivec_vclrrb): Likewise.
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(__builtin_vec_clrl): New overloaded built-in function.
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(__builtin_vec_clrr): Likewise.
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* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
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Define overloaded forms of __builtin_vec_clrl and
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__builtin_vec_clrr.
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* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
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for a Future Architecture): Add descriptions of vec_clrl and
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vec_clrr.
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2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
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@ -697,6 +697,8 @@ __altivec_scalar_pred(vec_any_nle,
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/* Overloaded built-in functions for future architecture. */
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#define vec_gnb(a, b) __builtin_vec_gnb (a, b)
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#define vec_clrl(a, b) __builtin_vec_clrl (a, b)
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#define vec_clrr(a, b) __builtin_vec_clrr (a, b)
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#endif
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#endif /* _ALTIVEC_H */
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@ -166,6 +166,8 @@
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UNSPEC_VGNB
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UNSPEC_VPDEPD
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UNSPEC_VPEXTD
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UNSPEC_VCLRLB
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UNSPEC_VCLRRB
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])
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(define_c_enum "unspecv"
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@ -4156,6 +4158,33 @@
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"vgnb %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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(define_insn "vclrlb"
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[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
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(unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_VCLRLB))]
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"TARGET_FUTURE"
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{
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if (BYTES_BIG_ENDIAN)
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return "vclrlb %0,%1,%2";
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else
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return "vclrrb %0,%1,%2";
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}
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[(set_attr "type" "vecsimple")])
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(define_insn "vclrrb"
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[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
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(unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_VCLRRB))]
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"TARGET_FUTURE"
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{
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if (BYTES_BIG_ENDIAN)
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return "vclrrb %0,%1,%2";
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else
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return "vclrlb %0,%1,%2";
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}
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[(set_attr "type" "vecsimple")])
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(define_expand "bcd<bcd_add_sub>_<code>"
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[(parallel [(set (reg:CCFP CR6_REGNO)
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@ -2579,6 +2579,8 @@ BU_FUTURE_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm)
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BU_FUTURE_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm)
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/* Future architecture vector built-ins. */
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BU_FUTURE_V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
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BU_FUTURE_V_2 (VCLRRB, "vclrrb", CONST, vclrrb)
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BU_FUTURE_V_2 (VCFUGED, "vcfuged", CONST, vcfuged)
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BU_FUTURE_V_2 (VCLZDM, "vclzdm", CONST, vclzdm)
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BU_FUTURE_V_2 (VCTZDM, "vctzdm", CONST, vctzdm)
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@ -2587,6 +2589,8 @@ BU_FUTURE_V_2 (VPEXTD, "vpextd", CONST, vpextd)
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BU_FUTURE_V_2 (VGNB, "vgnb", CONST, vgnb)
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/* Future architecture overloaded vector built-ins. */
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BU_FUTURE_OVERLOAD_2 (CLRL, "clrl")
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BU_FUTURE_OVERLOAD_2 (CLRR, "clrr")
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BU_FUTURE_OVERLOAD_2 (GNB, "gnb")
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@ -5506,6 +5506,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_INTSI, RS6000_BTI_INTSI },
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/* FUTURE overloaded builtin functions, */
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{ FUTURE_BUILTIN_VEC_CLRL, FUTURE_BUILTIN_VCLRLB,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
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{ FUTURE_BUILTIN_VEC_CLRL, FUTURE_BUILTIN_VCLRLB,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
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RS6000_BTI_UINTSI, 0 },
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{ FUTURE_BUILTIN_VEC_CLRR, FUTURE_BUILTIN_VCLRRB,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
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{ FUTURE_BUILTIN_VEC_CLRR, FUTURE_BUILTIN_VCLRRB,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
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RS6000_BTI_UINTSI, 0 },
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{ FUTURE_BUILTIN_VEC_GNB, FUTURE_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
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{ FUTURE_BUILTIN_VEC_GNB, FUTURE_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
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@ -20760,6 +20760,30 @@ Perform a vector count trailing zeros under bit mask operation, as if
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implemented by the Future @code{vctzdm} instruction.
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@findex vec_ctzm
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@smallexample
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@exdent vector signed char
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@exdent vec_clrl (vector signed char a, unsigned int n)
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@exdent vector unsigned char
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@exdent vec_clrl (vector unsigned char a, unsigned int n)
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@end smallexample
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Clear the left-most @code{(16 - n)} bytes of vector argument @code{a}, as if
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implemented by the @code{vclrlb} instruction on a big-endian target
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and by the @code{vclrrb} instruction on a little-endian target. A
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value of @code{n} that is greater than 16 is treated as if it equaled 16.
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@findex vec_clrl
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@smallexample
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@exdent vector signed char
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@exdent vec_clrr (vector signed char a, unsigned int n)
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@exdent vector unsigned char
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@exdent vec_clrr (vector unsigned char a, unsigned int n)
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@end smallexample
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Clear the right-most @code{(16 - n)} bytes of vector argument @code{a}, as if
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implemented by the @code{vclrrb} instruction on a big-endian target
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and by the @code{vclrlb} instruction on a little-endian target. A
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value of @code{n} that is greater than 16 is treated as if it equaled 16.
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@findex vec_clrr
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@smallexample
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@exdent vector unsigned long long int
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@exdent vec_gnb (vector unsigned char, const unsigned char)
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@ -1,3 +1,10 @@
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2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* gcc.target/powerpc/vec-clrl-0.c: New.
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* gcc.target/powerpc/vec-clrl-1.c: New.
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* gcc.target/powerpc/vec-clrr-0.c: New.
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* gcc.target/powerpc/vec-clrr-1.c: New.
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2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
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* gcc.target/powerpc/cntlzdm-0.c: New test.
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16
gcc/testsuite/gcc.target/powerpc/vec-clrl-0.c
Normal file
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gcc/testsuite/gcc.target/powerpc/vec-clrl-0.c
Normal file
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@ -0,0 +1,16 @@
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/* { dg-do compile } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear left-most bytes of unsigned char. */
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vector unsigned char
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clrl (vector unsigned char arg, int n)
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{
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return vec_clrl (arg, n);
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}
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/* { dg-final { scan-assembler {\mvclrlb\M} { target be } } } */
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/* { dg-final { scan-assembler {\mvclrrb\M} { target le } } } */
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37
gcc/testsuite/gcc.target/powerpc/vec-clrl-1.c
Normal file
37
gcc/testsuite/gcc.target/powerpc/vec-clrl-1.c
Normal file
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@ -0,0 +1,37 @@
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/* { dg-do run } */
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/* { dg-require-effective-target powerpc_future_hw } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear left-most bytes of unsigned char. */
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vector unsigned char
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clrl (vector unsigned char arg, int n)
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{
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return vec_clrl (arg, n);
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}
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int main (int argc, char *argv [])
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{
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vector unsigned char input0 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector unsigned char expected0 =
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{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector unsigned char expected1 =
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{ 0x0, 0x0, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector unsigned char expected2 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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if (!vec_all_eq (clrl (input0, 5), expected0))
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abort ();
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if (!vec_all_eq (clrl (input0, 13), expected1))
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abort ();
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if (!vec_all_eq (clrl (input0, 19), expected2))
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abort ();
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}
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16
gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c
Normal file
16
gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c
Normal file
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/* { dg-do compile } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear left-most bytes of unsigned char. */
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vector signed char
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clrl (vector signed char arg, int n)
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{
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return vec_clrl (arg, n);
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}
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/* { dg-final { scan-assembler {\mvclrlb\M} { target be } } } */
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/* { dg-final { scan-assembler {\mvclrrb\M} { target le } } } */
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37
gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c
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37
gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c
Normal file
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/* { dg-do run } */
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/* { dg-require-effective-target powerpc_future_hw } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear left-most bytes of unsigned char. */
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vector signed char
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clrl (vector signed char arg, int n)
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{
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return vec_clrl (arg, n);
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}
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int main (int argc, char *argv [])
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{
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vector signed char input0 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector signed char expected0 =
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{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector signed char expected1 =
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{ 0x0, 0x0, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector signed char expected2 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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if (!vec_all_eq (clrl (input0, 5), expected0))
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abort ();
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if (!vec_all_eq (clrl (input0, 13), expected1))
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abort ();
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if (!vec_all_eq (clrl (input0, 19), expected2))
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abort ();
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}
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16
gcc/testsuite/gcc.target/powerpc/vec-clrr-0.c
Normal file
16
gcc/testsuite/gcc.target/powerpc/vec-clrr-0.c
Normal file
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/* { dg-do compile } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear right-most bytes of unsigned char. */
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vector unsigned char
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clrr (vector unsigned char arg, int n)
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{
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return vec_clrr (arg, n);
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}
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/* { dg-final { scan-assembler {\mvclrrb\M} { target be } } } */
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/* { dg-final { scan-assembler {\mvclrlb\M} { target le } } } */
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37
gcc/testsuite/gcc.target/powerpc/vec-clrr-1.c
Normal file
37
gcc/testsuite/gcc.target/powerpc/vec-clrr-1.c
Normal file
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/* { dg-do run } */
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/* { dg-require-effective-target powerpc_future_hw } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear right-most bytes of unsigned char. */
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vector unsigned char
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clrr (vector unsigned char arg, int n)
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{
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return vec_clrr (arg, n);
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}
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int main (int argc, char *argv [])
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{
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vector unsigned char input0 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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vector unsigned char expected0 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
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vector unsigned char expected1 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
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vector unsigned char expected2 =
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{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
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0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
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if (!vec_all_eq (clrr(input0, 5), expected0))
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abort ();
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if (!vec_all_eq (clrr(input0, 13), expected1))
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abort ();
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if (!vec_all_eq (clrr(input0, 19), expected2))
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abort ();
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}
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16
gcc/testsuite/gcc.target/powerpc/vec-clrr-2.c
Normal file
16
gcc/testsuite/gcc.target/powerpc/vec-clrr-2.c
Normal file
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@ -0,0 +1,16 @@
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/* { dg-do compile } */
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/* { dg-options "-mdejagnu-cpu=future" } */
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#include <altivec.h>
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extern void abort (void);
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/* Vector string clear right-most bytes of unsigned char. */
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vector signed char
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clrr (vector signed char arg, int n)
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{
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return vec_clrr (arg, n);
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}
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/* { dg-final { scan-assembler {\mvclrrb\M} { target be } } } */
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/* { dg-final { scan-assembler {\mvclrlb\M} { target le } } } */
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37
gcc/testsuite/gcc.target/powerpc/vec-clrr-3.c
Normal file
37
gcc/testsuite/gcc.target/powerpc/vec-clrr-3.c
Normal file
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@ -0,0 +1,37 @@
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/* { dg-do run } */
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/* { dg-require-effective-target powerpc_future_hw } */
|
||||
/* { dg-options "-mdejagnu-cpu=future" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
/* Vector string clear right-most bytes of unsigned char. */
|
||||
vector signed char
|
||||
clrr (vector signed char arg, int n)
|
||||
{
|
||||
return vec_clrr (arg, n);
|
||||
}
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
vector signed char input0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
vector signed char expected0 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x0, 0x0, 0x0,
|
||||
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
|
||||
vector signed char expected1 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
|
||||
vector signed char expected2 =
|
||||
{ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
|
||||
0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
|
||||
|
||||
if (!vec_all_eq (clrr (input0, 5), expected0))
|
||||
abort ();
|
||||
if (!vec_all_eq (clrr (input0, 13), expected1))
|
||||
abort ();
|
||||
if (!vec_all_eq (clrr (input0, 19), expected2))
|
||||
abort ();
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue