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RISC-V: Remove masking third operand of rotate instructions

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Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.

2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>

gcc/ChangeLog:
	* config/riscv/constraints.md (DsS, DsD): Restore agreement
	with shiftm1 mode attribute.
This commit is contained in:
Joern Rennecke 2023-05-19 16:18:42 -06:00 • committed by Jeff Law
parent ae2345285c
commit 259b4b7d34
1 changed files with 2 additions and 2 deletions
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4
gcc/config/riscv/constraints.md
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@ -65,13 +65,13 @@
"@internal
31 immediate"
(and (match_code "const_int")
(match_test "ival == 31")))
(match_test "(ival & 31) == 31")))
(define_constraint "DsD"
"@internal
63 immediate"
(and (match_code "const_int")
(match_test "ival == 63")))
(match_test "(ival & 63) == 63")))
(define_constraint "DbS"
"@internal"