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xtensa: Make full transition to LRA

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gcc/ChangeLog:

	* config/xtensa/constraints.md (R, T, U):
	Change define_constraint to define_memory_constraint.
	* config/xtensa/predicates.md (move_operand): Don't check that a
	constant pool operand size is a multiple of UNITS_PER_WORD.
	* config/xtensa/xtensa.cc
	(xtensa_lra_p, TARGET_LRA_P): Remove.
	(xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
	clause as it can no longer be true.
	(fixup_subreg_mem): Drop function.
	(xtensa_output_integer_literal_parts): Consider 16-bit wide
	constants.
	(xtensa_legitimate_constant_p): Add short-circuit path for
	integer load instructions. Don't check that mode size is
	at least UNITS_PER_WORD.
	* config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
	rather reload_in_progress and reload_completed.
	(doloop_end): Drop operand 2.
	(movhi_internal): Add alternative loading constant from a
	literal pool.
	(define_split for DI register_operand): Don't limit to
	!TARGET_AUTO_LITPOOLS.
	* config/xtensa/xtensa.opt (mlra): Change to no effect.
This commit is contained in:
Takayuki 'January June' Suwa 2023-05-08 22:38:51 +09:00 • committed by Max Filippov
parent 1a4c47e10e
commit 24d5e0bf19
5 changed files with 26 additions and 74 deletions
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26
gcc/config/xtensa/constraints.md
View file

@ -123,29 +123,19 @@
(and (match_code "const_int")
(match_test "! xtensa_split1_finished_p ()"))))
;; Memory constraints. Do not use define_memory_constraint here. Doing so
;; causes reload to force some constants into the constant pool, but since
;; the Xtensa constant pool can only be accessed with L32R instructions, it
;; is always better to just copy a constant into a register. Instead, use
;; regular constraints but add a check to allow pseudos during reload.
;; Memory constraints.
(define_constraint "R"
(define_memory_constraint "R"
"Memory that can be accessed with a 4-bit unsigned offset from a register."
(ior (and (match_code "mem")
(match_test "smalloffset_mem_p (op)"))
(and (match_code "reg")
(match_test "reload_in_progress
&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
(and (match_code "mem")
(match_test "smalloffset_mem_p (op)")))
(define_constraint "T"
(define_memory_constraint "T"
"Memory in a literal pool (addressable with an L32R instruction)."
(and (match_code "mem")
(match_test "!TARGET_CONST16 && constantpool_mem_p (op)")))
(define_constraint "U"
(define_memory_constraint "U"
"Memory that is not in a literal pool."
(ior (and (match_code "mem")
(match_test "! constantpool_mem_p (op)"))
(and (match_code "reg")
(match_test "reload_in_progress
&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
(and (match_code "mem")
(match_test "! constantpool_mem_p (op)")))

7
gcc/config/xtensa/predicates.md
View file

@ -143,17 +143,14 @@
(define_predicate "move_operand"
(ior
(ior (match_operand 0 "register_operand")
(and (match_operand 0 "memory_operand")
(match_test "!constantpool_mem_p (op)
|| GET_MODE_SIZE (mode) % UNITS_PER_WORD == 0")))
(match_operand 0 "memory_operand"))
(ior (and (match_code "const_int")
(match_test "(GET_MODE_CLASS (mode) == MODE_INT
&& xtensa_simm12b (INTVAL (op)))
|| ! xtensa_split1_finished_p ()"))
(and (match_code "const_int,const_double,const,symbol_ref,label_ref")
(match_test "(TARGET_CONST16 || TARGET_AUTO_LITPOOLS)
&& CONSTANT_P (op)
&& GET_MODE_SIZE (mode) % UNITS_PER_WORD == 0")))))
&& CONSTANT_P (op)")))))
;; Accept the floating point constant 1 in the appropriate mode.
(define_predicate "const_float_1_operand"

46
gcc/config/xtensa/xtensa.cc
View file

@ -115,7 +115,6 @@ static enum internal_test map_test_to_internal_test (enum rtx_code);
static rtx gen_int_relational (enum rtx_code, rtx, rtx);
static rtx gen_float_relational (enum rtx_code, rtx, rtx);
static rtx gen_conditional_move (enum rtx_code, machine_mode, rtx, rtx);
static rtx fixup_subreg_mem (rtx);
static struct machine_function * xtensa_init_machine_status (void);
static rtx xtensa_legitimize_tls_address (rtx);
static rtx xtensa_legitimize_address (rtx, rtx, machine_mode);
@ -192,7 +191,6 @@ static void xtensa_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta,
HOST_WIDE_INT vcall_offset,
tree function);
static bool xtensa_lra_p (void);
static rtx xtensa_delegitimize_address (rtx);
@ -286,9 +284,6 @@ static rtx xtensa_delegitimize_address (rtx);
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
#undef TARGET_LRA_P
#define TARGET_LRA_P xtensa_lra_p
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
@ -1333,35 +1328,10 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
operands[1] = xtensa_copy_incoming_a7 (operands[1]);
/* During reload we don't want to emit (subreg:X (mem:Y)) since that
instruction won't be recognized after reload, so we remove the
subreg and adjust mem accordingly. */
if (reload_in_progress)
{
operands[0] = fixup_subreg_mem (operands[0]);
operands[1] = fixup_subreg_mem (operands[1]);
}
return 0;
}
static rtx
fixup_subreg_mem (rtx x)
{
if (GET_CODE (x) == SUBREG
&& GET_CODE (SUBREG_REG (x)) == REG
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
rtx temp =
gen_rtx_SUBREG (GET_MODE (x),
reg_equiv_mem (REGNO (SUBREG_REG (x))),
SUBREG_BYTE (x));
x = alter_subreg (&temp, true);
}
return x;
}
/* Check if an incoming argument in a7 is expected to be used soon and
if OPND is a register or register pair that includes a7. If so,
create a new pseudo and copy a7 into that pseudo at the very
@ -2355,7 +2325,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict,
code_helper)
{
/* Allow constant pool addresses. */
if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
if (mode != BLKmode
&& ! TARGET_CONST16 && constantpool_address_p (addr)
&& ! xtensa_tls_referenced_p (addr))
return true;
@ -3280,7 +3250,7 @@ xtensa_output_integer_literal_parts (FILE *file, rtx x, int size)
fputs (", ", file);
xtensa_output_integer_literal_parts (file, second, size / 2);
}
else if (size == 4)
else if (size == 4 || size == 2)
{
output_addr_const (file, x);
}
@ -4952,6 +4922,10 @@ xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
static bool
xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
if (CONST_INT_P (x))
return TARGET_AUTO_LITPOOLS || TARGET_CONST16
|| xtensa_simm12b (INTVAL (x));
return !xtensa_tls_referenced_p (x);
}
@ -5393,12 +5367,4 @@ xtensa_delegitimize_address (rtx op)
return op;
}
/* Implement TARGET_LRA_P. */
static bool
xtensa_lra_p (void)
{
return TARGET_LRA;
}
#include "gt-xtensa.h"

17
gcc/config/xtensa/xtensa.md
View file

@ -1244,7 +1244,7 @@
(define_split
[(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "const_int_operand"))]
"!TARGET_CONST16 && !TARGET_AUTO_LITPOOLS
"!TARGET_CONST16
&& ! xtensa_split1_finished_p ()"
[(set (match_dup 0)
(match_dup 1))
@ -1328,8 +1328,8 @@
})
(define_insn "movhi_internal"
[(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
(match_operand:HI 1 "move_operand" "M,d,r,I,Y,U,r,*A,*r"))]
[(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,a,U,*a,*A")
(match_operand:HI 1 "move_operand" "M,d,r,I,Y,T,U,r,*A,*r"))]
"xtensa_valid_move (HImode, operands)"
"@
movi.n\t%0, %x1
@ -1337,13 +1337,14 @@
mov\t%0, %1
movi\t%0, %x1
movi\t%0, %1
%v1l32r\t%0, %1
%v1l16ui\t%0, %1
%v0s16i\t%1, %0
rsr\t%0, ACCLO
wsr\t%1, ACCLO"
[(set_attr "type" "move,move,move,move,move,load,store,rsr,wsr")
[(set_attr "type" "move,move,move,move,move,load,load,store,rsr,wsr")
(set_attr "mode" "HI")
(set_attr "length" "2,2,3,3,3,3,3,3,3")])
(set_attr "length" "2,2,3,3,3,3,3,3,3,3")])
;; 8-bit Integer moves
@ -1420,7 +1421,7 @@
if ((!register_operand (operands[0], SFmode)
&& !register_operand (operands[1], SFmode))
|| (FP_REG_P (xt_true_regnum (operands[0]))
&& !(reload_in_progress | reload_completed)
&& can_create_pseudo_p ()
&& (constantpool_mem_p (operands[1])
|| CONSTANT_P (operands[1]))))
operands[1] = force_reg (SFmode, operands[1]);
@ -2368,14 +2369,12 @@
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))
(unspec [(const_int 0)] UNSPEC_LSETUP_END)
(clobber (match_dup 2))])] ; match_scratch
(unspec [(const_int 0)] UNSPEC_LSETUP_END)])]
"TARGET_LOOPS && optimize"
{
/* The loop optimizer doesn't check the predicates... */
if (GET_MODE (operands[0]) != SImode)
FAIL;
operands[2] = gen_rtx_SCRATCH (SImode);
})

4
gcc/config/xtensa/xtensa.opt
View file

@ -38,8 +38,8 @@ Target RejectNegative Joined UInteger Var(xtensa_extra_l32r_costs) Init(0)
Set extra memory access cost for L32R instruction, in clock-cycle units.
mlra
Target Mask(LRA)
Use LRA instead of reload (transitional).
Target Ignore
Does nothing. Preserved for backward compatibility.
mtarget-align
Target