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aarch64: Rename bic/orn patterns to iorn/andn for vector modes

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This renames the patterns orn<mode>3 to iorn<mode>3 so it
matches the new optab that was added with r15-1890-gf379596e0ba99d.
Likewise for bic<mode>3 to andn<mode>3.

Note the operand 1 and operand 2 are swapped from the original
patterns to match the optab now.

Built and tested for aarch64-linux-gnu with no regression.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md
	(bic<mode>3<vczle><vczbe>): Rename to ...
	(andn<mode>3<vczle><vczbe>): This. Also swap operands.
	(orn<mode>3<vczle><vczbe>): Rename to ...
	(iorn<mode>3<vczle><vczbe>): This. Also swap operands.
	(vec_cmp<mode><v_int_equiv>): Update orn call to iorn
	and swap the last two arguments.

gcc/testsuite/ChangeLog:

	* g++.target/aarch64/vect_cmp-1.C: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
This commit is contained in:
Andrew Pinski 2024-07-22 11:19:11 -07:00
parent 8a5f528fba
commit 245187de49
2 changed files with 47 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

20
gcc/config/aarch64/aarch64-simd.md
View file

@ -322,21 +322,21 @@
[(set_attr "length" "4")]
)
(define_insn "orn<mode>3<vczle><vczbe>"
(define_insn "iorn<mode>3<vczle><vczbe>"
[(set (match_operand:VDQ_I 0 "register_operand" "=w")
(ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
(match_operand:VDQ_I 2 "register_operand" "w")))]
(ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w"))
(match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SIMD"
"orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
"orn\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "bic<mode>3<vczle><vczbe>"
(define_insn "andn<mode>3<vczle><vczbe>"
[(set (match_operand:VDQ_I 0 "register_operand" "=w")
(and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
(match_operand:VDQ_I 2 "register_operand" "w")))]
(and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w"))
(match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SIMD"
"bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
"bic\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
@ -4064,7 +4064,7 @@
tmp0, <V_INT_EQUIV>mode),
lowpart_subreg (<MODE>mode,
tmp1, <V_INT_EQUIV>mode)));
emit_insn (gen_orn<v_int_equiv>3 (operands[0], tmp2, operands[0]));
emit_insn (gen_iorn<v_int_equiv>3 (operands[0], operands[0], tmp2));
}
break;
@ -4111,7 +4111,7 @@
else if (code == UNEQ)
{
emit_insn (gen_aarch64_cmeq<mode> (tmp, operands[2], operands[3]));
emit_insn (gen_orn<v_int_equiv>3 (operands[0], operands[0], tmp));
emit_insn (gen_iorn<v_int_equiv>3 (operands[0], tmp, operands[0]));
}
break;

37
gcc/testsuite/g++.target/aarch64/vect_cmp-1.C Normal file
View file

@ -0,0 +1,37 @@
/* { dg-do compile } */
/* { dg-additional-options "-O2 -fdump-tree-optimized" } */
/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */
#pragma GCC target "+nosve"
#define vect8 __attribute__((vector_size(8) ))
/**
**bar1:
** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s
** bic v0.8b, v2.8b, v\1.8b
** ret
*/
extern "C"
vect8 int bar1(vect8 float a, vect8 float b, vect8 int c)
{
return (a > b) ? 0 : c;
}
/**
**bar2:
** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s
** orn v0.8b, v2.8b, v\1.8b
** ret
*/
extern "C"
vect8 int bar2(vect8 float a, vect8 float b, vect8 int c)
{
return (a > b) ? c : -1;
}
// We should produce a BIT_ANDC and BIT_IORC here.
// { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } }
// { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } }