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Delete powerpcspe

Browse source 
This deletes powerpcspe, which was deprecated for GCC 8.

This does not change the testsuite, or libgcc for rs6000 (which still
is shared code with powerpcspe, so can use some cleanup after this).


/
	* contrib/config-list.mk: Remove powerpc-eabispe and powerpc-linux_spe.

gcc/
	* config.gcc (Obsolete configurations): Delete powerpc*-*-*spe*.
	(Unsupported targets): Add powerpc*-*-*spe*.
	(powerpc*-*-*spe*): Delete.
	(powerpc-*-eabispe*): Delete.
	(powerpc-*-rtems*spe*): Delete.
	(powerpc*-*-linux*spe*): Delete.
	(powerpc*-*-linux*): Do not handle the linux*spe* targets.
	(powerpc-wrs-vxworks*spe): Delete.
	(with_cpu setting code): Delete powerpc*-*-*spe* handling.
	* config.host (target powerpc*-*-*spe*): Delete.
	* doc/invoke.texi (PowerPC SPE Options): Delete.
	(PowerPC SPE Options): Delete.
	* config/powerpcspe: Delete.

From-SVN: r266961
This commit is contained in:
Segher Boessenkool 2018-12-10 20:40:27 +01:00 • committed by Segher Boessenkool
parent a84162511d
commit 23d3e2d5a7
153 changed files with 23 additions and 112990 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
ChangeLog
View file

@ -1,3 +1,7 @@
2018-12-10 Segher Boessenkool <segher@kernel.crashing.org>
* contrib/config-list.mk: Remove powerpc-eabispe and powerpc-linux_spe.
2018-12-05 Iain Sandoe <iain@sandoe.co.uk>
* configure.ac (NCN_STRICT_CHECK_TOOLS): Check otool.

4
contrib/config-list.mk
View file

@ -73,9 +73,9 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \
pdp11-aout \
powerpc-darwin8 \
powerpc-darwin7 powerpc64-darwin powerpc-freebsd6 powerpc-netbsd \
powerpc-eabispe powerpc-eabisimaltivec powerpc-eabisim ppc-elf \
powerpc-eabisimaltivec powerpc-eabisim ppc-elf \
powerpc-eabialtivec powerpc-xilinx-eabi powerpc-eabi \
powerpc-rtems powerpc-linux_spe \
powerpc-rtems \
powerpc64-linux_altivec \
powerpc-wrs-vxworks powerpc-wrs-vxworksae powerpc-wrs-vxworksmils \
powerpc-lynxos powerpcle-elf \

16
gcc/ChangeLog
View file

@ -1,3 +1,19 @@
2018-12-10 Segher Boessenkool <segher@kernel.crashing.org>
* config.gcc (Obsolete configurations): Delete powerpc*-*-*spe*.
(Unsupported targets): Add powerpc*-*-*spe*.
(powerpc*-*-*spe*): Delete.
(powerpc-*-eabispe*): Delete.
(powerpc-*-rtems*spe*): Delete.
(powerpc*-*-linux*spe*): Delete.
(powerpc*-*-linux*): Do not handle the linux*spe* targets.
(powerpc-wrs-vxworks*spe): Delete.
(with_cpu setting code): Delete powerpc*-*-*spe* handling.
* config.host (target powerpc*-*-*spe*): Delete.
* doc/invoke.texi (PowerPC SPE Options): Delete.
(PowerPC SPE Options): Delete.
* config/powerpcspe: Delete.
2018-12-10 Uros Bizjak <ubizjak@gmail.com>
PR target/88418

65
gcc/config.gcc
View file

@ -248,7 +248,6 @@ md_file=
# Obsolete configurations.
case ${target} in
*-*-solaris2.10* \
| powerpc*-*-*spe* \
| tile*-*-* \
)
if test "x$enable_obsolete" != xyes; then
@ -279,6 +278,7 @@ case ${target} in
| mips64orion*-*-rtems* \
| pdp11-*-bsd \
| powerpc*-*-linux*paired* \
| powerpc*-*-*spe* \
| sparc-hal-solaris2* \
| thumb-*-* \
| *-*-freebsd[12] | *-*-freebsd[1234].* \
@ -488,16 +488,6 @@ nvptx-*-*)
or1k*-*-*)
cpu_type=or1k
;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
extra_options="${extra_options} g.opt fused-madd.opt powerpcspe/powerpcspe-tables.opt"
;;
powerpc*-*-*)
cpu_type=rs6000
extra_objs="rs6000-string.o rs6000-p8swap.o"
@ -2592,12 +2582,6 @@ powerpc-*-netbsd*)
tmake_file="${tmake_file} rs6000/t-netbsd"
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpc-*-eabispe*)
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h ${cpu_type}/sysv4.h ${cpu_type}/eabi.h ${cpu_type}/e500.h ${cpu_type}/eabispe.h"
extra_options="${extra_options} ${cpu_type}/sysv4.opt"
tmake_file="${cpu_type}/t-spe ${cpu_type}/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisimaltivec*)
tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/eabisim.h rs6000/eabialtivec.h"
extra_options="${extra_options} rs6000/sysv4.opt"
@ -2627,26 +2611,11 @@ powerpc-*-eabi*)
tmake_file="rs6000/t-fprules rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-rtems*spe*)
tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h powerpcspe/sysv4.h powerpcspe/eabi.h powerpcspe/e500.h powerpcspe/rtems.h rtems.h"
extra_options="${extra_options} powerpcspe/sysv4.opt"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-rtems powerpcspe/t-ppccomm"
;;
powerpc-*-rtems*)
tm_file="rs6000/biarch64.h ${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/rtems.h rtems.h"
extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-rtems rs6000/t-ppccomm"
;;
powerpc*-*-linux*spe*)
tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h powerpcspe/sysv4.h"
extra_options="${extra_options} powerpcspe/sysv4.opt"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-ppccomm"
extra_objs="$extra_objs powerpcspe-linux.o"
maybe_biarch=
tm_file="${tm_file} powerpcspe/linux.h glibc-stdint.h"
tmake_file="${tmake_file} powerpcspe/t-ppcos powerpcspe/t-linux"
tm_file="${tm_file} powerpcspe/linuxspe.h powerpcspe/e500.h"
;;
powerpc*-*-linux*)
tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h freebsd-spec.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
@ -2664,15 +2633,6 @@ powerpc*-*-linux*)
*powerpc64*) maybe_biarch=yes ;;
all) maybe_biarch=yes ;;
esac
case ${target} in
powerpc64*-*-linux*spe*)
echo "*** Configuration ${target} not supported" 1>&2
exit 1
;;
powerpc*-*-linux*spe*)
maybe_biarch=
;;
esac
case ${target}:${enable_targets}:${maybe_biarch} in
powerpc64-* | powerpc-*:*:yes | *:*powerpc64-*:yes | *:all:yes \
| powerpc64le*:*powerpcle* | powerpc64le*:*powerpc-* \
@ -2713,8 +2673,6 @@ powerpc*-*-linux*)
extra_options="${extra_options} rs6000/476.opt" ;;
powerpc*-*-linux*altivec*)
tm_file="${tm_file} rs6000/linuxaltivec.h" ;;
powerpc*-*-linux*spe*)
tm_file="${tm_file} ${cpu_type}/linuxspe.h ${cpu_type}/e500.h" ;;
esac
case ${target} in
*-linux*-musl*)
@ -2724,13 +2682,6 @@ powerpc*-*-linux*)
tm_file="rs6000/secureplt.h ${tm_file}"
fi
;;
powerpc-wrs-vxworks*spe)
tm_file="${tm_file} elfos.h freebsd-spec.h powerpcspe/sysv4.h"
tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-ppccomm powerpcspe/t-vxworks"
extra_options="${extra_options} powerpcspe/sysv4.opt"
extra_headers=ppc-asm.h
tm_file="${tm_file} vx-common.h vxworks.h powerpcspe/vxworks.h powerpcspe/e500.h"
;;
powerpc-wrs-vxworks*)
tm_file="${tm_file} elfos.h gnu-user.h freebsd-spec.h rs6000/sysv4.h"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-ppccomm rs6000/t-vxworks"
@ -3619,20 +3570,6 @@ if test x$with_cpu = x ; then
;;
esac
;;
powerpc*-*-*spe*)
# For SPE, start with 8540, then upgrade to 8548 if
# --enable-e500-double was requested explicitly or if we were
# configured for e500v2.
with_cpu=8540
if test x$enable_e500_double = xyes; then
with_cpu=8548
fi
case ${target_noncanonical} in
e500v2*)
with_cpu=8548
;;
esac
;;
sparc*-*-*)
case ${target} in
*-leon-*)

4
gcc/config.host
View file

@ -144,10 +144,6 @@ case ${host} in
rs6000-*-* \
| powerpc*-*-* )
case ${target} in
powerpc*-*-*spe*)
host_extra_gcc_objs="driver-powerpcspe.o"
host_xmake_file="${host_xmake_file} powerpcspe/x-powerpcspe"
;;
rs6000-*-* \
| powerpc*-*-* )
host_extra_gcc_objs="driver-rs6000.o"

124
gcc/config/powerpcspe/40x.md
View file

@ -1,124 +0,0 @@
;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc40x,ppc40xiu")
(define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
(define_cpu_unit "iu_40x" "ppc40xiu")
;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
;; Embedded PowerPC controller
;; In-order execution
;; Max issue two insns/cycle (includes one branch)
(define_insn_reservation "ppc403-load" 2
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x")
(define_insn_reservation "ppc403-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc405"))
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
(and (ior (eq_attr "type" "halfmul")
(and (eq_attr "type" "mul")
(eq_attr "size" "8")))
(eq_attr "cpu" "ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-idiv" 33
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x*33")
(define_insn_reservation "ppc403-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc403-cr" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc403,ppc405"))
"bpu_40x")
(define_insn_reservation "ppc405-float" 11
(and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
(eq_attr "cpu" "ppc405"))
"fpu_405*10")

138
gcc/config/powerpcspe/440.md
View file

@ -1,138 +0,0 @@
;; Scheduling description for IBM PowerPC 440 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; PPC440 Embedded PowerPC controller
;; dual issue
;; i_pipe - complex integer / compare / branch
;; j_pipe - simple integer arithmetic
;; l_pipe - load-store
;; f_pipe - floating point arithmetic
(define_automaton "ppc440_core,ppc440_apu")
(define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
(define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
(define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
(define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
(define_insn_reservation "ppc440-load" 3
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
(and (ior (eq_attr "type" "halfmul")
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-idiv" 34
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe*33")
(define_insn_reservation "ppc440-branch" 1
(and (eq_attr "type" "branch,jmpreg,isync")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
(and (ior (eq_attr "type" "cmp,cr_logical,delayed_cr,mfcr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-fpcompare" 3 ; 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
(define_insn_reservation "ppc440-fp" 5
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe")
(define_insn_reservation "ppc440-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*15")
(define_insn_reservation "ppc440-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_f_pipe*29")
(define_insn_reservation "ppc440-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")

32
gcc/config/powerpcspe/476.h
View file

@ -1,32 +0,0 @@
/* Enable IBM PowerPC 476 support.
Copyright (C) 2011-2018 Free Software Foundation, Inc.
Contributed by Peter Bergner (bergner@vnet.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#undef TARGET_LINK_STACK
#define TARGET_LINK_STACK (rs6000_link_stack)
#undef SET_TARGET_LINK_STACK
#define SET_TARGET_LINK_STACK(X) do { TARGET_LINK_STACK = (X); } while (0)
#undef TARGET_ASM_CODE_END
#define TARGET_ASM_CODE_END rs6000_code_end

143
gcc/config/powerpcspe/476.md
View file

@ -1,143 +0,0 @@
;; Scheduling description for IBM PowerPC 476 processor.
;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
;; Contributed by Peter Bergner (bergner@vnet.ibm.com).
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; PPC476 Embedded PowerPC controller
;; 3 issue (476) / 4 issue (476fp)
;;
;; i_pipe - complex integer / compare
;; lj_pipe - load-store / simple integer arithmetic
;; b_pipe - branch pipe
;; f_pipe - floating point arithmetic
(define_automaton "ppc476_core,ppc476_apu")
(define_cpu_unit "ppc476_i_pipe,ppc476_lj_pipe,ppc476_b_pipe" "ppc476_core")
(define_cpu_unit "ppc476_issue_fp,ppc476_f_pipe" "ppc476_apu")
(define_cpu_unit "ppc476_issue_0,ppc476_issue_1,ppc476_issue_2" "ppc476_core")
(define_reservation "ppc476_issue" "ppc476_issue_0|ppc476_issue_1|ppc476_issue_2")
(define_reservation "ppc476_issue2" "ppc476_issue_0+ppc476_issue_1\
|ppc476_issue_0+ppc476_issue_2\
|ppc476_issue_1+ppc476_issue_2")
(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2")
(define_insn_reservation "ppc476-load" 4
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-store" 4
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpstore" 4
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-complex-integer" 1
(and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
(and (eq_attr "type" "mul,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
(define_insn_reservation "ppc476-idiv" 11
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe*11")
(define_insn_reservation "ppc476-branch" 1
(and (eq_attr "type" "branch,jmpreg")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_b_pipe")
(define_insn_reservation "ppc476-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc476"))
"ppc476_issue2,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc476"))
"ppc476_issue3,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe,\
ppc476_i_pipe|ppc476_lj_pipe")
(define_insn_reservation "ppc476-fpcompare" 6
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc476"))
"ppc476_issue+ppc476_issue_fp,\
ppc476_f_pipe+ppc476_i_pipe")
(define_insn_reservation "ppc476-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe")
(define_insn_reservation "ppc476-sdiv" 19
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,
ppc476_f_pipe*19")
(define_insn_reservation "ppc476-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc476"))
"ppc476_issue_fp,\
ppc476_f_pipe*33")

24
gcc/config/powerpcspe/476.opt
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@ -1,24 +0,0 @@
; IBM PowerPC 476 options.
;
; Copyright (C) 2011-2018 Free Software Foundation, Inc.
; Contributed by Peter Bergner (bergner@vnet.ibm.com)
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
mpreserve-link-stack
Target Var(rs6000_link_stack) Init(-1) Save
Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses.

137
gcc/config/powerpcspe/601.md
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@ -1,137 +0,0 @@
;; Scheduling description for PowerPC 601 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc601,ppc601fp")
(define_cpu_unit "iu_ppc601" "ppc601")
(define_cpu_unit "fpu_ppc601" "ppc601fp")
(define_cpu_unit "bpu_ppc601" "ppc601")
;; PPC601 32-bit IU, FPU, BPU
(define_insn_reservation "ppc601-load" 2
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-store" 2
(and (eq_attr "type" "store")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc601"))
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
(and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,isel")
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
(define_insn_reservation "ppc601-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*5")
(define_insn_reservation "ppc601-idiv" 36
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*36")
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601,nothing,bpu_ppc601")
(define_insn_reservation "ppc601-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc601"))
"(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601")
(define_insn_reservation "ppc601-fp" 4
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601")
(define_insn_reservation "ppc601-dmul" 5
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*2")
(define_insn_reservation "ppc601-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*17")
(define_insn_reservation "ppc601-ddiv" 31
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc601"))
"fpu_ppc601*31")
(define_insn_reservation "ppc601-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-mtcr" 4
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-crlogical" 4
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc601"))
"bpu_ppc601")
(define_insn_reservation "ppc601-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc601"))
"iu_ppc601,bpu_ppc601")
(define_insn_reservation "ppc601-branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc601"))
"bpu_ppc601")

147
gcc/config/powerpcspe/603.md
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@ -1,147 +0,0 @@
;; Scheduling description for PowerPC 603 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc603,ppc603fp")
(define_cpu_unit "iu_603" "ppc603")
(define_cpu_unit "fpu_603" "ppc603fp")
(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 2 insns per cycle.
;; The PPC603e user's manual recommends that to reduce branch mispredictions,
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them; separation by more than 9 insns ensures that the CR
;; bits will be immediately available for execution.
;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; CR insns get executed in the SRU. Not modelled.
(define_insn_reservation "ppc603-load" 2
(and (eq_attr "type" "load,load_l")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc603"))
"lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-storec" 8
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "ppc603"))
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
(define_insn_reservation "ppc603-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603")
(define_insn_reservation "ppc603-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603,iu_603")
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-imul2" 2
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-idiv" 37
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc603"))
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
(define_insn_reservation "ppc603-fpcompare" 3
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc603"))
"(fpu_603+iu_603*2),bpu_603")
(define_insn_reservation "ppc603-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc603"))
"fpu_603")
(define_insn_reservation "ppc603-dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc603"))
"fpu_603*2")
; Divides are not pipelined
(define_insn_reservation "ppc603-sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc603"))
"fpu_603*18")
(define_insn_reservation "ppc603-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc603"))
"fpu_603*33")
(define_insn_reservation "ppc603-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-mfjmpr" 2
(and (eq_attr "type" "mfjmpr,isync,sync")
(eq_attr "cpu" "ppc603"))
"sru_603")
(define_insn_reservation "ppc603-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc603"))
"bpu_603")

284
gcc/config/powerpcspe/6xx.md
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@ -1,284 +0,0 @@
;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
;; and PowerPC 630 processors.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
(define_cpu_unit "fpu_6xx" "ppc6xxfp")
(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
;; MCIU used for imul/idiv and moves from/to spr
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; Max issue 4 insns/clock cycle
;; PPC604e is PPC604 with larger caches and a CRU. In the 604
;; the CR logical operations are handled in the BPU.
;; In the 604e, the CRU shares bus with BPU so only one condition
;; register or branch insn can be issued per clock. Not modelled.
;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
;; Max issue 4 insns/clock cycle
;; Out-of-order execution, in-order completion
;; No following instruction can dispatch in the same cycle as a branch
;; instruction. Not modelled. This is no problem if RCSP is not
;; enabled since the scheduler stops a schedule when it gets to a branch.
;; Four insns can be dispatched per cycle.
(define_insn_reservation "ppc604-load" 2
(and (eq_attr "type" "load")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-llsc" 3
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc604,ppc604e"))
"lsu_6xx")
(define_insn_reservation "ppc630-llsc" 4
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc620,ppc630"))
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul2" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul3" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "8")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-lmul" 7
(and (eq_attr "type" "mul")
(eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*5")
(define_insn_reservation "ppc604-idiv" 20
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc604,ppc604e"))
"mciu_6xx*19")
(define_insn_reservation "ppc620-idiv" 37
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc620"))
"mciu_6xx*36")
(define_insn_reservation "ppc630-idiv" 21
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc630"))
"mciu_6xx*20")
(define_insn_reservation "ppc620-ldiv" 37
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
; FPU PPC604{,e},PPC620
(define_insn_reservation "ppc604-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
(define_insn_reservation "ppc604-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
(define_insn_reservation "ppc604-dmul" 3
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx")
; Divides are not pipelined
(define_insn_reservation "ppc604-sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx*18")
(define_insn_reservation "ppc604-ddiv" 32
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"fpu_6xx*32")
(define_insn_reservation "ppc620-ssqrt" 31
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc620"))
"fpu_6xx*31")
(define_insn_reservation "ppc620-dsqrt" 31
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc620"))
"fpu_6xx*31")
; 2xFPU PPC630
(define_insn_reservation "ppc630-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx|fpu2_6xx")
(define_insn_reservation "ppc630-fp" 3
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx|fpu2_6xx")
(define_insn_reservation "ppc630-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*17|fpu2_6xx*17")
(define_insn_reservation "ppc630-ddiv" 21
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*21|fpu2_6xx*21")
(define_insn_reservation "ppc630-ssqrt" 18
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*18|fpu2_6xx*18")
(define_insn_reservation "ppc630-dsqrt" 25
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc630"))
"fpu1_6xx*25|fpu2_6xx*25")
(define_insn_reservation "ppc604-mfcr" 3
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-mtcr" 2
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604"))
"bpu_6xx")
(define_insn_reservation "ppc604e-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
"cru_6xx")
(define_insn_reservation "ppc604-mtjmpr" 2
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
"mciu_6xx")
(define_insn_reservation "ppc630-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc630"))
"mciu_6xx")
(define_insn_reservation "ppc604-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"bpu_6xx")
(define_insn_reservation "ppc604-isync" 0
(and (eq_attr "type" "isync")
(eq_attr "cpu" "ppc604,ppc604e"))
"bpu_6xx")
(define_insn_reservation "ppc630-isync" 6
(and (eq_attr "type" "isync")
(eq_attr "cpu" "ppc620,ppc630"))
"bpu_6xx")
(define_insn_reservation "ppc604-sync" 35
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc604,ppc604e"))
"lsu_6xx")
(define_insn_reservation "ppc630-sync" 26
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc620,ppc630"))
"lsu_6xx")

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gcc/config/powerpcspe/7450.md
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@ -1,188 +0,0 @@
;; Scheduling description for Motorola PowerPC 7450 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
(define_cpu_unit "mciu_7450" "ppc7450mciu")
(define_cpu_unit "fpu_7450" "ppc7450fp")
(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
;; IU1,IU2,IU3 can perform all integer operations
;; MCIU performs imul and idiv, cr logical, SPR moves
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; It also has 4 vector units, one for each type of vector instruction.
;; However, we can only dispatch 2 instructions per cycle.
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; In-order execution
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 3 insns per cycle.
(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
(define_insn_reservation "ppc7450-load" 3
(and (eq_attr "type" "load,vecload")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-store" 3
(and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450*3")
(define_insn_reservation "ppc7450-llsc" 3
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-sync" 35
(and (eq_attr "type" "sync")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
(define_insn_reservation "ppc7450-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-idiv" 23
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc7450-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
(define_insn_reservation "ppc7450-fp" 5
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450")
; Divides are not pipelined
(define_insn_reservation "ppc7450-sdiv" 21
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450*21")
(define_insn_reservation "ppc7450-ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,fpu_7450*35")
(define_insn_reservation "ppc7450-mfcr" 2
(and (eq_attr "type" "mfcr,mtcr")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-crlogical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
(define_insn_reservation "ppc7450-mtjmpr" 2
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc7450"))
"nothing,mciu_7450*2")
(define_insn_reservation "ppc7450-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc7450"))
"nothing,bpu_7450")
;; Altivec
(define_insn_reservation "ppc7450-vecsimple" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
(define_insn_reservation "ppc7450-veccomplex" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-veccmp" 2
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,veccmplx_7450")
(define_insn_reservation "ppc7450-vecfloat" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecflt_7450")
(define_insn_reservation "ppc7450-vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,ppc7450_vec_du,vecperm_7450")

30
gcc/config/powerpcspe/750cl.h
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@ -1,30 +0,0 @@
/* Enable 750cl paired single support.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
Contributed by Revital Eres (eres@il.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#undef TARGET_PAIRED_FLOAT
#define TARGET_PAIRED_FLOAT rs6000_paired_float
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "-m750cl"

186
gcc/config/powerpcspe/7xx.md
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@ -1,186 +0,0 @@
;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc7xx,ppc7xxfp")
(define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx")
(define_cpu_unit "fpu_7xx" "ppc7xxfp")
(define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx")
(define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx")
(define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx")
;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU
;; IU1 can perform all integer operations
;; IU2 can perform all integer operations except imul and idiv
;; LSU 2 stage pipelined
;; FPU 3 stage pipelined
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; In-order execution
;; The PPC750 user's manual recommends that to reduce branch mispredictions,
;; the insn that sets CR bits should be separated from the branch insn
;; that evaluates them. There is no advantage have more than 10 cycles
;; of separation.
;; This could be artificially achieved by exaggerating the latency of
;; compare insns but at the expense of a poorer schedule.
;; Branches go straight to the BPU. All other insns are handled
;; by a dispatch unit which can issue a max of 2 insns per cycle.
(define_reservation "ppc750_du" "du1_7xx|du2_7xx")
(define_reservation "ppc7400_vec_du" "vdu_7xx")
(define_insn_reservation "ppc750-load" 2
(and (eq_attr "type" "load,fpload,vecload,load_l")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-store" 2
(and (eq_attr "type" "store,fpstore,vecstore")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-storec" 8
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
(define_insn_reservation "ppc750-imul2" 3
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*2")
(define_insn_reservation "ppc750-imul3" 2
(and (eq_attr "type" "mul")
(eq_attr "size" "8")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-idiv" 19
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
(define_insn_reservation "ppc750-fpcompare" 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx")
(define_insn_reservation "ppc750-dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc750"))
"ppc750_du,fpu_7xx*2")
(define_insn_reservation "ppc7400-dmul" 3
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,fpu_7xx")
; Divides are not pipelined
(define_insn_reservation "ppc750-sdiv" 17
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx*17")
(define_insn_reservation "ppc750-ddiv" 31
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,fpu_7xx*31")
(define_insn_reservation "ppc750-mfcr" 2
(and (eq_attr "type" "mfcr,mtcr")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
(define_insn_reservation "ppc750-crlogical" 3
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-mtjmpr" 2
(and (eq_attr "type" "mtjmpr,isync,sync")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-mfjmpr" 3
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,sru_7xx*2")
(define_insn_reservation "ppc750-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc750,ppc7400"))
"nothing,bpu_7xx")
;; Altivec
(define_insn_reservation "ppc7400-vecsimple" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-veccomplex" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-vecfloat" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,veccmplx_7xx")
(define_insn_reservation "ppc7400-vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc7400"))
"ppc750_du,ppc7400_vec_du,vecperm_7xx")

248
gcc/config/powerpcspe/8540.md
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@ -1,248 +0,0 @@
;; Pipeline description for Motorola PowerPC 8540 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
;; We don't simulate general issue queue (GIC). If we have SU insn
;; and then SU1 insn, they cannot be issued on the same cycle
;; (although SU1 insn and then SU insn can be issued) because the SU
;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
;; multipass insn scheduling will find the situation and issue the SU1
;; insn and then the SU insn.
(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
;; We could describe completion buffers slots in combination with the
;; retirement units and the order of completion but the result
;; automaton would behave in the same way because we cannot describe
;; real latency time with taking in order completion into account.
;; Actually we could define the real latency time by querying reserved
;; automaton units but the current scheduler uses latency time before
;; issuing insns and making any reservations.
;;
;; So our description is aimed to achieve a insn schedule in which the
;; insns would not wait in the completion buffer.
(define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
;; Branch unit:
(define_cpu_unit "ppc8540_bu" "ppc8540_most")
;; SU:
(define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
;; We could describe here MU subunits for float multiply, float add
;; etc. But the result automaton would behave the same way as the
;; described one pipeline below because MU can start only one insn
;; per cycle. Actually we could simplify the automaton more not
;; describing stages 1-3, the result automata would be the same.
(define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
(define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
;; The following unit is used to describe non-pipelined division.
(define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
;; Here we simplified LSU unit description not describing the stages.
(define_cpu_unit "ppc8540_lsu" "ppc8540_most")
;; The following units are used to make automata deterministic
(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
(define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
(presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
;; Some useful abbreviations.
(define_reservation "ppc8540_decode"
"ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0")
(define_reservation "ppc8540_issue"
"ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
(define_reservation "ppc8540_retire"
"ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
(define_reservation "ppc8540_su_stage0"
"ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
(and (eq_attr "type" "integer,add,logical,insert,cmp,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppc8540_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Multiply
(define_insn_reservation "ppc8540_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Divide. We use the average latency time here. We omit reserving a
;; retire unit because of the result automata will be huge. We ignore
;; reservation of miu_stage3 here because we use the average latency
;; time.
(define_insn_reservation "ppc8540_divide" 14
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*13")
;; CR logical
(define_insn_reservation "ppc8540_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Mfcr
(define_insn_reservation "ppc8540_mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtcrf
(define_insn_reservation "ppc8540_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtjmpr
(define_insn_reservation "ppc8540_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Loads
(define_insn_reservation "ppc8540_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Stores.
(define_insn_reservation "ppc8540_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Simple FP
(define_insn_reservation "ppc8540_simple_float" 1
(and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; FP
(define_insn_reservation "ppc8540_float" 4
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; float divides. We omit reserving a retire unit and miu_stage3
;; because of the result automata will be huge.
(define_insn_reservation "ppc8540_float_vector_divide" 29
(and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*28")
;; Brinc
(define_insn_reservation "ppc8540_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Simple vector compare
(define_insn_reservation "ppc8540_simple_vector_compare" 1
(and (eq_attr "type" "veccmpsimple")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; evsplatfi evsplati
(define_insn_reservation "ppc8540_vector_perm" 1
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Vector float
(define_insn_reservation "ppc8540_float_vector" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Vector divides: Use the average. We omit reserving a retire unit
;; because of the result automata will be huge. We ignore reservation
;; of miu_stage3 here because we use the average latency time.
(define_insn_reservation "ppc8540_vector_divide" 14
(and (eq_attr "type" "vecdiv")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*13")
;; Complex vector.
(define_insn_reservation "ppc8540_complex_vector" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Vector load
(define_insn_reservation "ppc8540_vector_load" 3
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Vector store
(define_insn_reservation "ppc8540_vector_store" 3
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")

138
gcc/config/powerpcspe/a2.md
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@ -1,138 +0,0 @@
;; Scheduling description for PowerPC A2 processors.
;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppca2")
;; CPU units
;; The multiplier pipeline.
(define_cpu_unit "mult" "ppca2")
;; The auxiliary processor unit (FP/vector unit).
(define_cpu_unit "axu" "ppca2")
;; D.4.6
;; Some peculiarities for certain SPRs
(define_insn_reservation "ppca2-mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppca2"))
"nothing")
(define_insn_reservation "ppca2-mfjmpr" 5
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "ppca2"))
"nothing")
(define_insn_reservation "ppca2-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppca2"))
"nothing")
;; D.4.8
(define_insn_reservation "ppca2-imul" 1
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16,32")
(eq_attr "cpu" "ppca2"))
"nothing")
;; FIXME: latency and multiplier reservation for 64-bit multiply?
(define_insn_reservation "ppca2-lmul" 6
(and (eq_attr "type" "mul")
(eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*3")
;; D.4.9
(define_insn_reservation "ppca2-idiv" 32
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppca2"))
"mult*32")
(define_insn_reservation "ppca2-ldiv" 65
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*65")
;; D.4.13
(define_insn_reservation "ppca2-load" 5
(and (eq_attr "type" "load")
(eq_attr "cpu" "ppca2"))
"nothing")
;; D.8.1
(define_insn_reservation "ppca2-fp" 6
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.4
(define_insn_reservation "ppca2-fp-load" 6
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.5
(define_insn_reservation "ppca2-fp-store" 2
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.6
(define_insn_reservation "ppca2-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.7
;;
;; Instructions from the same thread succeeding the floating-point
;; divide cannot be executed until the floating-point divide has
;; completed. Since there is nothing else we can do, this thread will
;; just have to stall.
(define_insn_reservation "ppca2-ddiv" 72
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppca2"))
"axu")
(define_insn_reservation "ppca2-sdiv" 59
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppca2"))
"axu")
;; D.8.8
;;
;; Instructions from the same thread succeeding the floating-point
;; divide cannot be executed until the floating-point divide has
;; completed. Since there is nothing else we can do, this thread will
;; just have to stall.
(define_insn_reservation "ppca2-dsqrt" 69
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppca2"))
"axu")
(define_insn_reservation "ppca2-ssqrt" 65
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppca2"))
"axu")

51
gcc/config/powerpcspe/aix-stdint.h
View file

@ -1,51 +0,0 @@
/* Definitions for <stdint.h> types on systems using AIX.
Copyright (C) 2009-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define SIG_ATOMIC_TYPE "int"
#define INT8_TYPE "signed char"
#define INT16_TYPE "short int"
#define INT32_TYPE "int"
#define INT64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT8_TYPE "unsigned char"
#define UINT16_TYPE "short unsigned int"
#define UINT32_TYPE "unsigned int"
#define UINT64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INT_LEAST8_TYPE "signed char"
#define INT_LEAST16_TYPE "short int"
#define INT_LEAST32_TYPE "int"
#define INT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT_LEAST8_TYPE "unsigned char"
#define UINT_LEAST16_TYPE "short unsigned int"
#define UINT_LEAST32_TYPE "unsigned int"
#define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INT_FAST8_TYPE "signed char"
#define INT_FAST16_TYPE "short int"
#define INT_FAST32_TYPE "int"
#define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT_FAST8_TYPE "unsigned char"
#define UINT_FAST16_TYPE "short unsigned int"
#define UINT_FAST32_TYPE "unsigned int"
#define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INTPTR_TYPE "long int"
#define UINTPTR_TYPE "long unsigned int"

277
gcc/config/powerpcspe/aix.h
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@ -1,277 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX.
Copyright (C) 2000-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Yes! We are AIX! */
#define DEFAULT_ABI ABI_AIX
#undef TARGET_AIX
#define TARGET_AIX 1
/* Linux64.h wants to redefine TARGET_AIX based on -m64, but it can't be used
in the #if conditional in options-default.h, so provide another macro. */
#undef TARGET_AIX_OS
#define TARGET_AIX_OS 1
/* AIX always has a TOC. */
#define TARGET_NO_TOC 0
#define TARGET_TOC 1
#define FIXED_R2 1
/* AIX allows r13 to be used in 32-bit mode. */
#define FIXED_R13 0
/* 32-bit and 64-bit AIX stack boundary is 128. */
#undef STACK_BOUNDARY
#define STACK_BOUNDARY 128
/* Offset within stack frame to start allocating local variables at.
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
first local allocated. Otherwise, it is the offset to the BEGINNING
of the first local allocated.
On the RS/6000, the frame pointer is the same as the stack pointer,
except for dynamic allocations. So we start after the fixed area and
outgoing parameter area.
If the function uses dynamic stack space (CALLS_ALLOCA is set), that
space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
sizes of the fixed area and the parameter area must be a multiple of
STACK_BOUNDARY. */
#undef RS6000_STARTING_FRAME_OFFSET
#define RS6000_STARTING_FRAME_OFFSET \
(cfun->calls_alloca \
? RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, 16) \
: (RS6000_ALIGN (crtl->outgoing_args_size, 16) + RS6000_SAVE_AREA))
/* Offset from the stack pointer register to an item dynamically
allocated on the stack, e.g., by `alloca'.
The default value for this macro is `STACK_POINTER_OFFSET' plus the
length of the outgoing arguments. The default is correct for most
machines. See `function.c' for details.
This value must be a multiple of STACK_BOUNDARY (hard coded in
`emit-rtl.c'). */
#undef STACK_DYNAMIC_OFFSET
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
+ STACK_POINTER_OFFSET, 16)
#undef TARGET_IEEEQUAD
#define TARGET_IEEEQUAD 0
/* The AIX linker will discard static constructors in object files before
collect has a chance to see them, so scan the object files directly. */
#define COLLECT_EXPORT_LIST
/* On AIX, initialisers specified with -binitfini are called in breadth-first
order.
e.g. if a.out depends on lib1.so, the init function for a.out is called before
the init function for lib1.so.
To ensure global C++ constructors in linked libraries are run before global
C++ constructors from the current module, there is additional symbol scanning
logic in collect2.
The global initialiser/finaliser functions are named __GLOBAL_AIXI_{libname}
and __GLOBAL_AIXD_{libname} and are exported from each shared library.
collect2 will detect these symbols when they exist in shared libraries that
the current program is being linked against. All such initiliser functions
will be called prior to the constructors of the current program, and
finaliser functions called after destructors.
Reference counting generated by collect2 will ensure that constructors are
only invoked once in the case of multiple dependencies on a library.
-binitfini is still used in parallel to this solution.
This handles the case where a library is loaded through dlopen(), and also
handles the option -blazy.
*/
#define COLLECT_SHARED_INIT_FUNC(STREAM, FUNC) \
fprintf ((STREAM), "void %s() {\n\t%s();\n}\n", aix_shared_initname, (FUNC))
#define COLLECT_SHARED_FINI_FUNC(STREAM, FUNC) \
fprintf ((STREAM), "void %s() {\n\t%s();\n}\n", aix_shared_fininame, (FUNC))
#if HAVE_AS_REF
/* Issue assembly directives that create a reference to the given DWARF table
identifier label from the current function section. This is defined to
ensure we drag frame tables associated with needed function bodies in
a link with garbage collection activated. */
#define ASM_OUTPUT_DWARF_TABLE_REF rs6000_aix_asm_output_dwarf_table_ref
#endif
/* This is the only version of nm that collect2 can work with. */
#define REAL_NM_FILE_NAME "/usr/ucb/nm"
#define USER_LABEL_PREFIX ""
/* Don't turn -B into -L if the argument specifies a relative file name. */
#define RELATIVE_PREFIX_NOT_LINKDIR
/* Because of the above, we must have gcc search itself to find libgcc.a. */
#define LINK_LIBGCC_SPECIAL_1
/* Names to predefine in the preprocessor for this target machine. */
#define TARGET_OS_AIX_CPP_BUILTINS() \
do \
{ \
builtin_define ("_IBMR2"); \
builtin_define ("_POWER"); \
builtin_define ("__unix__"); \
builtin_define ("_AIX"); \
builtin_define ("_AIX32"); \
builtin_define ("_AIX41"); \
builtin_define ("_LONG_LONG"); \
if (TARGET_LONG_DOUBLE_128) \
builtin_define ("__LONGDOUBLE128"); \
builtin_assert ("system=unix"); \
builtin_assert ("system=aix"); \
if (TARGET_64BIT) \
{ \
builtin_define ("__PPC__"); \
builtin_define ("__PPC64__"); \
builtin_define ("__powerpc__"); \
builtin_define ("__powerpc64__"); \
builtin_assert ("cpu=powerpc64"); \
builtin_assert ("machine=powerpc64"); \
} \
else \
{ \
builtin_define ("__PPC__"); \
builtin_define ("__powerpc__"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
} \
} \
while (0)
/* Define appropriate architecture macros for preprocessor depending on
target switches. */
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
%{ansi: -D_ANSI_C_SOURCE}"
#define CC1_SPEC "%(cc1_cpu)"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC ""
/* Tell the assembler to assume that all undefined names are external.
Don't do this until the fixed IBM assembler is more generally available.
When this becomes permanently defined, the ASM_OUTPUT_EXTERNAL,
ASM_OUTPUT_EXTERNAL_LIBCALL, and RS6000_OUTPUT_BASENAME macros will no
longer be needed. Also, the extern declaration of mcount in
rs6000_xcoff_file_start will no longer be needed. */
/* #define ASM_SPEC "-u %(asm_cpu)" */
/* Default location of syscalls.exp under AIX */
#define LINK_SYSCALLS_SPEC "-bI:%R/lib/syscalls.exp"
/* Default location of libg.exp under AIX */
#define LINK_LIBG_SPEC "-bexport:%R/usr/lib/libg.exp"
/* Define the options for the binder: Start text at 512, align all segments
to 512 bytes, and warn if there is text relocation.
The -bhalt:4 option supposedly changes the level at which ld will abort,
but it also suppresses warnings about multiply defined symbols and is
used by the AIX cc command. So we use it here.
-bnodelcsect undoes a poor choice of default relating to multiply-defined
csects. See AIX documentation for more information about this.
-bM:SRE tells the linker that the output file is Shared REusable. Note
that to actually build a shared library you will also need to specify an
export list with the -Wl,-bE option. */
#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\
%{static:-bnso %(link_syscalls) } \
%{!shared:%{g*: %(link_libg) }} %{shared:-bM:SRE}"
/* Profiled library versions are used by linking with special directories. */
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled} %{!shared:%{g*:-lg}} -lc"
/* Static linking with shared libstdc++ requires libsupc++ as well. */
#define LIBSTDCXX_STATIC "supc++"
/* This now supports a natural alignment mode. */
/* AIX word-aligns FP doubles but doubleword-aligns 64-bit ints. */
#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
((TARGET_ALIGN_NATURAL == 0 \
&& TYPE_MODE (strip_array_types (TYPE)) == DFmode) \
? MIN ((COMPUTED), 32) \
: (COMPUTED))
/* AIX increases natural record alignment to doubleword if the first
field is an FP double while the FP fields remain word aligned. */
#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
((TREE_CODE (STRUCT) == RECORD_TYPE \
|| TREE_CODE (STRUCT) == UNION_TYPE \
|| TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
&& TARGET_ALIGN_NATURAL == 0 \
? rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED) \
: MAX ((COMPUTED), (SPECIFIED)))
/* The AIX ABI isn't explicit on whether aggregates smaller than a
word/doubleword should be padded upward or downward. One could
reasonably assume that they follow the normal rules for structure
layout treating the parameter area as any other block of memory,
then map the reg param area to registers, i.e., pad upward, which
is the way IBM Compilers for AIX behave.
Setting both of the following defines results in this behavior. */
#define AGGREGATE_PADDING_FIXED 1
#define AGGREGATES_PAD_UPWARD_ALWAYS 1
/* Specify padding for the last element of a block move between
registers and memory. FIRST is nonzero if this is the only
element. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE))
/* Indicate that jump tables go in the text section. */
#define JUMP_TABLES_IN_TEXT_SECTION 1
/* Define any extra SPECS that the compiler needs to generate. */
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "link_syscalls", LINK_SYSCALLS_SPEC }, \
{ "link_libg", LINK_LIBG_SPEC }
#define PROFILE_HOOK(LABEL) output_profile_hook (LABEL)
/* No version of AIX fully supports AltiVec or 64-bit instructions in
32-bit mode. */
#define OS_MISSING_POWERPC64 1
#define OS_MISSING_ALTIVEC 1
/* WINT_TYPE */
#define WINT_TYPE "int"
/* Static stack checking is supported by means of probes. */
#define STACK_CHECK_STATIC_BUILTIN 1
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING

167
gcc/config/powerpcspe/aix43.h
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@ -1,167 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX version 4.3.
Copyright (C) 1998-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{!mpowerpc64: %(asm_default)} \
%{mpowerpc64: -mppc64}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
%{ansi: -D_ANSI_C_SOURCE}\
%{maix64: -D__64BIT__}\
%{mpe: -I%R/usr/lpp/ppe.poe/include}\
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "mcpu=common" }
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-L%R/usr/lib/threads -lpthreads -lc_r %R/usr/lib/libc.a}\
%{!pthread:-lc}"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX 4.3 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
/* The IBM AIX 4.x assembler doesn't support forward references in
.set directives. We handle this by deferring the output of .set
directives to the end of the compilation unit. */
#define TARGET_DEFERRED_OUTPUT_DEFS(DECL,TARGET) true
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
#define TARGET_AIX_VERSION 43
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function

169
gcc/config/powerpcspe/aix51.h
View file

@ -1,169 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.
Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{!mpowerpc64: %(asm_default)} \
%{mpowerpc64: -mppc64}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m620} \
%{mcpu=G5: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "mcpu=common" }
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 51
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function

179
gcc/config/powerpcspe/aix52.h
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@ -1,179 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.2.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{!mpowerpc64: %(asm_default)}}} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=power5: -m620} \
%{mcpu=power5+: -m620} \
%{mcpu=power6: -m620} \
%{mcpu=power6x: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m620} \
%{mcpu=G5: -m620}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER4
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
/* AIX does not support Altivec. */
#undef TARGET_ALTIVEC
#define TARGET_ALTIVEC 0
#undef TARGET_ALTIVEC_ABI
#define TARGET_ALTIVEC_ABI 0
#undef TARGET_EXTRA_BUILTINS
#define TARGET_EXTRA_BUILTINS 0
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 52

180
gcc/config/powerpcspe/aix53.h
View file

@ -1,180 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V5.3.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970}"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER5
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER5
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 53

213
gcc/config/powerpcspe/aix61.h
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@ -1,213 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V6.1.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
TARGET_NO_FP_IN_TOC = 0; \
TARGET_NO_SUM_IN_TOC = 0; \
} \
if (rs6000_current_cmodel == CMODEL_MEDIUM) \
{ \
rs6000_current_cmodel = CMODEL_LARGE; \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970} \
%{mvsx: %{!mcpu*: -mpwr6}} \
-many"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpwr4"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
builtin_define ("_AIX61"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE -D__COMPATMATH__ \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
/* AIX 6.1 kernel and assembler have necessary support for Altivec and VSX. */
#undef OS_MISSING_ALTIVEC
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
%{!maix64:\
%{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}\
%{shared:crtcxa_s%O%s;:crtcxa%O%s} crtdbase%O%s"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* Large TOC Support */
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 61

55
gcc/config/powerpcspe/aix64.opt
View file

@ -1,55 +0,0 @@
; Options for the 64-bit flavor of AIX.
;
; Copyright (C) 2005-2018 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
maix64
Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
Compile for 64-bit pointers.
maix32
Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
Compile for 32-bit pointers.
mcmodel=
Target RejectNegative Joined Enum(rs6000_cmodel) Var(rs6000_current_cmodel)
Select code model.
Enum
Name(rs6000_cmodel) Type(enum rs6000_cmodel)
Known code models (for use with the -mcmodel= option):
EnumValue
Enum(rs6000_cmodel) String(small) Value(CMODEL_SMALL)
EnumValue
Enum(rs6000_cmodel) String(medium) Value(CMODEL_MEDIUM)
EnumValue
Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE)
mpe
Target Report RejectNegative Var(internal_nothing_1) Save
Support message passing with the Parallel Environment.
posix
Driver
pthread
Driver

230
gcc/config/powerpcspe/aix71.h
View file

@ -1,230 +0,0 @@
/* Definitions of target machine for GNU compiler,
for IBM RS/6000 POWER running AIX V7.1.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by David Edelsohn (edelsohn@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
get control in TARGET_OPTION_OVERRIDE. */
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
{ \
rs6000_long_double_type_size = 64; \
if (global_options_set.x_rs6000_long_double_type_size) \
warning (0, "soft-float and long-double-128 are incompatible"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
{ \
error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
TARGET_NO_FP_IN_TOC = 0; \
TARGET_NO_SUM_IN_TOC = 0; \
} \
if (rs6000_current_cmodel == CMODEL_MEDIUM) \
{ \
rs6000_current_cmodel = CMODEL_LARGE; \
} \
} while (0)
#undef ASM_SPEC
#define ASM_SPEC "-u %{maix64:-a64 %{!mcpu*:-mppc64}} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amongst the various targets for
handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
provide the default assembler options if the user uses -mcpu=native, so if
you make changes here, make them there also. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{!mcpu*: %{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}} \
%{mcpu=native: %(asm_cpu_native)} \
%{mcpu=power3: -m620} \
%{mcpu=power4: -mpwr4} \
%{mcpu=power5: -mpwr5} \
%{mcpu=power5+: -mpwr5x} \
%{mcpu=power6: -mpwr6} \
%{mcpu=power6x: -mpwr6} \
%{mcpu=power7: -mpwr7} \
%{mcpu=power8: -mpwr8} \
%{mcpu=power9: -mpwr9} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
%{mcpu=603e: -m603} \
%{mcpu=604: -m604} \
%{mcpu=604e: -m604} \
%{mcpu=620: -m620} \
%{mcpu=630: -m620} \
%{mcpu=970: -m970} \
%{mcpu=G5: -m970} \
%{mvsx: %{!mcpu*: -mpwr6}} \
-many"
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpwr4"
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("_AIX43"); \
builtin_define ("_AIX51"); \
builtin_define ("_AIX52"); \
builtin_define ("_AIX53"); \
builtin_define ("_AIX61"); \
builtin_define ("_AIX71"); \
TARGET_OS_AIX_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
%{ansi: -D_ANSI_C_SOURCE} \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
/* The GNU C++ standard library requires that these macros be
defined. Synchronize with libstdc++ os_defines.h. */
#undef CPLUSPLUS_CPP_SPEC
#define CPLUSPLUS_CPP_SPEC \
"-D_ALL_SOURCE -D__COMPATMATH__ \
%{maix64: -D__64BIT__} \
%{mpe: -I%R/usr/lpp/ppe.poe/include} \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER7
/* AIX 7.1 kernel and assembler have necessary support for Altivec and VSX. */
#undef OS_MISSING_ALTIVEC
/* Define this macro as a C expression for the initializer of an
array of string to tell the driver program which options are
defaults for this target and thus do not need to be handled
specially when using `MULTILIB_OPTIONS'.
Do not define this macro if `MULTILIB_OPTIONS' is not defined in
the target makefile fragment or if none of the options listed in
`MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */
#undef MULTILIB_DEFAULTS
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{p:-L%R/lib/profiled -L%R/usr/lib/profiled}\
%{!maix64:%{!shared:%{g*:-lg}}}\
%{fprofile-arcs|fprofile-generate*|coverage:-lpthreads}\
%{mpe:-L%R/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{pthread:-lpthreads} -lc"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro}\
%{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
%{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
%{mpe:-binitfini:poe_remote_main}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{maix64:%{pg:gcrt0_64%O%s;:%{p:mcrt0_64%O%s;:crt0_64%O%s}};:\
%{pthread:%{pg:gcrt0_r%O%s;:%{p:mcrt0_r%O%s;:crt0_r%O%s}};:\
%{pg:gcrt0%O%s;:%{p:mcrt0%O%s;:crt0%O%s}}}}}\
%{shared:crtcxa_s%O%s;:crtcxa%O%s} crtdbase%O%s"
/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
/* Type used for wchar_t, as a string used in a declaration. */
#undef WCHAR_TYPE
#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int")
/* Width of wchar_t in bits. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32)
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */
#undef HAS_INIT_SECTION
#define HAS_INIT_SECTION
#undef LD_INIT_SWITCH
#define LD_INIT_SWITCH "-binitfini"
#ifndef _AIX52
extern long long int atoll(const char *);
#endif
/* This target uses the aix64.opt file. */
#define TARGET_USES_AIX64_OPT 1
/* Large TOC Support */
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
/* This target defines SUPPORTS_WEAK and TARGET_ASM_NAMED_SECTION,
but does not have crtbegin/end. */
#define TARGET_AIX_VERSION 71
/* AIX 7.1 supports DWARF3 debugging, but XCOFF remains the default. */
#define DWARF2_DEBUGGING_INFO 1
#define PREFERRED_DEBUGGING_TYPE XCOFF_DEBUG
#define DEBUG_INFO_SECTION "0x10000"
#define DEBUG_LINE_SECTION "0x20000"
#define DEBUG_PUBNAMES_SECTION "0x30000"
#define DEBUG_PUBTYPES_SECTION "0x40000"
#define DEBUG_ARANGES_SECTION "0x50000"
#define DEBUG_ABBREV_SECTION "0x60000"
#define DEBUG_STR_SECTION "0x70000"
#define DEBUG_RANGES_SECTION "0x80000"
#define DEBUG_LOC_SECTION "0x90000"
#define DEBUG_FRAME_SECTION "0xA0000"
#define DEBUG_MACINFO_SECTION "0xB0000"
#define DEBUG_MACRO_SECTION "0xB0000"

648
gcc/config/powerpcspe/altivec.h
View file

@ -1,648 +0,0 @@
/* PowerPC AltiVec include file.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
Rewritten by Paolo Bonzini (bonzini@gnu.org).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Implemented to conform to the specification included in the AltiVec
Technology Programming Interface Manual (ALTIVECPIM/D 6/1999 Rev 0). */
#ifndef _ALTIVEC_H
#define _ALTIVEC_H 1
#if !defined(__VEC__) || !defined(__ALTIVEC__)
#error Use the "-maltivec" flag to enable PowerPC AltiVec support
#endif
/* If __APPLE_ALTIVEC__ is defined, the compiler supports 'vector',
'pixel' and 'bool' as context-sensitive AltiVec keywords (in
non-AltiVec contexts, they revert to their original meanings,
if any), so we do not need to define them as macros. */
#if !defined(__APPLE_ALTIVEC__)
/* You are allowed to undef these for C++ compatibility. */
#define vector __vector
#define pixel __pixel
#define bool __bool
#endif
/* Condition register codes for AltiVec predicates. */
#define __CR6_EQ 0
#define __CR6_EQ_REV 1
#define __CR6_LT 2
#define __CR6_LT_REV 3
/* Synonyms. */
#define vec_vaddcuw vec_addc
#define vec_vand vec_and
#define vec_vandc vec_andc
#define vec_vrfip vec_ceil
#define vec_vcmpbfp vec_cmpb
#define vec_vcmpgefp vec_cmpge
#define vec_vctsxs vec_cts
#define vec_vctuxs vec_ctu
#define vec_vexptefp vec_expte
#define vec_vrfim vec_floor
#define vec_lvx vec_ld
#define vec_lvxl vec_ldl
#define vec_vlogefp vec_loge
#define vec_vmaddfp vec_madd
#define vec_vmhaddshs vec_madds
#define vec_vmladduhm vec_mladd
#define vec_vmhraddshs vec_mradds
#define vec_vnmsubfp vec_nmsub
#define vec_vnor vec_nor
#define vec_vor vec_or
#define vec_vpkpx vec_packpx
#define vec_vperm vec_perm
#define vec_vrefp vec_re
#define vec_vrfin vec_round
#define vec_vrsqrtefp vec_rsqrte
#define vec_vsel vec_sel
#define vec_vsldoi vec_sld
#define vec_vsl vec_sll
#define vec_vslo vec_slo
#define vec_vspltisb vec_splat_s8
#define vec_vspltish vec_splat_s16
#define vec_vspltisw vec_splat_s32
#define vec_vsr vec_srl
#define vec_vsro vec_sro
#define vec_stvx vec_st
#define vec_stvxl vec_stl
#define vec_vsubcuw vec_subc
#define vec_vsum2sws vec_sum2s
#define vec_vsumsws vec_sums
#define vec_vrfiz vec_trunc
#define vec_vxor vec_xor
/* Functions that are resolved by the backend to one of the
typed builtins. */
#define vec_vaddfp __builtin_vec_vaddfp
#define vec_addc __builtin_vec_addc
#define vec_adde __builtin_vec_adde
#define vec_addec __builtin_vec_addec
#define vec_vaddsws __builtin_vec_vaddsws
#define vec_vaddshs __builtin_vec_vaddshs
#define vec_vaddsbs __builtin_vec_vaddsbs
#define vec_vavgsw __builtin_vec_vavgsw
#define vec_vavguw __builtin_vec_vavguw
#define vec_vavgsh __builtin_vec_vavgsh
#define vec_vavguh __builtin_vec_vavguh
#define vec_vavgsb __builtin_vec_vavgsb
#define vec_vavgub __builtin_vec_vavgub
#define vec_ceil __builtin_vec_ceil
#define vec_cmpb __builtin_vec_cmpb
#define vec_vcmpeqfp __builtin_vec_vcmpeqfp
#define vec_cmpge __builtin_vec_cmpge
#define vec_vcmpgtfp __builtin_vec_vcmpgtfp
#define vec_vcmpgtsw __builtin_vec_vcmpgtsw
#define vec_vcmpgtuw __builtin_vec_vcmpgtuw
#define vec_vcmpgtsh __builtin_vec_vcmpgtsh
#define vec_vcmpgtuh __builtin_vec_vcmpgtuh
#define vec_vcmpgtsb __builtin_vec_vcmpgtsb
#define vec_vcmpgtub __builtin_vec_vcmpgtub
#define vec_vcfsx __builtin_vec_vcfsx
#define vec_vcfux __builtin_vec_vcfux
#define vec_cts __builtin_vec_cts
#define vec_ctu __builtin_vec_ctu
#define vec_cpsgn __builtin_vec_copysign
#define vec_double __builtin_vec_double
#define vec_expte __builtin_vec_expte
#define vec_floor __builtin_vec_floor
#define vec_loge __builtin_vec_loge
#define vec_madd __builtin_vec_madd
#define vec_madds __builtin_vec_madds
#define vec_mtvscr __builtin_vec_mtvscr
#define vec_vmaxfp __builtin_vec_vmaxfp
#define vec_vmaxsw __builtin_vec_vmaxsw
#define vec_vmaxsh __builtin_vec_vmaxsh
#define vec_vmaxsb __builtin_vec_vmaxsb
#define vec_vminfp __builtin_vec_vminfp
#define vec_vminsw __builtin_vec_vminsw
#define vec_vminsh __builtin_vec_vminsh
#define vec_vminsb __builtin_vec_vminsb
#define vec_mradds __builtin_vec_mradds
#define vec_vmsumshm __builtin_vec_vmsumshm
#define vec_vmsumuhm __builtin_vec_vmsumuhm
#define vec_vmsummbm __builtin_vec_vmsummbm
#define vec_vmsumubm __builtin_vec_vmsumubm
#define vec_vmsumshs __builtin_vec_vmsumshs
#define vec_vmsumuhs __builtin_vec_vmsumuhs
#define vec_vmulesb __builtin_vec_vmulesb
#define vec_vmulesh __builtin_vec_vmulesh
#define vec_vmuleuh __builtin_vec_vmuleuh
#define vec_vmuleub __builtin_vec_vmuleub
#define vec_vmulosh __builtin_vec_vmulosh
#define vec_vmulouh __builtin_vec_vmulouh
#define vec_vmulosb __builtin_vec_vmulosb
#define vec_vmuloub __builtin_vec_vmuloub
#define vec_nmsub __builtin_vec_nmsub
#define vec_packpx __builtin_vec_packpx
#define vec_vpkswss __builtin_vec_vpkswss
#define vec_vpkuwus __builtin_vec_vpkuwus
#define vec_vpkshss __builtin_vec_vpkshss
#define vec_vpkuhus __builtin_vec_vpkuhus
#define vec_vpkswus __builtin_vec_vpkswus
#define vec_vpkshus __builtin_vec_vpkshus
#define vec_re __builtin_vec_re
#define vec_round __builtin_vec_round
#define vec_recipdiv __builtin_vec_recipdiv
#define vec_rlmi __builtin_vec_rlmi
#define vec_vrlnm __builtin_vec_rlnm
#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((b)<<8)|(c)))
#define vec_rsqrt __builtin_vec_rsqrt
#define vec_rsqrte __builtin_vec_rsqrte
#define vec_vsubfp __builtin_vec_vsubfp
#define vec_subc __builtin_vec_subc
#define vec_vsubsws __builtin_vec_vsubsws
#define vec_vsubshs __builtin_vec_vsubshs
#define vec_vsubsbs __builtin_vec_vsubsbs
#define vec_sum4s __builtin_vec_sum4s
#define vec_vsum4shs __builtin_vec_vsum4shs
#define vec_vsum4sbs __builtin_vec_vsum4sbs
#define vec_vsum4ubs __builtin_vec_vsum4ubs
#define vec_sum2s __builtin_vec_sum2s
#define vec_sums __builtin_vec_sums
#define vec_trunc __builtin_vec_trunc
#define vec_vupkhpx __builtin_vec_vupkhpx
#define vec_vupkhsh __builtin_vec_vupkhsh
#define vec_vupkhsb __builtin_vec_vupkhsb
#define vec_vupklpx __builtin_vec_vupklpx
#define vec_vupklsh __builtin_vec_vupklsh
#define vec_vupklsb __builtin_vec_vupklsb
#define vec_abs __builtin_vec_abs
#define vec_nabs __builtin_vec_nabs
#define vec_abss __builtin_vec_abss
#define vec_add __builtin_vec_add
#define vec_adds __builtin_vec_adds
#define vec_and __builtin_vec_and
#define vec_andc __builtin_vec_andc
#define vec_avg __builtin_vec_avg
#define vec_cmpeq __builtin_vec_cmpeq
#define vec_cmpne __builtin_vec_cmpne
#define vec_cmpgt __builtin_vec_cmpgt
#define vec_ctf __builtin_vec_ctf
#define vec_dst __builtin_vec_dst
#define vec_dstst __builtin_vec_dstst
#define vec_dststt __builtin_vec_dststt
#define vec_dstt __builtin_vec_dstt
#define vec_ld __builtin_vec_ld
#define vec_lde __builtin_vec_lde
#define vec_ldl __builtin_vec_ldl
#define vec_lvebx __builtin_vec_lvebx
#define vec_lvehx __builtin_vec_lvehx
#define vec_lvewx __builtin_vec_lvewx
#define vec_neg __builtin_vec_neg
#define vec_pmsum_be __builtin_vec_vpmsum
#define vec_shasigma_be __builtin_crypto_vshasigma
/* Cell only intrinsics. */
#ifdef __PPU__
#define vec_lvlx __builtin_vec_lvlx
#define vec_lvlxl __builtin_vec_lvlxl
#define vec_lvrx __builtin_vec_lvrx
#define vec_lvrxl __builtin_vec_lvrxl
#endif
#define vec_lvsl __builtin_vec_lvsl
#define vec_lvsr __builtin_vec_lvsr
#define vec_max __builtin_vec_max
#define vec_mergee __builtin_vec_vmrgew
#define vec_mergeh __builtin_vec_mergeh
#define vec_mergel __builtin_vec_mergel
#define vec_mergeo __builtin_vec_vmrgow
#define vec_min __builtin_vec_min
#define vec_mladd __builtin_vec_mladd
#define vec_msum __builtin_vec_msum
#define vec_msums __builtin_vec_msums
#define vec_mul __builtin_vec_mul
#define vec_mule __builtin_vec_mule
#define vec_mulo __builtin_vec_mulo
#define vec_nor __builtin_vec_nor
#define vec_or __builtin_vec_or
#define vec_pack __builtin_vec_pack
#define vec_packs __builtin_vec_packs
#define vec_packsu __builtin_vec_packsu
#define vec_perm __builtin_vec_perm
#define vec_rl __builtin_vec_rl
#define vec_sel __builtin_vec_sel
#define vec_sl __builtin_vec_sl
#define vec_sld __builtin_vec_sld
#define vec_sldw __builtin_vsx_xxsldwi
#define vec_sll __builtin_vec_sll
#define vec_slo __builtin_vec_slo
#define vec_splat __builtin_vec_splat
#define vec_sr __builtin_vec_sr
#define vec_sra __builtin_vec_sra
#define vec_srl __builtin_vec_srl
#define vec_sro __builtin_vec_sro
#define vec_st __builtin_vec_st
#define vec_ste __builtin_vec_ste
#define vec_stl __builtin_vec_stl
#define vec_stvebx __builtin_vec_stvebx
#define vec_stvehx __builtin_vec_stvehx
#define vec_stvewx __builtin_vec_stvewx
/* Cell only intrinsics. */
#ifdef __PPU__
#define vec_stvlx __builtin_vec_stvlx
#define vec_stvlxl __builtin_vec_stvlxl
#define vec_stvrx __builtin_vec_stvrx
#define vec_stvrxl __builtin_vec_stvrxl
#endif
#define vec_sub __builtin_vec_sub
#define vec_subs __builtin_vec_subs
#define vec_sum __builtin_vec_sum
#define vec_unpackh __builtin_vec_unpackh
#define vec_unpackl __builtin_vec_unpackl
#define vec_vaddubm __builtin_vec_vaddubm
#define vec_vaddubs __builtin_vec_vaddubs
#define vec_vadduhm __builtin_vec_vadduhm
#define vec_vadduhs __builtin_vec_vadduhs
#define vec_vadduwm __builtin_vec_vadduwm
#define vec_vadduws __builtin_vec_vadduws
#define vec_vcmpequb __builtin_vec_vcmpequb
#define vec_vcmpequh __builtin_vec_vcmpequh
#define vec_vcmpequw __builtin_vec_vcmpequw
#define vec_vmaxub __builtin_vec_vmaxub
#define vec_vmaxuh __builtin_vec_vmaxuh
#define vec_vmaxuw __builtin_vec_vmaxuw
#define vec_vminub __builtin_vec_vminub
#define vec_vminuh __builtin_vec_vminuh
#define vec_vminuw __builtin_vec_vminuw
#define vec_vmrghb __builtin_vec_vmrghb
#define vec_vmrghh __builtin_vec_vmrghh
#define vec_vmrghw __builtin_vec_vmrghw
#define vec_vmrglb __builtin_vec_vmrglb
#define vec_vmrglh __builtin_vec_vmrglh
#define vec_vmrglw __builtin_vec_vmrglw
#define vec_vpkuhum __builtin_vec_vpkuhum
#define vec_vpkuwum __builtin_vec_vpkuwum
#define vec_vrlb __builtin_vec_vrlb
#define vec_vrlh __builtin_vec_vrlh
#define vec_vrlw __builtin_vec_vrlw
#define vec_vslb __builtin_vec_vslb
#define vec_vslh __builtin_vec_vslh
#define vec_vslw __builtin_vec_vslw
#define vec_vspltb __builtin_vec_vspltb
#define vec_vsplth __builtin_vec_vsplth
#define vec_vspltw __builtin_vec_vspltw
#define vec_vsrab __builtin_vec_vsrab
#define vec_vsrah __builtin_vec_vsrah
#define vec_vsraw __builtin_vec_vsraw
#define vec_vsrb __builtin_vec_vsrb
#define vec_vsrh __builtin_vec_vsrh
#define vec_vsrw __builtin_vec_vsrw
#define vec_vsububs __builtin_vec_vsububs
#define vec_vsububm __builtin_vec_vsububm
#define vec_vsubuhm __builtin_vec_vsubuhm
#define vec_vsubuhs __builtin_vec_vsubuhs
#define vec_vsubuwm __builtin_vec_vsubuwm
#define vec_vsubuws __builtin_vec_vsubuws
#define vec_xor __builtin_vec_xor
#define vec_extract __builtin_vec_extract
#define vec_insert __builtin_vec_insert
#define vec_splats __builtin_vec_splats
#define vec_promote __builtin_vec_promote
#ifdef __VSX__
/* VSX additions */
#define vec_div __builtin_vec_div
#define vec_mul __builtin_vec_mul
#define vec_msub __builtin_vec_msub
#define vec_nmadd __builtin_vec_nmadd
#define vec_nearbyint __builtin_vec_nearbyint
#define vec_rint __builtin_vec_rint
#define vec_sqrt __builtin_vec_sqrt
#define vec_vsx_ld __builtin_vec_vsx_ld
#define vec_vsx_st __builtin_vec_vsx_st
#define vec_xl __builtin_vec_vsx_ld
#define vec_xst __builtin_vec_vsx_st
/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
instead of __builtin_vec_<xxx> */
#define vec_xxsldwi __builtin_vsx_xxsldwi
#define vec_xxpermdi __builtin_vsx_xxpermdi
#endif
#ifdef _ARCH_PWR8
/* Vector additions added in ISA 2.07. */
#define vec_eqv __builtin_vec_eqv
#define vec_nand __builtin_vec_nand
#define vec_orc __builtin_vec_orc
#define vec_vaddcuq __builtin_vec_vaddcuq
#define vec_vaddudm __builtin_vec_vaddudm
#define vec_vadduqm __builtin_vec_vadduqm
#define vec_vbpermq __builtin_vec_vbpermq
#define vec_bperm __builtin_vec_vbperm_api
#define vec_vclz __builtin_vec_vclz
#define vec_cntlz __builtin_vec_vclz
#define vec_vclzb __builtin_vec_vclzb
#define vec_vclzd __builtin_vec_vclzd
#define vec_vclzh __builtin_vec_vclzh
#define vec_vclzw __builtin_vec_vclzw
#define vec_vaddecuq __builtin_vec_vaddecuq
#define vec_vaddeuqm __builtin_vec_vaddeuqm
#define vec_vsubecuq __builtin_vec_vsubecuq
#define vec_vsubeuqm __builtin_vec_vsubeuqm
#define vec_vgbbd __builtin_vec_vgbbd
#define vec_gb __builtin_vec_vgbbd
#define vec_vmaxsd __builtin_vec_vmaxsd
#define vec_vmaxud __builtin_vec_vmaxud
#define vec_vminsd __builtin_vec_vminsd
#define vec_vminud __builtin_vec_vminud
#define vec_vmrgew __builtin_vec_vmrgew
#define vec_vmrgow __builtin_vec_vmrgow
#define vec_vpksdss __builtin_vec_vpksdss
#define vec_vpksdus __builtin_vec_vpksdus
#define vec_vpkudum __builtin_vec_vpkudum
#define vec_vpkudus __builtin_vec_vpkudus
#define vec_vpopcnt __builtin_vec_vpopcnt
#define vec_vpopcntb __builtin_vec_vpopcntb
#define vec_vpopcntd __builtin_vec_vpopcntd
#define vec_vpopcnth __builtin_vec_vpopcnth
#define vec_vpopcntw __builtin_vec_vpopcntw
#define vec_popcnt __builtin_vec_vpopcntu
#define vec_popcntb __builtin_vec_vpopcntub
#define vec_popcnth __builtin_vec_vpopcntuh
#define vec_popcntw __builtin_vec_vpopcntuw
#define vec_popcntd __builtin_vec_vpopcntud
#define vec_vrld __builtin_vec_vrld
#define vec_vsld __builtin_vec_vsld
#define vec_vsrad __builtin_vec_vsrad
#define vec_vsrd __builtin_vec_vsrd
#define vec_vsubcuq __builtin_vec_vsubcuq
#define vec_vsubudm __builtin_vec_vsubudm
#define vec_vsubuqm __builtin_vec_vsubuqm
#define vec_vupkhsw __builtin_vec_vupkhsw
#define vec_vupklsw __builtin_vec_vupklsw
#endif
#ifdef __POWER9_VECTOR__
/* Vector additions added in ISA 3.0. */
#define vec_vctz __builtin_vec_vctz
#define vec_cnttz __builtin_vec_vctz
#define vec_vctzb __builtin_vec_vctzb
#define vec_vctzd __builtin_vec_vctzd
#define vec_vctzh __builtin_vec_vctzh
#define vec_vctzw __builtin_vec_vctzw
#define vec_vextract4b __builtin_vec_vextract4b
#define vec_vinsert4b __builtin_vec_vinsert4b
#define vec_vprtyb __builtin_vec_vprtyb
#define vec_vprtybd __builtin_vec_vprtybd
#define vec_vprtybw __builtin_vec_vprtybw
#ifdef _ARCH_PPC64
#define vec_vprtybq __builtin_vec_vprtybq
#endif
#define vec_absd __builtin_vec_vadu
#define vec_absdb __builtin_vec_vadub
#define vec_absdh __builtin_vec_vaduh
#define vec_absdw __builtin_vec_vaduw
#define vec_slv __builtin_vec_vslv
#define vec_srv __builtin_vec_vsrv
#define vec_extract_exp __builtin_vec_extract_exp
#define vec_extract_sig __builtin_vec_extract_sig
#define vec_insert_exp __builtin_vec_insert_exp
#define vec_test_data_class __builtin_vec_test_data_class
#define scalar_extract_exp __builtin_vec_scalar_extract_exp
#define scalar_extract_sig __builtin_vec_scalar_extract_sig
#define scalar_insert_exp __builtin_vec_scalar_insert_exp
#define scalar_test_data_class __builtin_vec_scalar_test_data_class
#define scalar_test_neg __builtin_vec_scalar_test_neg
#define scalar_cmp_exp_gt __builtin_vec_scalar_cmp_exp_gt
#define scalar_cmp_exp_lt __builtin_vec_scalar_cmp_exp_lt
#define scalar_cmp_exp_eq __builtin_vec_scalar_cmp_exp_eq
#define scalar_cmp_exp_unordered __builtin_vec_scalar_cmp_exp_unordered
#ifdef _ARCH_PPC64
#define vec_xl_len __builtin_vec_lxvl
#define vec_xst_len __builtin_vec_stxvl
#endif
#define vec_cmpnez __builtin_vec_vcmpnez
#define vec_cntlz_lsbb __builtin_vec_vclzlsbb
#define vec_cnttz_lsbb __builtin_vec_vctzlsbb
#define vec_xlx __builtin_vec_vextulx
#define vec_xrx __builtin_vec_vexturx
#define vec_revb __builtin_vec_revb
#endif
/* Predicates.
For C++, we use templates in order to allow non-parenthesized arguments.
For C, instead, we use macros since non-parenthesized arguments were
not allowed even in older GCC implementation of AltiVec.
In the future, we may add more magic to the back-end, so that no
one- or two-argument macros are used. */
#ifdef __cplusplus__
#define __altivec_unary_pred(NAME, CALL) \
template <class T> int NAME (T a1) { return CALL; }
#define __altivec_scalar_pred(NAME, CALL) \
template <class T, class U> int NAME (T a1, U a2) { return CALL; }
/* Given the vec_step of a type, return the corresponding bool type. */
template <int STEP> class __altivec_bool_ret { };
template <> class __altivec_bool_ret <4> {
typedef __vector __bool int __ret;
};
template <> class __altivec_bool_ret <8> {
typedef __vector __bool short __ret;
};
template <> class __altivec_bool_ret <16> {
typedef __vector __bool char __ret;
};
/* Be very liberal in the pairs we accept. Mistakes such as passing
a `vector char' and `vector short' will be caught by the middle-end,
while any attempt to detect them here would produce hard to understand
error messages involving the implementation details of AltiVec. */
#define __altivec_binary_pred(NAME, CALL) \
template <class T, class U> \
typename __altivec_bool_ret <vec_step (T)>::__ret \
NAME (T a1, U a2) \
{ \
return CALL; \
}
__altivec_binary_pred(vec_cmplt,
__builtin_vec_cmpgt (a2, a1))
__altivec_binary_pred(vec_cmple,
__builtin_vec_cmpge (a2, a1))
__altivec_scalar_pred(vec_all_in,
__builtin_altivec_vcmpbfp_p (__CR6_EQ, a1, a2))
__altivec_scalar_pred(vec_any_out,
__builtin_altivec_vcmpbfp_p (__CR6_EQ_REV, a1, a2))
__altivec_unary_pred(vec_all_nan,
__builtin_altivec_vcmpeq_p (__CR6_EQ, a1, a1))
__altivec_unary_pred(vec_any_nan,
__builtin_altivec_vcmpeq_p (__CR6_LT_REV, a1, a1))
__altivec_unary_pred(vec_all_numeric,
__builtin_altivec_vcmpeq_p (__CR6_LT, a1, a1))
__altivec_unary_pred(vec_any_numeric,
__builtin_altivec_vcmpeq_p (__CR6_EQ_REV, a1, a1))
__altivec_scalar_pred(vec_all_eq,
__builtin_vec_vcmpeq_p (__CR6_LT, a1, a2))
#ifndef __POWER9_VECTOR__
__altivec_scalar_pred(vec_all_ne,
__builtin_vec_vcmpeq_p (__CR6_EQ, a1, a2))
__altivec_scalar_pred(vec_any_eq,
__builtin_vec_vcmpeq_p (__CR6_EQ_REV, a1, a2))
#else
__altivec_scalar_pred(vec_all_nez,
__builtin_vec_vcmpnez_p (__CR6_LT, a1, a2))
__altivec_scalar_pred(vec_any_eqz,
__builtin_vec_vcmpnez_p (__CR6_LT_REV, a1, a2))
__altivec_scalar_pred(vec_all_ne,
__builtin_vec_vcmpne_p (a1, a2))
__altivec_scalar_pred(vec_any_eq,
__builtin_vec_vcmpae_p (a1, a2))
#endif
__altivec_scalar_pred(vec_any_ne,
__builtin_vec_vcmpeq_p (__CR6_LT_REV, a1, a2))
__altivec_scalar_pred(vec_all_gt,
__builtin_vec_vcmpgt_p (__CR6_LT, a1, a2))
__altivec_scalar_pred(vec_all_lt,
__builtin_vec_vcmpgt_p (__CR6_LT, a2, a1))
__altivec_scalar_pred(vec_any_gt,
__builtin_vec_vcmpgt_p (__CR6_EQ_REV, a1, a2))
__altivec_scalar_pred(vec_any_lt,
__builtin_vec_vcmpgt_p (__CR6_EQ_REV, a2, a1))
__altivec_scalar_pred(vec_all_ngt,
__builtin_altivec_vcmpgt_p (__CR6_EQ, a1, a2))
__altivec_scalar_pred(vec_all_nlt,
__builtin_altivec_vcmpgt_p (__CR6_EQ, a2, a1))
__altivec_scalar_pred(vec_any_ngt,
__builtin_altivec_vcmpgt_p (__CR6_LT_REV, a1, a2))
__altivec_scalar_pred(vec_any_nlt,
__builtin_altivec_vcmpgt_p (__CR6_LT_REV, a2, a1))
/* __builtin_vec_vcmpge_p is vcmpgefp for floating-point vector types,
while for integer types it is converted to __builtin_vec_vcmpgt_p,
with inverted args and condition code. */
__altivec_scalar_pred(vec_all_le,
__builtin_vec_vcmpge_p (__CR6_LT, a2, a1))
__altivec_scalar_pred(vec_all_ge,
__builtin_vec_vcmpge_p (__CR6_LT, a1, a2))
__altivec_scalar_pred(vec_any_le,
__builtin_vec_vcmpge_p (__CR6_EQ_REV, a2, a1))
__altivec_scalar_pred(vec_any_ge,
__builtin_vec_vcmpge_p (__CR6_EQ_REV, a1, a2))
__altivec_scalar_pred(vec_all_nge,
__builtin_altivec_vcmpge_p (__CR6_EQ, a1, a2))
__altivec_scalar_pred(vec_all_nle,
__builtin_altivec_vcmpge_p (__CR6_EQ, a2, a1))
__altivec_scalar_pred(vec_any_nge,
__builtin_altivec_vcmpge_p (__CR6_LT_REV, a1, a2))
__altivec_scalar_pred(vec_any_nle,
__builtin_altivec_vcmpge_p (__CR6_LT_REV, a2, a1))
#undef __altivec_scalar_pred
#undef __altivec_unary_pred
#undef __altivec_binary_pred
#else
#define vec_cmplt(a1, a2) __builtin_vec_cmpgt ((a2), (a1))
#define vec_cmple(a1, a2) __builtin_vec_cmpge ((a2), (a1))
#define vec_all_in(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ, (a1), (a2))
#define vec_any_out(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ_REV, (a1), (a2))
#define vec_all_nan(a1) __builtin_vec_vcmpeq_p (__CR6_EQ, (a1), (a1))
#define vec_any_nan(a1) __builtin_vec_vcmpeq_p (__CR6_LT_REV, (a1), (a1))
#define vec_all_numeric(a1) __builtin_vec_vcmpeq_p (__CR6_LT, (a1), (a1))
#define vec_any_numeric(a1) __builtin_vec_vcmpeq_p (__CR6_EQ_REV, (a1), (a1))
#define vec_all_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_LT, (a1), (a2))
#ifdef __POWER9_VECTOR__
#define vec_all_nez(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT, (a1), (a2))
#define vec_any_eqz(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT_REV, (a1), (a2))
#define vec_all_ne(a1, a2) __builtin_vec_vcmpne_p ((a1), (a2))
#define vec_any_eq(a1, a2) __builtin_vec_vcmpae_p ((a1), (a2))
#else
#define vec_all_ne(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ, (a1), (a2))
#define vec_any_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ_REV, (a1), (a2))
#endif
#define vec_any_ne(a1, a2) __builtin_vec_vcmpeq_p (__CR6_LT_REV, (a1), (a2))
#define vec_all_gt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_LT, (a1), (a2))
#define vec_all_lt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_LT, (a2), (a1))
#define vec_any_gt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_EQ_REV, (a1), (a2))
#define vec_any_lt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_EQ_REV, (a2), (a1))
#define vec_all_ngt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_EQ, (a1), (a2))
#define vec_all_nlt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_EQ, (a2), (a1))
#define vec_any_ngt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_LT_REV, (a1), (a2))
#define vec_any_nlt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_LT_REV, (a2), (a1))
/* __builtin_vec_vcmpge_p is vcmpgefp for floating-point vector types,
while for integer types it is converted to __builtin_vec_vcmpgt_p,
with inverted args and condition code. */
#define vec_all_le(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT, (a2), (a1))
#define vec_all_ge(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT, (a1), (a2))
#define vec_any_le(a1, a2) __builtin_vec_vcmpge_p (__CR6_EQ_REV, (a2), (a1))
#define vec_any_ge(a1, a2) __builtin_vec_vcmpge_p (__CR6_EQ_REV, (a1), (a2))
#define vec_all_nge(a1, a2) __builtin_vec_vcmpge_p (__CR6_EQ, (a1), (a2))
#define vec_all_nle(a1, a2) __builtin_vec_vcmpge_p (__CR6_EQ, (a2), (a1))
#define vec_any_nge(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT_REV, (a1), (a2))
#define vec_any_nle(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT_REV, (a2), (a1))
#endif
/* These do not accept vectors, so they do not have a __builtin_vec_*
counterpart. */
#define vec_dss(x) __builtin_altivec_dss((x))
#define vec_dssall() __builtin_altivec_dssall ()
#define vec_mfvscr() ((__vector unsigned short) __builtin_altivec_mfvscr ())
#define vec_splat_s8(x) __builtin_altivec_vspltisb ((x))
#define vec_splat_s16(x) __builtin_altivec_vspltish ((x))
#define vec_splat_s32(x) __builtin_altivec_vspltisw ((x))
#define vec_splat_u8(x) ((__vector unsigned char) vec_splat_s8 ((x)))
#define vec_splat_u16(x) ((__vector unsigned short) vec_splat_s16 ((x)))
#define vec_splat_u32(x) ((__vector unsigned int) vec_splat_s32 ((x)))
/* This also accepts a type for its parameter, so it is not enough
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
#endif /* _ALTIVEC_H */

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gcc/config/powerpcspe/altivec.md
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26
gcc/config/powerpcspe/biarch64.h
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/* Definitions of target machine for GNU compiler, for 32/64 bit powerpc.
Copyright (C) 2003-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specify this in a cover file to provide bi-architecture (32/64) support. */
#define RS6000_BI_ARCH 1

169
gcc/config/powerpcspe/bmi2intrin.h
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/* Copyright (C) 2011-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This header is distributed to simplify porting x86_64 code that
makes explicit use of Intel intrinsics to powerpc64le.
It is the user's responsibility to determine if the results are
acceptable and make additional changes as necessary.
Note that much code that uses Intel intrinsics can be rewritten in
standard C or GNU C extensions, which are more portable and better
optimized across multiple targets. */
#if !defined _X86INTRIN_H_INCLUDED
# error "Never use <bmi2intrin.h> directly; include <x86intrin.h> instead."
#endif
#ifndef _BMI2INTRIN_H_INCLUDED
#define _BMI2INTRIN_H_INCLUDED
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bzhi_u32 (unsigned int __X, unsigned int __Y)
{
return ((__X << (32 - __Y)) >> (32 - __Y));
}
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mulx_u32 (unsigned int __X, unsigned int __Y, unsigned int *__P)
{
unsigned long long __res = (unsigned long long) __X * __Y;
*__P = (unsigned int) (__res >> 32);
return (unsigned int) __res;
}
#ifdef __PPC64__
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bzhi_u64 (unsigned long long __X, unsigned long long __Y)
{
return ((__X << (64 - __Y)) >> (64 - __Y));
}
/* __int128 requires base 64-bit. */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mulx_u64 (unsigned long long __X, unsigned long long __Y,
unsigned long long *__P)
{
unsigned __int128 __res = (unsigned __int128) __X * __Y;
*__P = (unsigned long long) (__res >> 64);
return (unsigned long long) __res;
}
#ifdef _ARCH_PWR7
/* popcount and bpermd require power7 minimum. */
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pdep_u64 (unsigned long long __X, unsigned long long __M)
{
unsigned long result = 0x0UL;
const unsigned long mask = 0x8000000000000000UL;
unsigned long m = __M;
unsigned long c, t;
unsigned long p;
/* The pop-count of the mask gives the number of the bits from
source to process. This is also needed to shift bits from the
source into the correct position for the result. */
p = 64 - __builtin_popcountl (__M);
/* The loop is for the number of '1' bits in the mask and clearing
each mask bit as it is processed. */
while (m != 0)
{
c = __builtin_clzl (m);
t = __X << (p - c);
m ^= (mask >> c);
result |= (t & (mask >> c));
p++;
}
return (result);
}
extern __inline unsigned long long
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pext_u64 (unsigned long long __X, unsigned long long __M)
{
unsigned long p = 0x4040404040404040UL; // initial bit permute control
const unsigned long mask = 0x8000000000000000UL;
unsigned long m = __M;
unsigned long c;
unsigned long result;
/* if the mask is constant and selects 8 bits or less we can use
the Power8 Bit permute instruction. */
if (__builtin_constant_p (__M) && (__builtin_popcountl (__M) <= 8))
{
/* Also if the pext mask is constant, then the popcount is
constant, we can evaluate the following loop at compile
time and use a constant bit permute vector. */
for (long i = 0; i < __builtin_popcountl (__M); i++)
{
c = __builtin_clzl (m);
p = (p << 8) | c;
m ^= (mask >> c);
}
result = __builtin_bpermd (p, __X);
}
else
{
p = 64 - __builtin_popcountl (__M);
result = 0;
/* We could a use a for loop here, but that combined with
-funroll-loops can expand to a lot of code. The while
loop avoids unrolling and the compiler commons the xor
from clearing the mask bit with the (m != 0) test. The
result is a more compact loop setup and body. */
while (m != 0)
{
unsigned long t;
c = __builtin_clzl (m);
t = (__X & (mask >> c)) >> (p - c);
m ^= (mask >> c);
result |= (t);
p++;
}
}
return (result);
}
/* these 32-bit implementations depend on 64-bit pdep/pext
which depend on _ARCH_PWR7. */
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pdep_u32 (unsigned int __X, unsigned int __Y)
{
return _pdep_u64 (__X, __Y);
}
extern __inline unsigned int
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_pext_u32 (unsigned int __X, unsigned int __Y)
{
return _pext_u64 (__X, __Y);
}
#endif /* _ARCH_PWR7 */
#endif /* __PPC64__ */
#endif /* _BMI2INTRIN_H_INCLUDED */

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gcc/config/powerpcspe/bmiintrin.h
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/* Copyright (C) 2010-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This header is distributed to simplify porting x86_64 code that
makes explicit use of Intel intrinsics to powerpc64le.
It is the user's responsibility to determine if the results are
acceptable and make additional changes as necessary.
Note that much code that uses Intel intrinsics can be rewritten in
standard C or GNU C extensions, which are more portable and better
optimized across multiple targets. */
#if !defined _X86INTRIN_H_INCLUDED
# error "Never use <bmiintrin.h> directly; include <x86intrin.h> instead."
#endif
#ifndef _BMIINTRIN_H_INCLUDED
#define _BMIINTRIN_H_INCLUDED
extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u16 (unsigned short __X)
{
return __builtin_ctz (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__andn_u32 (unsigned int __X, unsigned int __Y)
{
return (~__X & __Y);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bextr_u32 (unsigned int __X, unsigned int __P, unsigned int __L)
{
return ((__X << (32 - (__L + __P))) >> (32 - __L));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bextr_u32 (unsigned int __X, unsigned int __Y)
{
unsigned int __P, __L;
__P = __Y & 0xFF;
__L = (__Y >> 8) & 0xFF;
return (_bextr_u32 (__X, __P, __L));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsi_u32 (unsigned int __X)
{
return (__X & -__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsi_u32 (unsigned int __X)
{
return __blsi_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsmsk_u32 (unsigned int __X)
{
return (__X ^ (__X - 1));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsmsk_u32 (unsigned int __X)
{
return __blsmsk_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsr_u32 (unsigned int __X)
{
return (__X & (__X - 1));
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsr_u32 (unsigned int __X)
{
return __blsr_u32 (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u32 (unsigned int __X)
{
return __builtin_ctz (__X);
}
extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_tzcnt_u32 (unsigned int __X)
{
return __builtin_ctz (__X);
}
/* use the 64-bit shift, rotate, and count leading zeros instructions
for long long. */
#ifdef __PPC64__
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__andn_u64 (unsigned long long __X, unsigned long long __Y)
{
return (~__X & __Y);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_bextr_u64 (unsigned long long __X, unsigned int __P, unsigned int __L)
{
return ((__X << (64 - (__L + __P))) >> (64 - __L));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__bextr_u64 (unsigned long long __X, unsigned long long __Y)
{
unsigned int __P, __L;
__P = __Y & 0xFF;
__L = (__Y & 0xFF00) >> 8;
return (_bextr_u64 (__X, __P, __L));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsi_u64 (unsigned long long __X)
{
return __X & -__X;
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsi_u64 (unsigned long long __X)
{
return __blsi_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsmsk_u64 (unsigned long long __X)
{
return (__X ^ (__X - 1));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsmsk_u64 (unsigned long long __X)
{
return __blsmsk_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__blsr_u64 (unsigned long long __X)
{
return (__X & (__X - 1));
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_blsr_u64 (unsigned long long __X)
{
return __blsr_u64 (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
__tzcnt_u64 (unsigned long long __X)
{
return __builtin_ctzll (__X);
}
extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_tzcnt_u64 (unsigned long long __X)
{
return __builtin_ctzll (__X);
}
#endif /* __PPC64__ */
#endif /* _BMIINTRIN_H_INCLUDED */

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gcc/config/powerpcspe/cell.md
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;; Scheduling description for cell processor.
;; Copyright (C) 2001-2018 Free Software Foundation, Inc.
;; Contributed by Sony Computer Entertainment, Inc.,
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 3 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Sources: BE BOOK4 (/sfs/enc/doc/PPU_BookIV_DD3.0_latest.pdf)
;; BE Architecture *DD3.0 and DD3.1*
;; This file simulate PPU processor unit backend of pipeline, maualP24.
;; manual P27, stall and flush points
;; IU, XU, VSU, dispatcher decodes and dispatch 2 insns per cycle in program
;; order, the grouped address are aligned by 8
;; This file only simulate one thread situation
;; XU executes all fixed point insns(3 units, a simple alu, a complex unit,
;; and load/store unit)
;; VSU executes all scalar floating points insn(a float unit),
;; VMX insns(VMX unit, 4 sub units, simple, permute, complex, floating point)
;; Dual issue combination
;; FXU LSU BR VMX VMX
;; (sx,cx,vsu_fp,fp_arith) (perm,vsu_ls,fp_ls)
;;FXU X
;;LSU X X X
;;BR X
;;VMX(sx,cx,vsu_fp,fp_arth) X
;;VMX(perm,vsu_ls, fp_ls) X
;; X are illegal combination.
;; Dual issue exceptions:
;;(1) nop-pipelined FXU instr in slot 0
;;(2) non-pipelined FPU inst in slot 0
;; CSI instr(contex-synchronizing insn)
;; Microcode insn
;; BRU unit: bru(none register stall), bru_cr(cr register stall)
;; VSU unit: vus(vmx simple), vup(vmx permute), vuc(vmx complex),
;; vuf(vmx float), fpu(floats). fpu_div is hypothetical, it is for
;; nonpipelined simulation
;; micr insns will stall at least 7 cycles to get the first instr from ROM,
;; micro instructions are not dual issued.
;; slot0 is older than slot1
;; non-pipelined insn need to be in slot1 to avoid 1cycle stall
;; There different stall point
;; IB2, only stall one thread if stall here, so try to stall here as much as
;; we can
;; condition(1) insert nop, OR and ORI instruction form
;; condition(2) flush happens, in case of: RAW, WAW, D-ERAT miss, or
;; CR0-access while stdcx, or stwcx
;; IS2 stall ;; Page91 for details
;; VQ8 stall
;; IS2 stall can be activated by VQ8 stall and trying to issue a vsu instr to
;; the vsu issue queue
;;(define_automaton "cellxu")
;;(define_cpu_unit "fxu_cell,lsu_cell,bru_cell,vsu1_cell,vsu2_cell" "cellxu")
;; ndfa
(define_automaton "cellxu,cellvsu,cellbru,cell_mis")
(define_cpu_unit "fxu_cell,lsu_cell" "cellxu")
(define_cpu_unit "bru_cell" "cellbru")
(define_cpu_unit "vsu1_cell,vsu2_cell" "cellvsu")
(define_cpu_unit "slot0,slot1" "cell_mis")
(absence_set "slot0" "slot1")
(define_reservation "nonpipeline" "fxu_cell+lsu_cell+vsu1_cell+vsu2_cell")
(define_reservation "slot01" "slot0|slot1")
;; Load/store
;; lmw, lswi, lswx are only generated for optimize for space, MC,
;; these instr are not simulated
(define_insn_reservation "cell-load" 2
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "cell"))
"slot01,lsu_cell")
;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs,
;; if with 32bytes alignment, CMC
(define_insn_reservation "cell-load-ux" 2
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell")
;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown
;; 11/7, 11/8, 11/12
(define_insn_reservation "cell-load-ext" 2
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell+lsu_cell")
;;lfs,lfsx,lfd,lfdx, 1 cycle
(define_insn_reservation "cell-fpload" 1
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01")
;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr)
(define_insn_reservation "cell-fpload-update" 1
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell"))
"fxu_cell+vsu2_cell+lsu_cell+slot01")
(define_insn_reservation "cell-vecload" 2
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "cell"))
"slot01,vsu2_cell+lsu_cell")
;;st? stw(MC)
(define_insn_reservation "cell-store" 1
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "cell"))
"lsu_cell+slot01")
;;stdux, stdu, (hardware breaks into store and add) 2 for update reg
(define_insn_reservation "cell-store-update" 1
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell"))
"fxu_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01")
(define_insn_reservation "cell-fpstore-update" 1
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "cell"))
"vsu2_cell+fxu_cell+lsu_cell+slot01")
(define_insn_reservation "cell-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "cell"))
"vsu2_cell+lsu_cell+slot01")
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
;; Two integer latency is 4 cycles
(define_insn_reservation "cell-two" 4
(and (eq_attr "type" "two")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell,fxu_cell*2")
;; Three integer latency is 6 cycles
(define_insn_reservation "cell-three" 6
(and (eq_attr "type" "three")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell,fxu_cell*4")
;; rlwimi, alter cr0
(define_insn_reservation "cell-insert" 2
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
;; cmpi, cmpli, cmpla, add, addo, sub, subo, alter cr0
(define_insn_reservation "cell-cmp" 1
(and (eq_attr "type" "cmp")
(eq_attr "cpu" "cell"))
"fxu_cell+slot01")
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
"slot01,fxu_cell")
(define_insn_reservation "cell-cmp-microcoded" 9
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
"slot0+slot1,fxu_cell,fxu_cell*7")
;; mulld
(define_insn_reservation "cell-lmul" 15
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*13")
;; mulld. is microcoded
(define_insn_reservation "cell-lmul-cmp" 22
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot0+slot1,nonpipeline,nonpipeline*20")
;; mulli, 6 cycles
(define_insn_reservation "cell-imul23" 6
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*4")
;; mullw, 9
(define_insn_reservation "cell-imul" 9
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*7")
;; divide
(define_insn_reservation "cell-idiv" 32
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*30")
(define_insn_reservation "cell-ldiv" 64
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*62")
;;mflr and mfctr are pipelined
(define_insn_reservation "cell-mfjmpr" 1
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "cell"))
"slot01+bru_cell")
;;mtlr and mtctr,
;;mtspr fully pipelined
(define_insn_reservation "cell-mtjmpr" 1
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "cell"))
"bru_cell+slot01")
;; Branches
;; b, ba, bl, bla, unconditional branch always predicts correctly n/a latency
;; bcctr, bcctrl, latency 2, actually adjust by be to 4
(define_insn_reservation "cell-branch" 1
(and (eq_attr "type" "branch")
(eq_attr "cpu" "cell"))
"bru_cell+slot1")
(define_insn_reservation "cell-branchreg" 1
(and (eq_attr "type" "jmpreg")
(eq_attr "cpu" "cell"))
"bru_cell+slot1")
;; cr hazard
;; page 90, special cases for CR hazard, only one instr can access cr per cycle
;; if insn reads CR following a stwcx, pipeline stall till stwcx finish
(define_insn_reservation "cell-crlogical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "cell"))
"bru_cell+slot01")
;; mfcrf and mfcr is about 34 cycles and nonpipelined
(define_insn_reservation "cell-mfcr" 34
(and (eq_attr "type" "mfcrf,mfcr")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*32")
;; mtcrf (1 field)
(define_insn_reservation "cell-mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "cell"))
"fxu_cell+slot01")
; Basic FP latency is 10 cycles, thoughput is 1/cycle
(define_insn_reservation "cell-fp" 10
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*8")
(define_insn_reservation "cell-fpcompare" 1
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "cell"))
"vsu1_cell+slot01")
;; sdiv thoughput 1/74, not pipelined but only in the FPU
(define_insn_reservation "cell-sdiv" 74
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*72")
;; fsqrt thoughput 1/84, not pipelined but only in the FPU
(define_insn_reservation "cell-sqrt" 84
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*82")
; VMX
(define_insn_reservation "cell-vecsimple" 4
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
;; mult, div, madd
(define_insn_reservation "cell-veccomplex" 10
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*8")
;; TODO: add support for recording instructions
(define_insn_reservation "cell-veccmp" 4
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*2")
(define_insn_reservation "cell-vecfloat" 12
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "cell"))
"slot01,vsu1_cell,vsu1_cell*10")
(define_insn_reservation "cell-vecperm" 4
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "cell"))
"slot01,vsu2_cell,vsu2_cell*2")
;; New for 4.2, syncs
(define_insn_reservation "cell-sync" 11
(and (eq_attr "type" "sync")
(eq_attr "cpu" "cell"))
"slot01,lsu_cell,lsu_cell*9")
(define_insn_reservation "cell-isync" 11
(and (eq_attr "type" "isync")
(eq_attr "cpu" "cell"))
"slot01,lsu_cell,lsu_cell*9")
(define_insn_reservation "cell-load_l" 11
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "cell"))
"slot01,lsu_cell,lsu_cell*9")
(define_insn_reservation "cell-store_c" 11
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "cell"))
"slot01,lsu_cell,lsu_cell*9")
;; RAW register dependency
;; addi r3, r3, 1
;; lw r4,offset(r3)
;; there are 5 cycle deplay for r3 bypassing
;; there are 5 cycle delay for a dependent load after a load
(define_bypass 5 "cell-integer" "cell-load")
(define_bypass 5 "cell-integer" "cell-load-ext")
(define_bypass 5 "cell-load,cell-load-ext" "cell-load,cell-load-ext")
;; there is a 6 cycle delay after a fp compare until you can use the cr.
(define_bypass 6 "cell-fpcompare" "cell-branch,cell-branchreg,cell-mfcr,cell-crlogical")
;; VXU float RAW
(define_bypass 11 "cell-vecfloat" "cell-vecfloat")
;; VXU and FPU
(define_bypass 6 "cell-veccomplex" "cell-vecsimple")
;;(define_bypass 6 "cell-veccompare" "cell-branch,cell-branchreg")
(define_bypass 3 "cell-vecfloat" "cell-veccomplex")
; this is not correct,
;; this is a stall in general and not dependent on result
(define_bypass 13 "cell-vecstore" "cell-fpstore")
; this is not correct, this can never be true, not dependent on result
(define_bypass 7 "cell-fp" "cell-fpload")
;; vsu1 should avoid writing to the same target register as vsu2 insn
;; within 12 cycles.
;; WAW hazard
;; the target of VSU estimate should not be reused within 10 dispatch groups
;; the target of VSU float should not be reused within 8 dispatch groups
;; the target of VSU complex should not be reused within 5 dispatch groups
;; FP LOAD should not reuse an FPU Arithmetic target with 6 dispatch gropus
;; mtctr-bcctr/bcctrl, branch target ctr register shadow update at
;; ex4 stage(10 cycles)
(define_bypass 10 "cell-mtjmpr" "cell-branchreg")
;;Things are not simulated:
;; update instruction, update address gpr are not simulated
;; vrefp, vrsqrtefp have latency(14), currently simulated as 12 cycle float
;; insns

323
gcc/config/powerpcspe/constraints.md
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@ -1,323 +0,0 @@
;; Constraint definitions for RS6000
;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Available constraint letters: e k q t u A B C D S T
;; Register constraints
(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
"@internal")
(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
"@internal")
(define_register_constraint "b" "BASE_REGS"
"@internal")
(define_register_constraint "h" "SPECIAL_REGS"
"@internal")
(define_register_constraint "c" "CTR_REGS"
"@internal")
(define_register_constraint "l" "LINK_REGS"
"@internal")
(define_register_constraint "v" "ALTIVEC_REGS"
"@internal")
(define_register_constraint "x" "CR0_REGS"
"@internal")
(define_register_constraint "y" "CR_REGS"
"@internal")
(define_register_constraint "z" "CA_REGS"
"@internal")
;; Use w as a prefix to add VSX modes
;; any VSX register
(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
"Any VSX register if the -mvsx option was used or NO_REGS.")
(define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]"
"Altivec register if the -mpower9-dform option was used or NO_REGS.")
;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
;; It is currently used for that purpose in LLVM.
(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
"VSX vector register to hold vector double data or NO_REGS.")
(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
"VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
"VSX vector register to hold vector float data or NO_REGS.")
(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
"If -mmfpgpr was used, a floating point register or NO_REGS.")
(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
"Floating point register if direct moves are available, or NO_REGS.")
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
"FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
"FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
"Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
"VSX register if direct move instructions are enabled, or NO_REGS.")
;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
;; direct move directly, and movsf can't to move between the register sets.
;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]"
"VSX register if the -mpower9-vector option was used or NO_REGS.")
(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
"VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
(define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
"VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.")
(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
"General purpose register if 64-bit instructions are enabled or NO_REGS.")
(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
"VSX vector register to hold scalar double values or NO_REGS.")
(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
"VSX vector register to hold 128 bit integer or NO_REGS.")
(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
"Altivec register to use for float/32-bit int loads/stores or NO_REGS.")
(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
"Altivec register to use for double loads/stores or NO_REGS.")
(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
"FP or VSX register to perform float operations under -mvsx or NO_REGS.")
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
"FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
"BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
;; wB needs ISA 2.07 VUPKHSW
(define_constraint "wB"
"Signed 5-bit constant integer that can be loaded into an altivec register."
(and (match_code "const_int")
(and (match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand"))))
(define_constraint "wD"
"Int constant that is the element number of the 64-bit scalar in a vector."
(and (match_code "const_int")
(match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)")))
(define_constraint "wE"
"Vector constant that can be loaded with the XXSPLTIB instruction."
(match_test "xxspltib_constant_nosplit (op, mode)"))
;; Extended fusion store
(define_memory_constraint "wF"
"Memory operand suitable for power9 fusion load/stores"
(match_operand 0 "fusion_addis_mem_combo_load"))
;; Fusion gpr load.
(define_memory_constraint "wG"
"Memory operand suitable for TOC fusion memory references"
(match_operand 0 "toc_fusion_mem_wrapped"))
(define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]"
"Altivec register to hold 32-bit integers or NO_REGS.")
(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]"
"FPR register to hold 32-bit integers or NO_REGS.")
(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]"
"FPR register to hold 8/16-bit integers or NO_REGS.")
(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]"
"Altivec register to hold 8/16-bit integers or NO_REGS.")
(define_constraint "wL"
"Int constant that is the element number mfvsrld accesses in a vector."
(and (match_code "const_int")
(and (match_test "TARGET_DIRECT_MOVE_128")
(match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
;; Generate the XXORC instruction to set a register to all 1's
(define_constraint "wM"
"Match vector constant with all 1's if the XXLORC instruction is available"
(and (match_test "TARGET_P8_VECTOR")
(match_operand 0 "all_ones_constant")))
;; ISA 3.0 vector d-form addresses
(define_memory_constraint "wO"
"Memory operand suitable for the ISA 3.0 vector d-form instructions."
(match_operand 0 "vsx_quad_dform_memory_operand"))
;; Lq/stq validates the address for load/store quad
(define_memory_constraint "wQ"
"Memory operand suitable for the load/store quad instructions"
(match_operand 0 "quad_memory_operand"))
(define_constraint "wS"
"Vector constant that can be loaded with XXSPLTIB & sign extension."
(match_test "xxspltib_constant_split (op, mode)"))
;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form.
;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four
;; offset is enforced for 32-bit too.
(define_memory_constraint "wY"
"Offsettable memory operand, with bottom 2 bits 0"
(and (match_code "mem")
(not (match_test "update_address_mem (op, mode)"))
(match_test "mem_operand_ds_form (op, mode)")))
;; Altivec style load/store that ignores the bottom bits of the address
(define_memory_constraint "wZ"
"Indexed or indirect memory operand, ignoring the bottom 4 bits"
(match_operand 0 "altivec_indexed_or_indirect_operand"))
;; Integer constraints
(define_constraint "I"
"A signed 16-bit constant"
(and (match_code "const_int")
(match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000")))
(define_constraint "J"
"high-order 16 bits nonzero"
(and (match_code "const_int")
(match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
(define_constraint "K"
"low-order 16 bits nonzero"
(and (match_code "const_int")
(match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
(define_constraint "L"
"signed 16-bit constant shifted left 16 bits"
(and (match_code "const_int")
(match_test "((ival & 0xffff) == 0
&& (ival >> 31 == -1 || ival >> 31 == 0))")))
(define_constraint "M"
"constant greater than 31"
(and (match_code "const_int")
(match_test "ival > 31")))
(define_constraint "N"
"positive constant that is an exact power of two"
(and (match_code "const_int")
(match_test "ival > 0 && exact_log2 (ival) >= 0")))
(define_constraint "O"
"constant zero"
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "P"
"constant whose negation is signed 16-bit constant"
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
;; Floating-point constraints
(define_constraint "G"
"Constant that can be copied into GPR with two insns for DF/DI
and one for SF."
(and (match_code "const_double")
(match_test "num_insns_constant (op, mode)
== (mode == SFmode ? 1 : 2)")))
(define_constraint "H"
"DF/DI constant that takes three insns."
(and (match_code "const_double")
(match_test "num_insns_constant (op, mode) == 3")))
;; Memory constraints
(define_memory_constraint "es"
"A ``stable'' memory operand; that is, one which does not include any
automodification of the base register. Unlike @samp{m}, this constraint
can be used in @code{asm} statements that might access the operand
several times, or that might not access it at all."
(and (match_code "mem")
(match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
(define_memory_constraint "Q"
"Memory operand that is an offset from a register (it is usually better
to use @samp{m} or @samp{es} in @code{asm} statements)"
(and (match_code "mem")
(match_test "GET_CODE (XEXP (op, 0)) == REG")))
(define_memory_constraint "Y"
"memory operand for 8 byte and 16 byte gpr load/store"
(and (match_code "mem")
(match_test "mem_operand_gpr (op, mode)")))
(define_memory_constraint "Z"
"Memory operand that is an indexed or indirect from a register (it is
usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
(match_operand 0 "indexed_or_indirect_operand"))
;; Address constraints
(define_address_constraint "a"
"Indexed or indirect address operand"
(match_operand 0 "indexed_or_indirect_address"))
(define_constraint "R"
"AIX TOC entry"
(match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
;; General constraints
(define_constraint "U"
"V.4 small data reference"
(and (match_test "DEFAULT_ABI == ABI_V4")
(match_test "small_data_operand (op, mode)")))
(define_constraint "W"
"vector constant that does not require memory"
(match_operand 0 "easy_vector_constant"))
(define_constraint "j"
"Zero vector constant"
(match_test "op == const0_rtx || op == CONST0_RTX (mode)"))

110
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@ -1,110 +0,0 @@
;; Cryptographic instructions added in ISA 2.07
;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; NOTE: Although this file contains all the instructions from
;; section 5.11 of ISA 2.07, only those in sections 5.11.1 and
;; 5.11.2 are in Category:Vector.Crypto. Those are the only
;; ones controlled by -m[no-]crypto.
;; FIXME: The builtin names for the instructions in this file
;; are likely to be deprecated in favor of other names to be
;; agreed upon with the XL compilers and LLVM.
(define_c_enum "unspec"
[UNSPEC_VCIPHER
UNSPEC_VNCIPHER
UNSPEC_VCIPHERLAST
UNSPEC_VNCIPHERLAST
UNSPEC_VSBOX
UNSPEC_VSHASIGMA
UNSPEC_VPERMXOR
UNSPEC_VPMSUM])
;; Iterator for VPMSUM/VPERMXOR
(define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])
(define_mode_attr CR_char [(V16QI "b")
(V8HI "h")
(V4SI "w")
(V2DI "d")])
;; Iterator for VSHASIGMAD/VSHASIGMAW
(define_mode_iterator CR_hash [V4SI V2DI])
;; Iterator for the other crypto functions
(define_int_iterator CR_code [UNSPEC_VCIPHER
UNSPEC_VNCIPHER
UNSPEC_VCIPHERLAST
UNSPEC_VNCIPHERLAST])
(define_int_attr CR_insn [(UNSPEC_VCIPHER "vcipher")
(UNSPEC_VNCIPHER "vncipher")
(UNSPEC_VCIPHERLAST "vcipherlast")
(UNSPEC_VNCIPHERLAST "vncipherlast")])
;; 2 operand crypto instructions
(define_insn "crypto_<CR_insn>"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")
(match_operand:V2DI 2 "register_operand" "v")]
CR_code))]
"TARGET_CRYPTO"
"<CR_insn> %0,%1,%2"
[(set_attr "type" "crypto")])
(define_insn "crypto_vpmsum<CR_char>"
[(set (match_operand:CR_mode 0 "register_operand" "=v")
(unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
(match_operand:CR_mode 2 "register_operand" "v")]
UNSPEC_VPMSUM))]
"TARGET_P8_VECTOR"
"vpmsum<CR_char> %0,%1,%2"
[(set_attr "type" "crypto")])
;; 3 operand crypto instructions
(define_insn "crypto_vpermxor_<mode>"
[(set (match_operand:CR_mode 0 "register_operand" "=v")
(unspec:CR_mode [(match_operand:CR_mode 1 "register_operand" "v")
(match_operand:CR_mode 2 "register_operand" "v")
(match_operand:CR_mode 3 "register_operand" "v")]
UNSPEC_VPERMXOR))]
"TARGET_P8_VECTOR"
"vpermxor %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
;; 1 operand crypto instruction
(define_insn "crypto_vsbox"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "v")]
UNSPEC_VSBOX))]
"TARGET_CRYPTO"
"vsbox %0,%1"
[(set_attr "type" "crypto")])
;; Hash crypto instructions
(define_insn "crypto_vshasigma<CR_char>"
[(set (match_operand:CR_hash 0 "register_operand" "=v")
(unspec:CR_hash [(match_operand:CR_hash 1 "register_operand" "v")
(match_operand:SI 2 "const_0_to_1_operand" "n")
(match_operand:SI 3 "const_0_to_15_operand" "n")]
UNSPEC_VSHASIGMA))]
"TARGET_CRYPTO"
"vshasigma<CR_char> %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])

420
gcc/config/powerpcspe/darwin.h
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@ -1,420 +0,0 @@
/* Target definitions for PowerPC running Darwin (Mac OS X).
Copyright (C) 1997-2018 Free Software Foundation, Inc.
Contributed by Apple Computer Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef DARWIN_PPC
#define DARWIN_PPC 1
/* The "Darwin ABI" is mostly like AIX, but with some key differences. */
#define DEFAULT_ABI ABI_DARWIN
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __powerpc64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
/* The object file format is Mach-O. */
#define TARGET_OBJECT_FORMAT OBJECT_MACHO
/* Size of the Obj-C jump buffer. */
#define OBJC_JBLEN ((TARGET_64BIT) ? (26*2 + 18*2 + 129 + 1) : (26 + 18*2 + 129 + 1))
/* We're not ever going to do TOCs. */
#define TARGET_TOC 0
#define TARGET_NO_TOC 1
/* Override the default rs6000 definition. */
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int")
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
if (!TARGET_64BIT) builtin_define ("__ppc__"); \
if (TARGET_64BIT) builtin_define ("__ppc64__"); \
builtin_define ("__POWERPC__"); \
builtin_define ("__NATURAL_ALIGNMENT__"); \
darwin_cpp_builtins (pfile); \
} \
while (0)
/* Generate branch islands stubs if this is true. */
extern int darwin_emit_branch_islands;
#define SUBTARGET_OVERRIDE_OPTIONS darwin_rs6000_override_options ()
#define C_COMMON_OVERRIDE_OPTIONS do { \
/* On powerpc, __cxa_get_exception_ptr is available starting in the \
10.4.6 libstdc++.dylib. */ \
if (strverscmp (darwin_macosx_version_min, "10.4.6") < 0 \
&& flag_use_cxa_get_exception_ptr == 2) \
flag_use_cxa_get_exception_ptr = 0; \
if (flag_mkernel) \
flag_no_builtin = 1; \
SUBTARGET_C_COMMON_OVERRIDE_OPTIONS; \
} while (0)
/* Darwin has 128-bit long double support in libc in 10.4 and later.
Default to 128-bit long doubles even on earlier platforms for ABI
consistency; arithmetic will work even if libc and libm support is
not available. */
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 128
/* We want -fPIC by default, unless we're using -static to compile for
the kernel or some such. The "-faltivec" option should have been
called "-maltivec" all along. */
#define CC1_SPEC "\
%(cc1_cpu) \
%{g: %{!fno-eliminate-unused-debug-symbols: -feliminate-unused-debug-symbols }} \
%{static: %{Zdynamic: %e conflicting code gen style switches are used}}\
%{!mkernel:%{!static:%{!mdynamic-no-pic:-fPIC}}} \
%{faltivec:-maltivec -include altivec.h} %{fno-altivec:-mno-altivec} \
%<faltivec %<fno-altivec " \
DARWIN_CC1_SPEC
#define DARWIN_ARCH_SPEC "%{m64:ppc64;:ppc}"
#define DARWIN_SUBARCH_SPEC " \
%{m64: ppc64} \
%{!m64: \
%{mcpu=601:ppc601; \
mcpu=603:ppc603; \
mcpu=603e:ppc603; \
mcpu=604:ppc604; \
mcpu=604e:ppc604e; \
mcpu=740:ppc750; \
mcpu=750:ppc750; \
mcpu=G3:ppc750; \
mcpu=7400:ppc7400; \
mcpu=G4:ppc7400; \
mcpu=7450:ppc7450; \
mcpu=970:ppc970; \
mcpu=power4:ppc970; \
mcpu=G5:ppc970; \
:ppc}}"
/* crt2.o is at least partially required for 10.3.x and earlier. */
#define DARWIN_CRT2_SPEC \
"%{!m64:%:version-compare(!> 10.4 mmacosx-version-min= crt2.o%s)}"
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
DARWIN_EXTRA_SPECS \
{ "darwin_arch", DARWIN_ARCH_SPEC }, \
{ "darwin_crt2", DARWIN_CRT2_SPEC }, \
{ "darwin_subarch", DARWIN_SUBARCH_SPEC },
/* Output a .machine directive. */
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START rs6000_darwin_file_start
/* Make both r2 and r13 available for allocation. */
#define FIXED_R2 0
#define FIXED_R13 0
/* Base register for access to local variables of the function. */
#undef HARD_FRAME_POINTER_REGNUM
#define HARD_FRAME_POINTER_REGNUM 30
#undef RS6000_PIC_OFFSET_TABLE_REGNUM
#define RS6000_PIC_OFFSET_TABLE_REGNUM 31
/* Pad the outgoing args area to 16 bytes instead of the usual 8. */
#undef RS6000_STARTING_FRAME_OFFSET
#define RS6000_STARTING_FRAME_OFFSET \
(RS6000_ALIGN (crtl->outgoing_args_size, 16) \
+ RS6000_SAVE_AREA)
#undef STACK_DYNAMIC_OFFSET
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
(RS6000_ALIGN (crtl->outgoing_args_size.to_constant (), 16) \
+ (STACK_POINTER_OFFSET))
/* Darwin uses a function call if everything needs to be saved/restored. */
#undef WORLD_SAVE_P
#define WORLD_SAVE_P(INFO) ((INFO)->world_save_p)
/* We don't use these on Darwin, they are just place-holders. */
#define SAVE_FP_PREFIX ""
#define SAVE_FP_SUFFIX ""
#define RESTORE_FP_PREFIX ""
#define RESTORE_FP_SUFFIX ""
/* The assembler wants the alternate register names, but without
leading percent sign. */
#undef REGISTER_NAMES
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
"mq", "lr", "ctr", "ap", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
"xer", \
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
"vrsave", "vscr", \
"spe_acc", "spefscr", \
"sfp", \
"tfhar", "tfiar", "texasr", \
"rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", \
"rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", \
"rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", \
"rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31" \
}
/* This outputs NAME to FILE. */
#undef RS6000_OUTPUT_BASENAME
#define RS6000_OUTPUT_BASENAME(FILE, NAME) \
assemble_name (FILE, NAME)
/* Globalizing directive for a label. */
#undef GLOBAL_ASM_OP
#define GLOBAL_ASM_OP "\t.globl "
#undef TARGET_ASM_GLOBALIZE_LABEL
/* This is how to output an internal label prefix. rs6000.c uses this
when generating traceback tables. */
/* Not really used for Darwin? */
#undef ASM_OUTPUT_INTERNAL_LABEL_PREFIX
#define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX) \
fprintf (FILE, "%s", PREFIX)
/* Override the standard rs6000 definition. */
#undef ASM_COMMENT_START
#define ASM_COMMENT_START ";"
/* This is how to output an assembler line that says to advance
the location counter to a multiple of 2**LOG bytes using the
"nop" instruction as padding. */
#define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
do \
{ \
if ((LOG) < 3) \
{ \
ASM_OUTPUT_ALIGN (FILE,LOG); \
} \
else /* nop == ori r0,r0,0 */ \
fprintf (FILE, "\t.align32 %d,0x60000000\n", (LOG)); \
} while (0)
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
/* This is supported in cctools 465 and later. The macro test
above prevents using it in earlier build environments. */
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
}
#endif
/* Generate insns to call the profiler. */
#define PROFILE_HOOK(LABEL) output_profile_hook (LABEL)
/* Function name to call to do profiling. */
#define RS6000_MCOUNT "*mcount"
/* Default processor: G4, and G5 for 64-bit. */
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC7400
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
/* Default target flag settings. Despite the fact that STMW/LMW
serializes, it's still a big code size win to use them. Use FSEL by
default as well. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT)
/* Darwin always uses IBM long double, never IEEE long double. */
#undef TARGET_IEEEQUAD
#define TARGET_IEEEQUAD 0
/* Since Darwin doesn't do TOCs, stub this out. */
#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE) ((void)X, (void)MODE, 0)
/* Unlike most other PowerPC targets, chars are signed, for
consistency with other Darwin architectures. */
#undef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR (1)
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
in some cases it is preferable to use a more restrictive class.
On the RS/6000, we have to return NO_REGS when we want to reload a
floating-point CONST_DOUBLE to force it to be copied to memory.
Don't allow R0 when loading the address of, or otherwise furtling with,
a SYMBOL_REF. */
#undef PREFERRED_RELOAD_CLASS
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
((CONSTANT_P (X) \
&& reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
? NO_REGS \
: ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == HIGH) \
&& reg_class_subset_p (BASE_REGS, (CLASS))) \
? BASE_REGS \
: (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
&& (CLASS) == NON_SPECIAL_REGS) \
? GENERAL_REGS \
: (CLASS))
/* Compute field alignment.
This implements the 'power' alignment rule by pegging the alignment of
items (beyond the first aggregate field) to 32 bits. The pegging is
suppressed for vector and long double items (both 128 in size).
There is a dummy use of the FIELD argument to avoid an unused variable
warning (see PR59496). */
#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
((void) (FIELD), \
(TARGET_ALIGN_NATURAL \
? (COMPUTED) \
: (COMPUTED) == 128 \
? 128 \
: MIN ((COMPUTED), 32)))
/* Darwin increases natural record alignment to doubleword if the first
field is an FP double while the FP fields remain word aligned. */
#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
((TREE_CODE (STRUCT) == RECORD_TYPE \
|| TREE_CODE (STRUCT) == UNION_TYPE \
|| TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
&& TARGET_ALIGN_NATURAL == 0 \
? darwin_rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED) \
: (TREE_CODE (STRUCT) == VECTOR_TYPE \
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (STRUCT))) \
? MAX (MAX ((COMPUTED), (SPECIFIED)), 128) \
: MAX ((COMPUTED), (SPECIFIED)))
/* Specify padding for the last element of a block move between
registers and memory. FIRST is nonzero if this is the only
element. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE))
#define DOUBLE_INT_ASM_OP "\t.quad\t"
/* For binary compatibility with 2.95; Darwin C APIs use bool from
stdbool.h, which was an int-sized enum in 2.95. Users can explicitly
choose to have sizeof(bool)==1 with the -mone-byte-bool switch. */
#define BOOL_TYPE_SIZE (darwin_one_byte_bool ? CHAR_TYPE_SIZE : INT_TYPE_SIZE)
#undef REGISTER_TARGET_PRAGMAS
#define REGISTER_TARGET_PRAGMAS() \
do \
{ \
DARWIN_REGISTER_TARGET_PRAGMAS(); \
targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
} \
while (0)
#ifdef IN_LIBGCC2
#include <stdbool.h>
#endif
/* True, iff we're generating fast turn around debugging code. When
true, we arrange for function prologues to start with 5 nops so
that gdb may insert code to redirect them, and for data to be
accessed indirectly. The runtime uses this indirection to forward
references for data to the original instance of that data. */
#define TARGET_FIX_AND_CONTINUE (darwin_fix_and_continue)
/* This is the reserved direct dispatch address for Objective-C. */
#define OFFS_MSGSEND_FAST 0xFFFEFF00
/* This is the reserved ivar address Objective-C. */
#define OFFS_ASSIGNIVAR_FAST 0xFFFEFEC0
/* Old versions of Mac OS/Darwin don't have C99 functions available. */
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION darwin_libc_has_function
/* When generating kernel code or kexts, we don't use Altivec by
default, as kernel code doesn't save/restore those registers. */
#define OS_MISSING_ALTIVEC (flag_mkernel || flag_apple_kext)
/* Darwin has support for section anchors on powerpc*.
It is disabled for any section containing a "zero-sized item" (because these
are re-written as size=1 to be compatible with the OSX ld64).
The re-writing would interfere with the computation of anchor offsets.
Therefore, we place zero-sized items in their own sections and make such
sections unavailable to section anchoring. */
#undef TARGET_ASM_OUTPUT_ANCHOR
#define TARGET_ASM_OUTPUT_ANCHOR darwin_asm_output_anchor
#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
#define TARGET_USE_ANCHORS_FOR_SYMBOL_P darwin_use_anchors_for_symbol_p
#undef DARWIN_SECTION_ANCHORS
#define DARWIN_SECTION_ANCHORS 1
/* PPC Darwin has to rename some of the long double builtins. */
#undef SUBTARGET_INIT_BUILTINS
#define SUBTARGET_INIT_BUILTINS \
do { \
darwin_patch_builtins (); \
rs6000_builtin_decls[(unsigned) (RS6000_BUILTIN_CFSTRING)] \
= darwin_init_cfstring_builtins ((unsigned) (RS6000_BUILTIN_CFSTRING)); \
} while(0)
/* So far, there is no rs6000_fold_builtin, if one is introduced, then
this will need to be modified similar to the x86 case. */
#define TARGET_FOLD_BUILTIN SUBTARGET_FOLD_BUILTIN
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING

480
gcc/config/powerpcspe/darwin.md
View file

@ -1,480 +0,0 @@
/* Machine description patterns for PowerPC running Darwin (Mac OS X).
Copyright (C) 2004-2018 Free Software Foundation, Inc.
Contributed by Apple Computer Inc.
This file is part of GCC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
(define_insn "adddi3_high"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(high:DI (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
"addis %0,%1,ha16(%2)"
[(set_attr "length" "4")])
(define_insn "movdf_low_si"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
"*
{
switch (which_alternative)
{
case 0:
return \"lfd %0,lo16(%2)(%1)\";
case 1:
{
if (TARGET_POWERPC64 && TARGET_32BIT)
/* Note, old assemblers didn't support relocation here. */
return \"ld %0,lo16(%2)(%1)\";
else
{
output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
output_asm_insn (\"lwz %L0,4(%0)\", operands);
return (\"lwz %0,0(%0)\");
}
}
default:
gcc_unreachable ();
}
}"
[(set_attr "type" "load")
(set_attr "length" "4,12")])
(define_insn "movdf_low_di"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"*
{
switch (which_alternative)
{
case 0:
return \"lfd %0,lo16(%2)(%1)\";
case 1:
return \"ld %0,lo16(%2)(%1)\";
default:
gcc_unreachable ();
}
}"
[(set_attr "type" "load")
(set_attr "length" "4,4")])
(define_insn "movdf_low_st_si"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_insn "movdf_low_st_di"
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_insn "movsf_low_si"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsf_low_di"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsf_low_st_si"
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_insn "movsf_low_st_di"
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
;; 64-bit MachO load/store support
(define_insn "movdi_low"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
"@
ld %0,lo16(%2)(%1)
lfd %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsi_low_st"
[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:SI 0 "gpc_reg_operand" "r"))]
"TARGET_MACHO && ! TARGET_64BIT"
"stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_insn "movdi_low_st"
[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
"TARGET_MACHO && TARGET_64BIT"
"@
std %0,lo16(%2)(%1)
stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
;; Mach-O PIC trickery.
(define_expand "macho_high"
[(set (match_operand 0 "" "")
(high (match_operand 1 "" "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
emit_insn (gen_macho_high_di (operands[0], operands[1]));
else
emit_insn (gen_macho_high_si (operands[0], operands[1]));
DONE;
})
(define_insn "macho_high_si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
(high:SI (match_operand 1 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT"
"lis %0,ha16(%1)")
(define_insn "macho_high_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
(high:DI (match_operand 1 "" "")))]
"TARGET_MACHO && TARGET_64BIT"
"lis %0,ha16(%1)")
(define_expand "macho_low"
[(set (match_operand 0 "" "")
(lo_sum (match_operand 1 "" "")
(match_operand 2 "" "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
else
emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "macho_low_si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT"
"la %0,lo16(%2)(%1)")
(define_insn "macho_low_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"TARGET_MACHO && TARGET_64BIT"
"la %0,lo16(%2)(%1)")
(define_split
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "short_cint_operand" "")))
(match_operand:V4SI 2 "register_operand" ""))
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_MACHO && TARGET_64BIT"
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
(set (mem:V4SI (match_dup 3))
(match_dup 2))]
"")
(define_expand "load_macho_picbase"
[(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
if (TARGET_32BIT)
emit_insn (gen_load_macho_picbase_si (operands[0]));
else
emit_insn (gen_load_macho_picbase_di (operands[0]));
DONE;
})
(define_insn "load_macho_picbase_si"
[(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
(pc)] UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
#if TARGET_MACHO
machopic_should_output_picbase_label (); /* Update for new func. */
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
(set_attr "length" "4")])
(define_insn "load_macho_picbase_di"
[(set (reg:DI LR_REGNO)
(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
(pc)] UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
{
#if TARGET_MACHO
machopic_should_output_picbase_label (); /* Update for new func. */
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
(set_attr "length" "4")])
(define_expand "macho_correct_pic"
[(set (match_operand 0 "" "")
(plus (match_operand 1 "" "")
(unspec [(match_operand 2 "" "")
(match_operand 3 "" "")]
UNSPEC_MPIC_CORRECT)))]
"DEFAULT_ABI == ABI_DARWIN"
{
if (TARGET_32BIT)
emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
operands[3]));
else
emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
operands[3]));
DONE;
})
(define_insn "macho_correct_pic_si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
(match_operand:SI 3 "immediate_operand" "s")]
UNSPEC_MPIC_CORRECT)))]
"DEFAULT_ABI == ABI_DARWIN"
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
[(set_attr "length" "8")])
(define_insn "macho_correct_pic_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
(match_operand:DI 3 "immediate_operand" "s")]
16)))]
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
[(set_attr "length" "8")])
(define_insn "*call_indirect_nonlocal_darwin64"
[(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
(match_operand 1 "" "g,g,g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
(clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
{
return "b%T0l";
}
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
(set_attr "length" "4,4,8,8")])
(define_insn "*call_nonlocal_darwin64"
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
(match_operand 1 "" "g,g"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN)
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
{
#if TARGET_MACHO
return output_call(insn, operands, 0, 2);
#else
gcc_unreachable ();
#endif
}
[(set_attr "type" "branch,branch")
(set_attr "length" "4,8")])
(define_insn "*call_value_indirect_nonlocal_darwin64"
[(set (match_operand 0 "" "")
(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
(match_operand 2 "" "g,g,g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
(clobber (reg:SI LR_REGNO))]
"DEFAULT_ABI == ABI_DARWIN"
{
return "b%T1l";
}
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
(set_attr "length" "4,4,8,8")])
(define_insn "*call_value_nonlocal_darwin64"
[(set (match_operand 0 "" "")
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
(match_operand 2 "" "g,g")))
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(DEFAULT_ABI == ABI_DARWIN)
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
{
#if TARGET_MACHO
return output_call(insn, operands, 1, 3);
#else
gcc_unreachable ();
#endif
}
[(set_attr "type" "branch,branch")
(set_attr "length" "4,8")])
(define_expand "reload_macho_picbase"
[(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
if (TARGET_32BIT)
emit_insn (gen_reload_macho_picbase_si (operands[0]));
else
emit_insn (gen_reload_macho_picbase_di (operands[0]));
DONE;
})
(define_insn "reload_macho_picbase_si"
[(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
(pc)] UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
#if TARGET_MACHO
if (machopic_should_output_picbase_label ())
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
(set_attr "length" "4")])
(define_insn "reload_macho_picbase_di"
[(set (reg:DI LR_REGNO)
(unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
(pc)] UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
{
#if TARGET_MACHO
if (machopic_should_output_picbase_label ())
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
return "bcl 20,31,%0\\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
(set_attr "length" "4")])
;; We need to restore the PIC register, at the site of nonlocal label.
(define_insn_and_split "nonlocal_goto_receiver"
[(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
"TARGET_MACHO && flag_pic"
"#"
"&& reload_completed"
[(const_int 0)]
{
#if TARGET_MACHO
if (crtl->uses_pic_offset_table)
{
static unsigned n = 0;
rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
rtx tmplrtx;
char tmplab[20];
ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
emit_insn (gen_reload_macho_picbase (tmplrtx));
emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
}
else
/* Not using PIC reg, no reload needed. */
emit_note (NOTE_INSN_DELETED);
#else
gcc_unreachable ();
#endif
DONE;
})

42
gcc/config/powerpcspe/darwin.opt
View file

@ -1,42 +0,0 @@
; Darwin options for PPC port.
;
; Copyright (C) 2005-2018 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Waltivec-long-deprecated
Driver Alias(mwarn-altivec-long)
faltivec
Driver
; -ffix-and-continue and -findirect-data are for compatibility for old
; compilers.
ffix-and-continue
Driver RejectNegative Alias(mfix-and-continue)
findirect-data
Driver RejectNegative Alias(mfix-and-continue)
m64
Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code.
m32
Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code.

32
gcc/config/powerpcspe/darwin64.h
View file

@ -1,32 +0,0 @@
/* Target definitions for PowerPC running Darwin (Mac OS X).
Copyright (C) 2006-2018 Free Software Foundation, Inc.
Contributed by Apple Computer Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \
| MASK_MULTIPLE | MASK_PPC_GFXOPT)
#undef DARWIN_ARCH_SPEC
#define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}"
#undef DARWIN_SUBARCH_SPEC
#define DARWIN_SUBARCH_SPEC DARWIN_ARCH_SPEC
#undef DARWIN_CRT2_SPEC
#define DARWIN_CRT2_SPEC ""

32
gcc/config/powerpcspe/darwin7.h
View file

@ -1,32 +0,0 @@
/* Target definitions for Darwin 7.x (Mac OS X) systems.
Copyright (C) 2004-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Machine dependent libraries. Include libmx when compiling for
Darwin 7.0 and above, but before libSystem, since the functions are
actually in libSystem but for 7.x compatibility we want them to be
looked for in libmx first. Include libmx by default because otherwise
libstdc++ isn't usable. */
#undef LIB_SPEC
#define LIB_SPEC "%{!static:\
%:version-compare(!< 10.3 mmacosx-version-min= -lmx)\
-lSystem}"
#undef DEF_MIN_OSX_VERSION
#define DEF_MIN_OSX_VERSION "10.3.9"

31
gcc/config/powerpcspe/darwin8.h
View file

@ -1,31 +0,0 @@
/* Target definitions for Darwin 8.0 and above (Mac OS X) systems.
Copyright (C) 2004-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Machine dependent libraries. Include libmx when compiling on
Darwin 7.0 and above, but before libSystem, since the functions are
actually in libSystem but for 7.x compatibility we want them to be
looked for in libmx first---but only do this if 7.x compatibility
is a concern, which it's not in 64-bit mode. Include
libSystemStubs when compiling on (not necessarily for) 8.0 and
above and not 64-bit long double. */
#undef LIB_SPEC
#define LIB_SPEC "%{!static:\
%{!mlong-double-64:%{pg:-lSystemStubs_profile;:-lSystemStubs}} \
%{!m64:%:version-compare(>< 10.3 10.4 mmacosx-version-min= -lmx)} -lSystem}"

31
gcc/config/powerpcspe/default64.h
View file

@ -1,31 +0,0 @@
/* Definitions of target machine for GNU compiler,
for 64 bit powerpc linux defaulting to -m64.
Copyright (C) 2003-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define RS6000_CPU(NAME, CPU, FLAGS)
#include "rs6000-cpus.def"
#undef RS6000_CPU
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN)
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
#endif

419
gcc/config/powerpcspe/dfp.md
View file

@ -1,419 +0,0 @@
;; Decimal Floating Point (DFP) patterns.
;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
;; (bergner@vnet.ibm.com).
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; UNSPEC usage
;;
(define_c_enum "unspec"
[UNSPEC_MOVSD_LOAD
UNSPEC_MOVSD_STORE
])
(define_insn "movsd_store"
[(set (match_operand:DD 0 "nonimmediate_operand" "=m")
(unspec:DD [(match_operand:SD 1 "input_operand" "d")]
UNSPEC_MOVSD_STORE))]
"(gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS"
"stfd%U0%X0 %1,%0"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
(define_insn "movsd_load"
[(set (match_operand:SD 0 "nonimmediate_operand" "=f")
(unspec:SD [(match_operand:DD 1 "input_operand" "m")]
UNSPEC_MOVSD_LOAD))]
"(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS"
"lfd%U1%X1 %0,%1"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
;; Hardware support for decimal floating point operations.
(define_insn "extendsddd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
"TARGET_DFP"
"dctdp %0,%1"
[(set_attr "type" "dfp")])
(define_expand "extendsdtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
{
rtx tmp = gen_reg_rtx (DDmode);
emit_insn (gen_extendsddd2 (tmp, operands[1]));
emit_insn (gen_extendddtd2 (operands[0], tmp));
DONE;
})
(define_insn "truncddsd2"
[(set (match_operand:SD 0 "gpc_reg_operand" "=f")
(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drsp %0,%1"
[(set_attr "type" "dfp")])
(define_expand "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1"
[(set_attr "type" "fpsimple")])
(define_expand "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*absdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_expand "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negtd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_expand "abstd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*abstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_insn "*nabstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
;; Hardware support for decimal floating point operations.
(define_insn "extendddtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctqpq %0,%1"
[(set_attr "type" "dfp")])
;; The result of drdpq is an even/odd register pair with the converted
;; value in the even register and zero in the odd register.
;; FIXME: Avoid the register move by using a reload constraint to ensure
;; that the result is the first of the pair receiving the result of drdpq.
(define_insn "trunctddd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:TD 2 "=d"))]
"TARGET_DFP"
"drdpq %2,%1\;fmr %0,%2"
[(set_attr "type" "dfp")
(set_attr "length" "8")])
(define_insn "adddd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dadd %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "addtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"daddq %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "subdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dsub %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "subtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dsubq %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "muldd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dmul %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "multd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dmulq %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "divdd3"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"ddiv %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "divtd3"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"ddivq %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "*cmpdd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
(match_operand:DD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcmpu %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "*cmptd_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
(match_operand:TD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcmpuq %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
(define_insn "floatditd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcffixq %0,%1"
[(set_attr "type" "dfp")])
;; Convert a decimal64 to a decimal64 whose value is an integer.
;; This is the first stage of converting it to an integer type.
(define_insn "ftruncdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drintn. 0,%0,%1,1"
[(set_attr "type" "dfp")])
;; Convert a decimal64 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.
(define_insn "fixdddi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctfix %0,%1"
[(set_attr "type" "dfp")])
;; Convert a decimal128 to a decimal128 whose value is an integer.
;; This is the first stage of converting it to an integer type.
(define_insn "ftrunctd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
(fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drintnq. 0,%0,%1,1"
[(set_attr "type" "dfp")])
;; Convert a decimal128 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.
(define_insn "fixtddi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctfixq %0,%1"
[(set_attr "type" "dfp")])
;; Decimal builtin support
(define_c_enum "unspec"
[UNSPEC_DDEDPD
UNSPEC_DENBCD
UNSPEC_DXEX
UNSPEC_DIEX
UNSPEC_DSCLI
UNSPEC_DTSTSFI
UNSPEC_DSCRI])
(define_code_iterator DFP_TEST [eq lt gt unordered])
(define_mode_iterator D64_D128 [DD TD])
(define_mode_attr dfp_suffix [(DD "")
(TD "q")])
(define_insn "dfp_ddedpd_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
UNSPEC_DDEDPD))]
"TARGET_DFP"
"ddedpd<dfp_suffix> %1,%0,%2"
[(set_attr "type" "dfp")])
(define_insn "dfp_denbcd_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
UNSPEC_DENBCD))]
"TARGET_DFP"
"denbcd<dfp_suffix> %1,%0,%2"
[(set_attr "type" "dfp")])
(define_insn "dfp_dxex_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
UNSPEC_DXEX))]
"TARGET_DFP"
"dxex<dfp_suffix> %0,%1"
[(set_attr "type" "dfp")])
(define_insn "dfp_diex_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
UNSPEC_DXEX))]
"TARGET_DFP"
"diex<dfp_suffix> %0,%1,%2"
[(set_attr "type" "dfp")])
(define_expand "dfptstsfi_<code>_<mode>"
[(set (match_dup 3)
(compare:CCFP
(unspec:D64_D128
[(match_operand:SI 1 "const_int_operand" "n")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
UNSPEC_DTSTSFI)
(match_dup 4)))
(set (match_operand:SI 0 "register_operand" "")
(DFP_TEST:SI (match_dup 3)
(const_int 0)))
]
"TARGET_P9_MISC"
{
operands[3] = gen_reg_rtx (CCFPmode);
operands[4] = const0_rtx;
})
(define_insn "*dfp_sgnfcnc_<mode>"
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
UNSPEC_DTSTSFI)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_MISC"
{
/* If immediate operand is greater than 63, it will behave as if
the value had been 63. The code generator does not support
immediate operand values greater than 63. */
if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
operands[1] = GEN_INT (63);
return "dtstsfi<dfp_suffix> %0,%1,%2";
}
[(set_attr "type" "fp")])
(define_insn "dfp_dscli_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_DSCLI))]
"TARGET_DFP"
"dscli<dfp_suffix> %0,%1,%2"
[(set_attr "type" "dfp")])
(define_insn "dfp_dscri_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_DSCRI))]
"TARGET_DFP"
"dscri<dfp_suffix> %0,%1,%2"
[(set_attr "type" "dfp")])

541
gcc/config/powerpcspe/driver-powerpcspe.c
View file

@ -1,541 +0,0 @@
/* Subroutines for the gcc driver.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <stdlib.h>
#ifdef _AIX
# include <sys/systemcfg.h>
#endif
#ifdef __linux__
# include <link.h>
#endif
#if defined (__APPLE__) || (__FreeBSD__)
# include <sys/types.h>
# include <sys/sysctl.h>
#endif
const char *host_detect_local_cpu (int argc, const char **argv);
#if GCC_VERSION >= 0
/* Returns parameters that describe L1_ASSOC associative cache of size
L1_SIZEKB with lines of size L1_LINE, and L2_SIZEKB. */
static char *
describe_cache (unsigned l1_sizekb, unsigned l1_line,
unsigned l1_assoc ATTRIBUTE_UNUSED, unsigned l2_sizekb)
{
char l1size[1000], line[1000], l2size[1000];
/* At the moment, gcc middle-end does not use the information about the
associativity of the cache. */
sprintf (l1size, "--param l1-cache-size=%u", l1_sizekb);
sprintf (line, "--param l1-cache-line-size=%u", l1_line);
sprintf (l2size, "--param l2-cache-size=%u", l2_sizekb);
return concat (l1size, " ", line, " ", l2size, " ", NULL);
}
#ifdef __APPLE__
/* Returns the description of caches on Darwin. */
static char *
detect_caches_darwin (void)
{
unsigned l1_sizekb, l1_line, l1_assoc, l2_sizekb;
size_t len = 4;
static int l1_size_name[2] = { CTL_HW, HW_L1DCACHESIZE };
static int l1_line_name[2] = { CTL_HW, HW_CACHELINE };
static int l2_size_name[2] = { CTL_HW, HW_L2CACHESIZE };
sysctl (l1_size_name, 2, &l1_sizekb, &len, NULL, 0);
sysctl (l1_line_name, 2, &l1_line, &len, NULL, 0);
sysctl (l2_size_name, 2, &l2_sizekb, &len, NULL, 0);
l1_assoc = 0;
return describe_cache (l1_sizekb / 1024, l1_line, l1_assoc,
l2_sizekb / 1024);
}
static const char *
detect_processor_darwin (void)
{
unsigned int proc;
size_t len = 4;
sysctlbyname ("hw.cpusubtype", &proc, &len, NULL, 0);
if (len > 0)
switch (proc)
{
case 1:
return "601";
case 2:
return "602";
case 3:
return "603";
case 4:
case 5:
return "603e";
case 6:
return "604";
case 7:
return "604e";
case 8:
return "620";
case 9:
return "750";
case 10:
return "7400";
case 11:
return "7450";
case 100:
return "970";
default:
return "powerpc";
}
return "powerpc";
}
#endif /* __APPLE__ */
#ifdef __FreeBSD__
/* Returns the description of caches on FreeBSD PPC. */
static char *
detect_caches_freebsd (void)
{
unsigned l1_sizekb, l1_line, l1_assoc, l2_sizekb;
size_t len = 4;
/* Currently, as of FreeBSD-7.0, there is only the cacheline_size
available via sysctl. */
sysctlbyname ("machdep.cacheline_size", &l1_line, &len, NULL, 0);
l1_sizekb = 32;
l1_assoc = 0;
l2_sizekb = 512;
return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
}
/* Currently returns default powerpc. */
static const char *
detect_processor_freebsd (void)
{
return "powerpc";
}
#endif /* __FreeBSD__ */
#ifdef __linux__
/* Returns AT_PLATFORM if present, otherwise generic PowerPC. */
static const char *
elf_platform (void)
{
int fd;
fd = open ("/proc/self/auxv", O_RDONLY);
if (fd != -1)
{
char buf[1024];
ElfW(auxv_t) *av;
ssize_t n;
n = read (fd, buf, sizeof (buf));
close (fd);
if (n > 0)
{
for (av = (ElfW(auxv_t) *) buf; av->a_type != AT_NULL; ++av)
switch (av->a_type)
{
case AT_PLATFORM:
return (const char *) av->a_un.a_val;
default:
break;
}
}
}
return NULL;
}
/* Returns AT_DCACHEBSIZE if present, otherwise generic 32. */
static int
elf_dcachebsize (void)
{
int fd;
fd = open ("/proc/self/auxv", O_RDONLY);
if (fd != -1)
{
char buf[1024];
ElfW(auxv_t) *av;
ssize_t n;
n = read (fd, buf, sizeof (buf));
close (fd);
if (n > 0)
{
for (av = (ElfW(auxv_t) *) buf; av->a_type != AT_NULL; ++av)
switch (av->a_type)
{
case AT_DCACHEBSIZE:
return av->a_un.a_val;
default:
break;
}
}
}
return 32;
}
/* Returns the description of caches on Linux. */
static char *
detect_caches_linux (void)
{
unsigned l1_sizekb, l1_line, l1_assoc, l2_sizekb;
const char *platform;
platform = elf_platform ();
if (platform != NULL)
{
l1_line = 128;
if (platform[5] == '6')
/* POWER6 and POWER6x */
l1_sizekb = 64;
else
l1_sizekb = 32;
}
else
{
l1_line = elf_dcachebsize ();
l1_sizekb = 32;
}
l1_assoc = 0;
l2_sizekb = 512;
return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
}
static const char *
detect_processor_linux (void)
{
const char *platform;
platform = elf_platform ();
if (platform != NULL)
return platform;
else
return "powerpc";
}
#endif /* __linux__ */
#ifdef _AIX
/* Returns the description of caches on AIX. */
static char *
detect_caches_aix (void)
{
unsigned l1_sizekb, l1_line, l1_assoc, l2_sizekb;
l1_sizekb = _system_configuration.dcache_size / 1024;
l1_line = _system_configuration.dcache_line;
l1_assoc = _system_configuration.dcache_asc;
l2_sizekb = _system_configuration.L2_cache_size / 1024;
return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
}
/* Returns the processor implementation on AIX. */
static const char *
detect_processor_aix (void)
{
switch (_system_configuration.implementation)
{
case 0x0008:
return "601";
case 0x0020:
return "603";
case 0x0010:
return "604";
case 0x0040:
return "620";
case 0x0080:
return "630";
case 0x0100:
case 0x0200:
case 0x0400:
return "rs64";
case 0x0800:
return "power4";
case 0x2000:
if (_system_configuration.version == 0x0F0000)
return "power5";
else
return "power5+";
case 0x4000:
return "power6";
case 0x8000:
return "power7";
case 0x10000:
return "power8";
case 0x20000:
return "power9";
default:
return "powerpc";
}
}
#endif /* _AIX */
/*
* Array to map -mcpu=native names to the switches passed to the assembler.
* This list mirrors the specs in ASM_CPU_SPEC, and any changes made here
* should be made there as well.
*/
struct asm_name {
const char *cpu;
const char *asm_sw;
};
static const struct asm_name asm_names[] = {
#if defined (_AIX)
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
{ "power5+", "-mpwr5x" },
{ "power6", "-mpwr6" },
{ "power6x", "-mpwr6" },
{ "power7", "-mpwr7" },
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "powerpc", "-mppc" },
{ "rs64a", "-mppc" },
{ "603", "-m603" },
{ "603e", "-m603" },
{ "604", "-m604" },
{ "604e", "-m604" },
{ "620", "-m620" },
{ "630", "-m620" },
{ "970", "-m970" },
{ "G5", "-m970" },
{ NULL, "\
%{!maix64: \
%{mpowerpc64: -mppc64} \
%{maltivec: -m970} \
%{!maltivec: %{!mpowerpc64: %(asm_default)}}}" },
#else
{ "cell", "-mcell" },
{ "power3", "-mppc64" },
{ "power4", "-mpower4" },
{ "power5", "%(asm_cpu_power5)" },
{ "power5+", "%(asm_cpu_power5)" },
{ "power6", "%(asm_cpu_power6) -maltivec" },
{ "power6x", "%(asm_cpu_power6) -maltivec" },
{ "power7", "%(asm_cpu_power7)" },
{ "power8", "%(asm_cpu_power8)" },
{ "power9", "%(asm_cpu_power9)" },
{ "powerpc", "-mppc" },
{ "rs64a", "-mppc64" },
{ "401", "-mppc" },
{ "403", "-m403" },
{ "405", "-m405" },
{ "405fp", "-m405" },
{ "440", "-m440" },
{ "440fp", "-m440" },
{ "464", "-m440" },
{ "464fp", "-m440" },
{ "505", "-mppc" },
{ "601", "-m601" },
{ "602", "-mppc" },
{ "603", "-mppc" },
{ "603e", "-mppc" },
{ "ec603e", "-mppc" },
{ "604", "-mppc" },
{ "604e", "-mppc" },
{ "620", "-mppc64" },
{ "630", "-mppc64" },
{ "740", "-mppc" },
{ "750", "-mppc" },
{ "G3", "-mppc" },
{ "7400", "-mppc -maltivec" },
{ "7450", "-mppc -maltivec" },
{ "G4", "-mppc -maltivec" },
{ "801", "-mppc" },
{ "821", "-mppc" },
{ "823", "-mppc" },
{ "860", "-mppc" },
{ "970", "-mpower4 -maltivec" },
{ "G5", "-mpower4 -maltivec" },
{ "8540", "-me500" },
{ "8548", "-me500" },
{ "e300c2", "-me300" },
{ "e300c3", "-me300" },
{ "e500mc", "-me500mc" },
{ NULL, "\
%{mpowerpc64*: -mppc64} \
%{!mpowerpc64*: %(asm_default)}" },
#endif
};
/* This will be called by the spec parser in gcc.c when it sees
a %:local_cpu_detect(args) construct. Currently it will be called
with either "arch" or "tune" as argument depending on if -march=native
or -mtune=native is to be substituted.
Additionally it will be called with "asm" to select the appropriate flags
for the assembler.
It returns a string containing new command line parameters to be
put at the place of the above two options, depending on what CPU
this is executed.
ARGC and ARGV are set depending on the actual arguments given
in the spec. */
const char *
host_detect_local_cpu (int argc, const char **argv)
{
const char *cpu = NULL;
const char *cache = "";
const char *options = "";
bool arch;
bool assembler;
size_t i;
if (argc < 1)
return NULL;
arch = strcmp (argv[0], "cpu") == 0;
assembler = (!arch && strcmp (argv[0], "asm") == 0);
if (!arch && !assembler && strcmp (argv[0], "tune"))
return NULL;
if (! assembler)
{
#if defined (_AIX)
cache = detect_caches_aix ();
#elif defined (__APPLE__)
cache = detect_caches_darwin ();
#elif defined (__FreeBSD__)
cache = detect_caches_freebsd ();
/* FreeBSD PPC does not provide any cache information yet. */
cache = "";
#elif defined (__linux__)
cache = detect_caches_linux ();
/* PPC Linux does not provide any cache information yet. */
cache = "";
#else
cache = "";
#endif
}
#if defined (_AIX)
cpu = detect_processor_aix ();
#elif defined (__APPLE__)
cpu = detect_processor_darwin ();
#elif defined (__FreeBSD__)
cpu = detect_processor_freebsd ();
#elif defined (__linux__)
cpu = detect_processor_linux ();
#else
cpu = "powerpc";
#endif
if (assembler)
{
for (i = 0; i < sizeof (asm_names) / sizeof (asm_names[0]); i++)
{
if (!asm_names[i].cpu || !strcmp (asm_names[i].cpu, cpu))
return asm_names[i].asm_sw;
}
return NULL;
}
return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
}
#else /* GCC_VERSION */
/* If we aren't compiling with GCC we just provide a minimal
default value. */
const char *
host_detect_local_cpu (int argc, const char **argv)
{
const char *cpu;
bool arch;
if (argc < 1)
return NULL;
arch = strcmp (argv[0], "cpu") == 0;
if (!arch && strcmp (argv[0], "tune"))
return NULL;
if (arch)
cpu = "powerpc";
return concat ("-m", argv[0], "=", cpu, NULL);
}
#endif /* GCC_VERSION */

193
gcc/config/powerpcspe/e300c2c3.md
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@ -1,193 +0,0 @@
;; Pipeline description for Motorola PowerPC e300c3 core.
;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
;; We don't simulate general issue queue (GIC). If we have SU insn
;; and then SU1 insn, they can not be issued on the same cycle
;; (although SU1 insn and then SU insn can be issued) because the SU
;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
;; multipass insn scheduling will find the situation and issue the SU1
;; insn and then the SU insn.
(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
;; We could describe completion buffers slots in combination with the
;; retirement units and the order of completion but the result
;; automaton would behave in the same way because we can not describe
;; real latency time with taking in order completion into account.
;; Actually we could define the real latency time by querying reserved
;; automaton units but the current scheduler uses latency time before
;; issuing insns and making any reservations.
;;
;; So our description is aimed to achieve a insn schedule in which the
;; insns would not wait in the completion buffer.
(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
;; Branch unit:
(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
;; IU:
(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
;; IU: This used to describe non-pipelined division.
(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
;; SRU:
(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
;; Here we simplified LSU unit description not describing the stages.
(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
;; FPU:
(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
;; The following units are used to make automata deterministic
(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
;; Some useful abbreviations.
(define_reservation "ppce300c3_decode"
"ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
(define_reservation "ppce300c3_issue"
"ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
(define_reservation "ppce300c3_retire"
"ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
(define_reservation "ppce300c3_iu_stage0"
"ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
+ppce300c3_retire")
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
(and (ior (eq_attr "type" "integer,insert,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppce300c3_branch" 1
(and (eq_attr "type" "jmpreg,branch")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
;; Multiply is non-pipelined but can be executed in any IU
(define_insn_reservation "ppce300c3_multiply" 2
(and (eq_attr "type" "mul")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
ppce300c3_iu_stage0+ppce300c3_retire")
;; Divide. We use the average latency time here. We omit reserving a
;; retire unit because of the result automata will be huge.
(define_insn_reservation "ppce300c3_divide" 20
(and (eq_attr "type" "div")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
ppce300c3_mu_div*19")
;; CR logical
(define_insn_reservation "ppce300c3_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mfcr
(define_insn_reservation "ppce300c3_mfcr" 1
(and (eq_attr "type" "mfcr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mtcrf
(define_insn_reservation "ppce300c3_mtcrf" 1
(and (eq_attr "type" "mtcr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Mtjmpr
(define_insn_reservation "ppce300c3_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
;; Float point instructions
(define_insn_reservation "ppce300c3_fpcompare" 3
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fp" 3
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
(define_insn_reservation "ppce300c3_dmul" 4
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
; Divides are not pipelined
(define_insn_reservation "ppce300c3_sdiv" 18
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
(define_insn_reservation "ppce300c3_ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
;; Loads
(define_insn_reservation "ppce300c3_load" 2
(and (eq_attr "type" "load")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpload" 2
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
;; Stores.
(define_insn_reservation "ppce300c3_store" 2
(and (eq_attr "type" "store")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
(define_insn_reservation "ppce300c3_fpstore" 2
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce300c3"))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")

45
gcc/config/powerpcspe/e500.h
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@ -1,45 +0,0 @@
/* Enable E500 support.
Copyright (C) 2003-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_SPE_ABI
#undef TARGET_SPE
#undef TARGET_FPRS
#undef TARGET_E500_SINGLE
#undef TARGET_E500_DOUBLE
#undef CHECK_E500_OPTIONS
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_FPRS (rs6000_float_gprs == 0)
#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
#define CHECK_E500_OPTIONS \
do { \
if (TARGET_SPE || TARGET_SPE_ABI \
|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
{ \
if (TARGET_ALTIVEC) \
error ("AltiVec and SPE instructions cannot coexist"); \
if (TARGET_VSX) \
error ("VSX and SPE instructions cannot coexist"); \
if (TARGET_64BIT) \
error ("64-bit SPE not supported"); \
if (TARGET_HARD_FLOAT && TARGET_FPRS) \
error ("E500 and FPRs not supported"); \
} \
} while (0)

198
gcc/config/powerpcspe/e500mc.md
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@ -1,198 +0,0 @@
;; Pipeline description for Motorola PowerPC e500mc core.
;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e500mc 32-bit SU(2), LSU, FPU, BPU
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; FP is half clocked, timings of other instructions are as in the e500v2.
(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
;; SU.
(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
;; MU.
(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
;; Non-pipelined division.
(define_cpu_unit "e500mc_mu_div" "e500mc_long")
;; LSU.
(define_cpu_unit "e500mc_lsu" "e500mc_most")
;; FPU.
(define_cpu_unit "e500mc_fpu" "e500mc_most")
;; Branch unit.
(define_cpu_unit "e500mc_bu" "e500mc_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
;; Some useful abbreviations.
(define_reservation "e500mc_decode"
"e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
(define_reservation "e500mc_issue"
"e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
(define_reservation "e500mc_retire"
"e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
(define_reservation "e500mc_su_stage0"
"e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
(and (eq_attr "type" "integer,add,logical,insert,cmp,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire,\
e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Multiply.
(define_insn_reservation "e500mc_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc_divide" 14
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
e500mc_mu_div*13")
;; Branch.
(define_insn_reservation "e500mc_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_bu,e500mc_retire")
;; CR logical.
(define_insn_reservation "e500mc_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_bu,e500mc_retire")
;; Mfcr.
(define_insn_reservation "e500mc_mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtcrf.
(define_insn_reservation "e500mc_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtjmpr.
(define_insn_reservation "e500mc_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Brinc.
(define_insn_reservation "e500mc_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Loads.
(define_insn_reservation "e500mc_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
;; Stores.
(define_insn_reservation "e500mc_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
;; The following ignores the retire unit to avoid a large automata.
;; Simple FP.
(define_insn_reservation "e500mc_simple_float" 8
(and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
;; FP.
(define_insn_reservation "e500mc_float" 8
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
(define_insn_reservation "e500mc_fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
(define_insn_reservation "e500mc_dmul" 10
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu")
;; FP divides are not pipelined.
(define_insn_reservation "e500mc_sdiv" 36
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
(define_insn_reservation "e500mc_ddiv" 66
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")

200
gcc/config/powerpcspe/e500mc64.md
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@ -1,200 +0,0 @@
;; Pipeline description for Freescale PowerPC e500mc64 core.
;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e500mc64 64-bit SU(2), LSU, FPU, BPU
;; Max issue 3 insns/clock cycle (includes 1 branch)
(define_automaton "e500mc64_most,e500mc64_long,e500mc64_retire")
(define_cpu_unit "e500mc64_decode_0,e500mc64_decode_1" "e500mc64_most")
(define_cpu_unit "e500mc64_issue_0,e500mc64_issue_1" "e500mc64_most")
(define_cpu_unit "e500mc64_retire_0,e500mc64_retire_1" "e500mc64_retire")
;; SU.
(define_cpu_unit "e500mc64_su0_stage0,e500mc64_su1_stage0" "e500mc64_most")
;; MU.
(define_cpu_unit "e500mc64_mu_stage0,e500mc64_mu_stage1" "e500mc64_most")
(define_cpu_unit "e500mc64_mu_stage2,e500mc64_mu_stage3" "e500mc64_most")
;; Non-pipelined division.
(define_cpu_unit "e500mc64_mu_div" "e500mc64_long")
;; LSU.
(define_cpu_unit "e500mc64_lsu" "e500mc64_most")
;; FPU.
(define_cpu_unit "e500mc64_fpu" "e500mc64_most")
;; Branch unit.
(define_cpu_unit "e500mc64_bu" "e500mc64_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e500mc64_decode_0" "e500mc64_most")
(define_cpu_unit "present_e500mc64_issue_0" "e500mc64_most")
(define_cpu_unit "present_e500mc64_retire_0" "e500mc64_retire")
(define_cpu_unit "present_e500mc64_su0_stage0" "e500mc64_most")
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_e500mc64_decode_0" "e500mc64_decode_0")
(presence_set "present_e500mc64_issue_0" "e500mc64_issue_0")
(presence_set "present_e500mc64_retire_0" "e500mc64_retire_0")
(presence_set "present_e500mc64_su0_stage0" "e500mc64_su0_stage0")
;; Some useful abbreviations.
(define_reservation "e500mc64_decode"
"e500mc64_decode_0|e500mc64_decode_1+present_e500mc64_decode_0")
(define_reservation "e500mc64_issue"
"e500mc64_issue_0|e500mc64_issue_1+present_e500mc64_issue_0")
(define_reservation "e500mc64_retire"
"e500mc64_retire_0|e500mc64_retire_1+present_e500mc64_retire_0")
(define_reservation "e500mc64_su_stage0"
"e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
(and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
(define_insn_reservation "e500mc64_delayed" 2
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
(define_insn_reservation "e500mc64_two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Multiply.
(define_insn_reservation "e500mc64_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc64_divide" 14
(and (eq_attr "type" "div")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
e500mc64_mu_div*13")
;; Branch.
(define_insn_reservation "e500mc64_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_bu,e500mc64_retire")
;; CR logical.
(define_insn_reservation "e500mc64_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_bu,e500mc64_retire")
;; Mfcr.
(define_insn_reservation "e500mc64_mfcr" 4
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0,e500mc64_su1_stage0*3+e500mc64_retire")
;; Mtcrf.
(define_insn_reservation "e500mc64_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0+e500mc64_retire")
;; Mtjmpr.
(define_insn_reservation "e500mc64_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Brinc.
(define_insn_reservation "e500mc64_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
;; Loads.
(define_insn_reservation "e500mc64_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
;; Stores.
(define_insn_reservation "e500mc64_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
(define_insn_reservation "e500mc64_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
;; The following ignores the retire unit to avoid a large automata.
;; FP.
(define_insn_reservation "e500mc64_float" 7
(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu")
; "e500mc64_decode,e500mc64_issue+e500mc64_fpu,nothing*5,e500mc64_retire")
;; FP divides are not pipelined.
(define_insn_reservation "e500mc64_sdiv" 20
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*19")
(define_insn_reservation "e500mc64_ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34")

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@ -1,190 +0,0 @@
;; Pipeline description for Freescale PowerPC e5500 core.
;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
;; Max issue 3 insns/clock cycle (includes 1 branch)
(define_automaton "e5500_most,e5500_long")
(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
;; SFX.
(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
;; CFX.
(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
;; Non-pipelined division.
(define_cpu_unit "e5500_cfx_div" "e5500_long")
;; LSU.
(define_cpu_unit "e5500_lsu" "e5500_most")
;; FPU.
(define_cpu_unit "e5500_fpu" "e5500_long")
;; BU.
(define_cpu_unit "e5500_bu" "e5500_most")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e5500_decode_0" "e5500_most")
(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
(presence_set "present_e5500_decode_0" "e5500_decode_0")
(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
;; Some useful abbreviations.
(define_reservation "e5500_decode"
"e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
(define_reservation "e5500_sfx"
"e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
(and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_delayed" 2
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx*2")
(define_insn_reservation "e5500_two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
(define_insn_reservation "e5500_three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
;; SFX - Mfcr.
(define_insn_reservation "e5500_mfcr" 4
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx_0*4")
;; SFX - Mtcrf.
(define_insn_reservation "e5500_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx_0")
;; SFX - Mtjmpr.
(define_insn_reservation "e5500_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
;; CFX - Multiply.
(define_insn_reservation "e5500_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
(define_insn_reservation "e5500_multiply_i" 5
(and (eq_attr "type" "mul")
(ior (eq_attr "dot" "yes")
(eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,\
e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
;; CFX - Divide.
(define_insn_reservation "e5500_divide" 16
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*15")
(define_insn_reservation "e5500_divide_d" 26
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
e5500_cfx_div*25")
;; LSU - Loads.
(define_insn_reservation "e5500_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
;; LSU - Stores.
(define_insn_reservation "e5500_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
(define_insn_reservation "e5500_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_lsu")
;; FP.
(define_insn_reservation "e5500_float" 7
(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu")
(define_insn_reservation "e5500_sdiv" 20
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu*20")
(define_insn_reservation "e5500_ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_fpu*35")
;; BU.
(define_insn_reservation "e5500_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_bu")
;; BU - CR logical.
(define_insn_reservation "e5500_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_bu")

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@ -1,228 +0,0 @@
;; Pipeline description for Freescale PowerPC e6500 core.
;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;
;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
;; Max issue 3 insns/clock cycle (includes 1 branch)
(define_automaton "e6500_most,e6500_long,e6500_vec")
(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
;; SFX.
(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
;; CFX.
(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
;; Non-pipelined division.
(define_cpu_unit "e6500_cfx_div" "e6500_long")
;; LSU.
(define_cpu_unit "e6500_lsu" "e6500_most")
;; FPU.
(define_cpu_unit "e6500_fpu" "e6500_long")
;; BU.
(define_cpu_unit "e6500_bu" "e6500_most")
;; Altivec unit
(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e6500_decode_0" "e6500_most")
(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
(presence_set "present_e6500_decode_0" "e6500_decode_0")
(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
;; Some useful abbreviations.
(define_reservation "e6500_decode"
"e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
(define_reservation "e6500_sfx"
"e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
(and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_delayed" 2
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx*2")
(define_insn_reservation "e6500_two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
(define_insn_reservation "e6500_three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
;; SFX - Mfcr.
(define_insn_reservation "e6500_mfcr" 4
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx_0*4")
;; SFX - Mtcrf.
(define_insn_reservation "e6500_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx_0")
;; SFX - Mtjmpr.
(define_insn_reservation "e6500_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
;; CFX - Multiply.
(define_insn_reservation "e6500_multiply" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
(define_insn_reservation "e6500_multiply_i" 5
(and (eq_attr "type" "mul")
(ior (eq_attr "dot" "yes")
(eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,\
e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
;; CFX - Divide.
(define_insn_reservation "e6500_divide" 16
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
e6500_cfx_div*15")
(define_insn_reservation "e6500_divide_d" 26
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
e6500_cfx_div*25")
;; LSU - Loads.
(define_insn_reservation "e6500_load" 3
(and (eq_attr "type" "load,load_l,sync")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpload" 4
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_vecload" 4
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
;; LSU - Stores.
(define_insn_reservation "e6500_store" 3
(and (eq_attr "type" "store,store_c")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_fpstore" 3
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
(define_insn_reservation "e6500_vecstore" 4
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_lsu")
;; FP.
(define_insn_reservation "e6500_float" 7
(and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_fpu")
(define_insn_reservation "e6500_sdiv" 20
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_fpu*20")
(define_insn_reservation "e6500_ddiv" 35
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_fpu*35")
;; BU.
(define_insn_reservation "e6500_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_bu")
;; BU - CR logical.
(define_insn_reservation "e6500_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_bu")
;; VSFX.
(define_insn_reservation "e6500_vecsimple" 1
(and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
;; VCFX.
(define_insn_reservation "e6500_veccomplex" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
;; VFPU.
(define_insn_reservation "e6500_vecfloat" 6
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")
;; VPERM.
(define_insn_reservation "e6500_vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vecperm")

41
gcc/config/powerpcspe/eabi.h
View file

@ -1,41 +0,0 @@
/* Core target definitions for GNU compiler
for IBM RS/6000 PowerPC targeted to embedded ELF systems.
Copyright (C) 1995-2018 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Add -meabi to target flags. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_EABI
/* Invoke an initializer function to set up the GOT. */
#define NAME__MAIN "__eabi"
#define INVOKE__main
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("PPC"); \
builtin_define ("__embedded__"); \
builtin_assert ("system=embedded"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
while (0)

27
gcc/config/powerpcspe/eabialtivec.h
View file

@ -1,27 +0,0 @@
/* Core target definitions for GNU compiler
for PowerPC targeted systems with AltiVec support.
Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Add -meabi and -maltivec to target flags. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1

51
gcc/config/powerpcspe/eabisim.h
View file

@ -1,51 +0,0 @@
/* Support for GCC on simulated PowerPC systems targeted to embedded ELF
systems.
Copyright (C) 1995-2018 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("PPC"); \
builtin_define ("__embedded__"); \
builtin_define ("__simulator__"); \
builtin_assert ("system=embedded"); \
builtin_assert ("system=simulator"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
while (0)
/* Make the simulator the default */
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "%(lib_sim)"
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "%(startfile_sim)"
#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "%(endfile_sim)"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "%(link_start_sim)"
#undef LINK_OS_DEFAULT_SPEC
#define LINK_OS_DEFAULT_SPEC "%(link_os_sim)"

26
gcc/config/powerpcspe/eabispe.h
View file

@ -1,26 +0,0 @@
/* Core target definitions for GNU compiler
for PowerPC embedded targeted systems with SPE support.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

79
gcc/config/powerpcspe/freebsd.h
View file

@ -1,79 +0,0 @@
/* Definitions for PowerPC running FreeBSD using the ELF format
Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Override the defaults, which exist to force the proper definition. */
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_freebsd)"
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "%(startfile_freebsd)"
#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "%(endfile_freebsd)"
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "%(lib_freebsd)"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "%(link_start_freebsd)"
#undef LINK_OS_DEFAULT_SPEC
#define LINK_OS_DEFAULT_SPEC "%(link_os_freebsd)"
/* XXX: This is wrong for many platforms in sysv4.h.
We should work on getting that definition fixed. */
#undef LINK_SHLIB_SPEC
#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
/************************[ Target stuff ]***********************************/
/* Define the actual types of some ANSI-mandated types.
Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.c,
c-common.c, and config/<arch>/<arch>.h. */
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
/* rs6000.h gets this wrong for FreeBSD. We use the GCC defaults instead. */
#undef WCHAR_TYPE
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
/* Override rs6000.h definition. */
#undef ASM_APP_ON
#define ASM_APP_ON "#APP\n"
/* Override rs6000.h definition. */
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
/* We don't need to generate entries in .fixup, except when
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
(rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING
#define POWERPC_FREEBSD

433
gcc/config/powerpcspe/freebsd64.h
View file

@ -1,433 +0,0 @@
/* Definitions for 64-bit PowerPC running FreeBSD using the ELF format
Copyright (C) 2012-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Override the defaults, which exist to force the proper definition. */
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __powerpc64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
#undef TARGET_AIX
#define TARGET_AIX TARGET_64BIT
#ifdef HAVE_LD_NO_DOT_SYMS
/* New ABI uses a local sym for the function entry point. */
extern int dot_symbols;
#undef DOT_SYMBOLS
#define DOT_SYMBOLS dot_symbols
#endif
#define TARGET_USES_LINUX64_OPT 1
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
/* Until now the 970 is the only Processor where FreeBSD 64-bit runs on. */
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER4
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4
/* We don't need to generate entries in .fixup, except when
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
(rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#undef RS6000_ABI_NAME
#define RS6000_ABI_NAME "freebsd"
#define INVALID_64BIT "-m%s not supported in this configuration"
#define INVALID_32BIT INVALID_64BIT
/* Use LINUX64 instead of FREEBSD64 for compat with e.g. sysv4le.h */
#ifdef LINUX64_DEFAULT_ABI_ELFv2
#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1)
#else
#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2)
#endif
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
do \
{ \
if (!global_options_set.x_rs6000_alignment_flags) \
rs6000_alignment_flags = MASK_ALIGN_NATURAL; \
if (TARGET_64BIT) \
{ \
if (DEFAULT_ABI != ABI_AIX) \
{ \
rs6000_current_abi = ABI_AIX; \
error (INVALID_64BIT, "call"); \
} \
dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \
if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
{ \
rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
error (INVALID_64BIT, "relocatable"); \
} \
if (ELFv2_ABI_CHECK) \
{ \
rs6000_current_abi = ABI_ELFv2; \
if (dot_symbols) \
error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \
} \
if (rs6000_isa_flags & OPTION_MASK_EABI) \
{ \
rs6000_isa_flags &= ~OPTION_MASK_EABI; \
error (INVALID_64BIT, "eabi"); \
} \
if (TARGET_PROTOTYPE) \
{ \
target_prototype = 0; \
error (INVALID_64BIT, "prototype"); \
} \
if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
error ("-m64 requires a PowerPC64 cpu"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
else \
{ \
if (!global_options_set.x_rs6000_current_cmodel) \
SET_CMODEL (CMODEL_MEDIUM); \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
TARGET_NO_FP_IN_TOC = 0; \
TARGET_NO_SUM_IN_TOC = 0; \
} \
} \
} \
} \
while (0)
#undef ASM_DEFAULT_SPEC
#undef ASM_SPEC
#undef LINK_OS_FREEBSD_SPEC
#define ASM_DEFAULT_SPEC "-mppc%{!m32:64}"
#define ASM_SPEC "%{m32:%(asm_spec32)}%{!m32:%(asm_spec64)} %(asm_spec_common)"
#define LINK_OS_FREEBSD_SPEC "%{m32:%(link_os_freebsd_spec32)}%{!m32:%(link_os_freebsd_spec64)}"
#define ASM_SPEC32 "-a32 \
%{mrelocatable} %{mrelocatable-lib} %{" FPIE_OR_FPIC_SPEC ":-K PIC} \
%{memb} %{!memb: %{msdata=eabi: -memb}} \
%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
%{mcall-freebsd: -mbig} \
%{mcall-i960-old: -mlittle} \
%{mcall-linux: -mbig} \
%{mcall-gnu: -mbig} \
%{mcall-netbsd: -mbig} \
}}}}"
#define ASM_SPEC64 "-a64"
#define ASM_SPEC_COMMON "%(asm_cpu) \
%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \
%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian}"
#undef SUBSUBTARGET_EXTRA_SPECS
#define SUBSUBTARGET_EXTRA_SPECS \
{ "asm_spec_common", ASM_SPEC_COMMON }, \
{ "asm_spec32", ASM_SPEC32 }, \
{ "asm_spec64", ASM_SPEC64 }, \
{ "link_os_freebsd_spec32", LINK_OS_FREEBSD_SPEC32 }, \
{ "link_os_freebsd_spec64", LINK_OS_FREEBSD_SPEC64 },
#define LINK_OS_FREEBSD_SPEC_DEF "\
%{p:%nconsider using `-pg' instead of `-p' with gprof(1)} \
%{v:-V} \
%{assert*} %{R*} %{rpath*} %{defsym*} \
%{shared:-Bshareable %{h*} %{soname*}} \
%{!shared: \
%{!static: \
%{rdynamic: -export-dynamic} \
%{!dynamic-linker:-dynamic-linker " FBSD_DYNAMIC_LINKER "}} \
%{static:-Bstatic}} \
%{symbolic:-Bsymbolic}"
#define LINK_OS_FREEBSD_SPEC32 "-melf32ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF
#define LINK_OS_FREEBSD_SPEC64 "-melf64ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "m64" }
/* PowerPC-64 FreeBSD increases natural record alignment to doubleword if
the first field is an FP double, only if in power alignment mode. */
#undef ROUND_TYPE_ALIGN
#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
((TARGET_64BIT \
&& (TREE_CODE (STRUCT) == RECORD_TYPE \
|| TREE_CODE (STRUCT) == UNION_TYPE \
|| TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
&& TARGET_ALIGN_NATURAL == 0) \
? rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED) \
: MAX ((COMPUTED), (SPECIFIED)))
/* Use the default for compiling target libs. */
#ifdef IN_TARGET_LIBS
#undef TARGET_ALIGN_NATURAL
#define TARGET_ALIGN_NATURAL 1
#endif
/* Indicate that jump tables go in the text section. */
#undef JUMP_TABLES_IN_TEXT_SECTION
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_64BIT
/* The linux ppc64 ABI isn't explicit on whether aggregates smaller
than a doubleword should be padded upward or downward. You could
reasonably assume that they follow the normal rules for structure
layout treating the parameter area as any other block of memory,
then map the reg param area to registers. i.e. pad upward.
Setting both of the following defines results in this behavior.
Setting just the first one will result in aggregates that fit in a
doubleword being padded downward, and others being padded upward.
Not a bad idea as this results in struct { int x; } being passed
the same way as an int. */
#define AGGREGATE_PADDING_FIXED TARGET_64BIT
#define AGGREGATES_PAD_UPWARD_ALWAYS 0
/* Specify padding for the last element of a block move between
registers and memory. FIRST is nonzero if this is the only
element. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE))
/* FreeBSD doesn't support saving and restoring 64-bit regs with a 32-bit
kernel. This is supported when running on a 64-bit kernel with
COMPAT_FREEBSD32, but tell GCC it isn't so that our 32-bit binaries
are compatible. */
#define OS_MISSING_POWERPC64 !TARGET_64BIT
#undef FBSD_TARGET_CPU_CPP_BUILTINS
#define FBSD_TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define ("__PPC__"); \
builtin_define ("__ppc__"); \
builtin_define ("__powerpc__"); \
if (TARGET_64BIT) \
{ \
builtin_define ("__arch64__"); \
builtin_define ("__LP64__"); \
builtin_define ("__PPC64__"); \
builtin_define ("__powerpc64__"); \
builtin_assert ("cpu=powerpc64"); \
builtin_assert ("machine=powerpc64"); \
} \
else \
{ \
builtin_define_std ("PPC"); \
builtin_define_std ("powerpc"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
} \
while (0)
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_freebsd)"
#undef CPP_OS_FREEBSD_SPEC
#define CPP_OS_FREEBSD_SPEC ""
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "%(startfile_freebsd)"
#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "%(endfile_freebsd)"
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "%(lib_freebsd)"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "%(link_start_freebsd)"
#undef LINK_OS_DEFAULT_SPEC
#define LINK_OS_DEFAULT_SPEC "%(link_os_freebsd)"
/* XXX: This is wrong for many platforms in sysv4.h.
We should work on getting that definition fixed. */
#undef LINK_SHLIB_SPEC
#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
/************************[ Target stuff ]***********************************/
/* Define the actual types of some ANSI-mandated types.
Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.c,
c-common.c, and config/<arch>/<arch>.h. */
#undef SIZE_TYPE
#define SIZE_TYPE (TARGET_64BIT ? "long unsigned int" : "unsigned int")
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int")
/* rs6000.h gets this wrong for FreeBSD. We use the GCC defaults instead. */
#undef WCHAR_TYPE
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
/* Override rs6000.h definition. */
#undef ASM_APP_ON
#define ASM_APP_ON "#APP\n"
/* Override rs6000.h definition. */
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
/* Function profiling bits */
#undef RS6000_MCOUNT
#define RS6000_MCOUNT "_mcount"
#define PROFILE_HOOK(LABEL) \
do { if (TARGET_64BIT) output_profile_hook (LABEL); } while (0)
/* _init and _fini functions are built from bits spread across many
object files, each potentially with a different TOC pointer. For
that reason, place a nop after the call so that the linker can
restore the TOC pointer if a TOC adjusting call stub is needed. */
#ifdef __powerpc64__
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n" \
" bl " #FUNC "\n" \
" nop\n" \
" .previous");
#endif
/* FP save and restore routines. */
#undef SAVE_FP_PREFIX
#define SAVE_FP_PREFIX (TARGET_64BIT ? "._savef" : "_savefpr_")
#undef SAVE_FP_SUFFIX
#define SAVE_FP_SUFFIX ""
#undef RESTORE_FP_PREFIX
#define RESTORE_FP_PREFIX (TARGET_64BIT ? "._restf" : "_restfpr_")
#undef RESTORE_FP_SUFFIX
#define RESTORE_FP_SUFFIX ""
/* Select a format to encode pointers in exception handling data. CODE
is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
true if the symbol may be affected by dynamic relocations. */
#undef ASM_PREFERRED_EH_DATA_FORMAT
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(TARGET_64BIT || flag_pic \
? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel \
| (TARGET_64BIT ? DW_EH_PE_udata8 : DW_EH_PE_sdata4)) \
: DW_EH_PE_absptr)
/* Static stack checking is supported by means of probes. */
#define STACK_CHECK_STATIC_BUILTIN 1
/* The default value isn't sufficient in 64-bit mode. */
#define STACK_CHECK_PROTECT (TARGET_64BIT ? 16 * 1024 : 12 * 1024)
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING
/* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */
#undef ADJUST_FIELD_ALIGN
#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
(rs6000_special_adjust_field_align_p ((TYPE), (COMPUTED)) \
? 128 \
: (TARGET_64BIT \
&& TARGET_ALIGN_NATURAL == 0 \
&& TYPE_MODE (strip_array_types (TYPE)) == DFmode) \
? MIN ((COMPUTED), 32) \
: (COMPUTED))
#undef TOC_SECTION_ASM_OP
#define TOC_SECTION_ASM_OP \
(TARGET_64BIT \
? "\t.section\t\".toc\",\"aw\"" \
: "\t.section\t\".got\",\"aw\"")
#undef MINIMAL_TOC_SECTION_ASM_OP
#define MINIMAL_TOC_SECTION_ASM_OP \
(TARGET_64BIT \
? "\t.section\t\".toc1\",\"aw\"" \
: (flag_pic \
? "\t.section\t\".got2\",\"aw\"" \
: "\t.section\t\".got1\",\"aw\""))
/* This is how to declare the size of a function. */
#undef ASM_DECLARE_FUNCTION_SIZE
#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
do \
{ \
if (!flag_inhibit_size_directive) \
{ \
fputs ("\t.size\t", (FILE)); \
if (TARGET_64BIT && DOT_SYMBOLS) \
putc ('.', (FILE)); \
assemble_name ((FILE), (FNAME)); \
fputs (",.-", (FILE)); \
rs6000_output_function_entry (FILE, FNAME); \
putc ('\n', (FILE)); \
} \
} \
while (0)
#undef ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE) \
(TARGET_TOC \
&& (GET_CODE (X) == SYMBOL_REF \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF) \
|| GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST_INT \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (GET_CODE (X) == CONST_DOUBLE \
&& ((TARGET_64BIT \
&& (TARGET_MINIMAL_TOC \
|| (SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
&& ! TARGET_NO_FP_IN_TOC))) \
|| (!TARGET_64BIT \
&& !TARGET_NO_FP_IN_TOC \
&& SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
&& BITS_PER_WORD == HOST_BITS_PER_INT)))))
/* Use --as-needed -lgcc_s for eh support. */
#ifdef HAVE_LD_AS_NEEDED
#define USE_LD_AS_NEEDED 1
#endif
#define POWERPC_FREEBSD

64
gcc/config/powerpcspe/genopt.sh
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@ -1,64 +0,0 @@
#!/bin/sh
# Generate powerpcspe-tables.opt from the list of CPUs in powerpcspe-cpus.def.
# Copyright (C) 2011-2018 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
cat <<EOF
; -*- buffer-read-only: t -*-
; Generated automatically by genopt.sh from powerpcspe-cpus.def.
; Copyright (C) 2011-2018 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Enum
Name(rs6000_cpu_opt_value) Type(int)
Known CPUs (for use with the -mcpu= and -mtune= options):
EnumValue
Enum(rs6000_cpu_opt_value) String(native) Value(RS6000_CPU_OPTION_NATIVE) DriverOnly
EOF
awk -F'[(, ]+' '
BEGIN {
value = 0
}
/^RS6000_CPU/ {
name = $2
gsub("\"", "", name)
print "EnumValue"
print "Enum(rs6000_cpu_opt_value) String(" name ") Value(" value ")"
print ""
value++
}' $1/powerpcspe-cpus.def

155
gcc/config/powerpcspe/host-darwin.c
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@ -1,155 +0,0 @@
/* Darwin/powerpc host-specific hook definitions.
Copyright (C) 2003-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "diagnostic.h"
#include <sys/ucontext.h>
#include "hosthooks.h"
#include "hosthooks-def.h"
#include "config/host-darwin.h"
static void segv_crash_handler (int);
static void segv_handler (int, siginfo_t *, void *);
static void darwin_rs6000_extra_signals (void);
#ifndef HAVE_DECL_SIGALTSTACK
/* This doesn't have a prototype in signal.h in 10.2.x and earlier,
fixed in later releases. */
extern int sigaltstack(const struct sigaltstack *, struct sigaltstack *);
#endif
/* The fields of the mcontext_t type have acquired underscores in later
OS versions. */
#ifdef HAS_MCONTEXT_T_UNDERSCORES
#define MC_FLD(x) __ ## x
#else
#define MC_FLD(x) x
#endif
#undef HOST_HOOKS_EXTRA_SIGNALS
#define HOST_HOOKS_EXTRA_SIGNALS darwin_rs6000_extra_signals
/* On Darwin/powerpc, hitting the stack limit turns into a SIGSEGV.
This code detects the difference between hitting the stack limit and
a true wild pointer dereference by looking at the instruction that
faulted; only a few kinds of instruction are used to access below
the previous bottom of the stack. */
static void
segv_crash_handler (int sig ATTRIBUTE_UNUSED)
{
internal_error ("Segmentation Fault (code)");
}
static void
segv_handler (int sig ATTRIBUTE_UNUSED,
siginfo_t *sip ATTRIBUTE_UNUSED,
void *scp)
{
ucontext_t *uc = (ucontext_t *)scp;
sigset_t sigset;
unsigned faulting_insn;
/* The fault might have happened when trying to run some instruction, in
which case the next line will segfault _again_. Handle this case. */
signal (SIGSEGV, segv_crash_handler);
sigemptyset (&sigset);
sigaddset (&sigset, SIGSEGV);
sigprocmask (SIG_UNBLOCK, &sigset, NULL);
faulting_insn = *(unsigned *)uc->uc_mcontext->MC_FLD(ss).MC_FLD(srr0);
/* Note that this only has to work for GCC, so we don't have to deal
with all the possible cases (GCC has no AltiVec code, for
instance). It's complicated because Darwin allows stores to
below the stack pointer, and the prologue code takes advantage of
this. */
if ((faulting_insn & 0xFFFF8000) == 0x94218000 /* stwu %r1, -xxx(%r1) */
|| (faulting_insn & 0xFC1F03FF) == 0x7C01016E /* stwux xxx, %r1, xxx */
|| (faulting_insn & 0xFC1F8000) == 0x90018000 /* stw xxx, -yyy(%r1) */
|| (faulting_insn & 0xFC1F8000) == 0xD8018000 /* stfd xxx, -yyy(%r1) */
|| (faulting_insn & 0xFC1F8000) == 0xBC018000 /* stmw xxx, -yyy(%r1) */)
{
char *shell_name;
fnotice (stderr, "Out of stack space.\n");
shell_name = getenv ("SHELL");
if (shell_name != NULL)
shell_name = strrchr (shell_name, '/');
if (shell_name != NULL)
{
static const char * shell_commands[][2] = {
{ "sh", "ulimit -S -s unlimited" },
{ "bash", "ulimit -S -s unlimited" },
{ "tcsh", "limit stacksize unlimited" },
{ "csh", "limit stacksize unlimited" },
/* zsh doesn't have "unlimited", this will work under the
default configuration. */
{ "zsh", "limit stacksize 32m" }
};
size_t i;
for (i = 0; i < ARRAY_SIZE (shell_commands); i++)
if (strcmp (shell_commands[i][0], shell_name + 1) == 0)
{
fnotice (stderr,
"Try running '%s' in the shell to raise its limit.\n",
shell_commands[i][1]);
}
}
if (global_dc->abort_on_error)
fancy_abort (__FILE__, __LINE__, __FUNCTION__);
exit (FATAL_EXIT_CODE);
}
fprintf (stderr, "[address=%08lx pc=%08x]\n",
uc->uc_mcontext->MC_FLD(es).MC_FLD(dar),
uc->uc_mcontext->MC_FLD(ss).MC_FLD(srr0));
internal_error ("Segmentation Fault");
exit (FATAL_EXIT_CODE);
}
static void
darwin_rs6000_extra_signals (void)
{
struct sigaction sact;
stack_t sigstk;
sigstk.ss_sp = (char*)xmalloc (SIGSTKSZ);
sigstk.ss_size = SIGSTKSZ;
sigstk.ss_flags = 0;
if (sigaltstack (&sigstk, NULL) < 0)
fatal_error (input_location, "While setting up signal stack: %m");
sigemptyset(&sact.sa_mask);
sact.sa_flags = SA_ONSTACK | SA_SIGINFO;
sact.sa_sigaction = segv_handler;
if (sigaction (SIGSEGV, &sact, 0) < 0)
fatal_error (input_location, "While setting up signal handler: %m");
}
const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;

32
gcc/config/powerpcspe/host-ppc64-darwin.c
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@ -1,32 +0,0 @@
/* ppc64-darwin host-specific hook definitions.
Copyright (C) 2006-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "hosthooks.h"
#include "hosthooks-def.h"
#include "config/host-darwin.h"
/* Darwin doesn't do anything special for ppc64 hosts; this file exists just
to include config/host-darwin.h. */
const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;

296
gcc/config/powerpcspe/htm.md
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@ -1,296 +0,0 @@
;; Hardware Transactional Memory (HTM) patterns.
;; Copyright (C) 2013-2018 Free Software Foundation, Inc.
;; Contributed by Peter Bergner <bergner@vnet.ibm.com>.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_constants
[(TFHAR_SPR 128)
(TFIAR_SPR 129)
(TEXASR_SPR 130)
(TEXASRU_SPR 131)
(MAX_HTM_OPERANDS 4)
])
;;
;; UNSPEC usage
;;
(define_c_enum "unspec"
[UNSPEC_HTM_FENCE
])
;;
;; UNSPEC_VOLATILE usage
;;
(define_c_enum "unspecv"
[UNSPECV_HTM_TABORT
UNSPECV_HTM_TABORTXC
UNSPECV_HTM_TABORTXCI
UNSPECV_HTM_TBEGIN
UNSPECV_HTM_TCHECK
UNSPECV_HTM_TEND
UNSPECV_HTM_TRECHKPT
UNSPECV_HTM_TRECLAIM
UNSPECV_HTM_TSR
UNSPECV_HTM_TTEST
UNSPECV_HTM_MFSPR
UNSPECV_HTM_MTSPR
])
(define_expand "tabort"
[(parallel
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
UNSPECV_HTM_TABORT))
(set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[2]) = 1;
})
(define_insn "*tabort"
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand:SI 0 "base_reg_operand" "b")]
UNSPECV_HTM_TABORT))
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort. %0"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tabort<wd>c"
[(parallel
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")]
UNSPECV_HTM_TABORTXC))
(set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[4]) = 1;
})
(define_insn "*tabort<wd>c"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")]
UNSPECV_HTM_TABORTXC))
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>c. %0,%1,%2"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tabort<wd>ci"
[(parallel
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand 2 "s5bit_cint_operand" "n")]
UNSPECV_HTM_TABORTXCI))
(set (match_dup 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[4] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[4]) = 1;
})
(define_insn "*tabort<wd>ci"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand 2 "s5bit_cint_operand" "n")]
UNSPECV_HTM_TABORTXCI))
(set (match_operand:BLK 4) (unspec:BLK [(match_dup 4)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabort<wd>ci. %0,%1,%2"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tbegin"
[(parallel
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TBEGIN))
(set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[2]) = 1;
})
(define_insn "*tbegin"
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TBEGIN))
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tbegin. %0"
[(set_attr "type" "htm")
(set_attr "length" "4")])
(define_expand "tcheck"
[(parallel
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
(set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[1]) = 1;
})
(define_insn "*tcheck"
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TCHECK))
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tcheck %0"
[(set_attr "type" "htm")
(set_attr "length" "4")])
(define_expand "tend"
[(parallel
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TEND))
(set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[2]) = 1;
})
(define_insn "*tend"
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TEND))
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tend. %0"
[(set_attr "type" "htm")
(set_attr "length" "4")])
(define_expand "trechkpt"
[(parallel
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
(set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[1]) = 1;
})
(define_insn "*trechkpt"
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TRECHKPT))
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"trechkpt."
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "treclaim"
[(parallel
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
UNSPECV_HTM_TRECLAIM))
(set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[2]) = 1;
})
(define_insn "*treclaim"
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
UNSPECV_HTM_TRECLAIM))
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"treclaim. %0"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "tsr"
[(parallel
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TSR))
(set (match_dup 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[2]) = 1;
})
(define_insn "*tsr"
[(set (match_operand:CC 1 "cc_reg_operand" "=x")
(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
UNSPECV_HTM_TSR))
(set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tsr. %0"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_expand "ttest"
[(parallel
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
(set (match_dup 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))])]
"TARGET_HTM"
{
operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[1]) = 1;
})
(define_insn "*ttest"
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_HTM_TTEST))
(set (match_operand:BLK 1) (unspec:BLK [(match_dup 1)] UNSPEC_HTM_FENCE))]
"TARGET_HTM"
"tabortwci. 0,1,0"
[(set_attr "type" "htmsimple")
(set_attr "length" "4")])
(define_insn "htm_mfspr_<mode>"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n")
(match_operand:GPR 2 "htm_spr_reg_operand" "")]
UNSPECV_HTM_MFSPR))]
"TARGET_HTM"
"mfspr %0,%1";
[(set_attr "type" "htm")
(set_attr "length" "4")])
(define_insn "htm_mtspr_<mode>"
[(set (match_operand:GPR 2 "htm_spr_reg_operand" "")
(unspec_volatile:GPR [(match_operand:GPR 0 "gpc_reg_operand" "r")
(match_operand 1 "u10bit_cint_operand" "n")]
UNSPECV_HTM_MTSPR))]
"TARGET_HTM"
"mtspr %1,%0";
[(set_attr "type" "htm")
(set_attr "length" "4")])

131
gcc/config/powerpcspe/htmintrin.h
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@ -1,131 +0,0 @@
/* Hardware Transactional Memory (HTM) intrinsics.
Copyright (C) 2013-2018 Free Software Foundation, Inc.
Contributed by Peter Bergner <bergner@vnet.ibm.com>.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef __HTM__
# error "HTM instruction set not enabled"
#endif /* __HTM__ */
#ifndef _HTMINTRIN_H
#define _HTMINTRIN_H
#include <stdint.h>
typedef uint64_t texasr_t;
typedef uint32_t texasru_t;
typedef uint32_t texasrl_t;
typedef uintptr_t tfiar_t;
typedef uintptr_t tfhar_t;
#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
#define _HTM_NONTRANSACTIONAL 0x0
#define _HTM_SUSPENDED 0x1
#define _HTM_TRANSACTIONAL 0x2
/* The following macros use the IBM bit numbering for BITNUM
as used in the ISA documentation. */
#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
(((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
(((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
#define _TEXASR_FAILURE_CODE(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
#define _TEXASRU_FAILURE_CODE(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
#define _TEXASR_DISALLOWED(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
#define _TEXASRU_DISALLOWED(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
#define _TEXASR_NESTING_OVERFLOW(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
#define _TEXASR_ABORT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
#define _TEXASRU_ABORT(TEXASRU) \
_TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
#define _TEXASR_SUSPENDED(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
#define _TEXASR_PRIVILEGE(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
#define _TEXASR_FAILURE_SUMMARY(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
#define _TEXASR_TFIAR_EXACT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
#define _TEXASR_ROT(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
_TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
#endif /* _HTMINTRIN_H */

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@ -1,214 +0,0 @@
/* XL compiler Hardware Transactional Memory (HTM) execution intrinsics.
Copyright (C) 2013-2018 Free Software Foundation, Inc.
Contributed by Peter Bergner <bergner@vnet.ibm.com>.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef __HTM__
# error "HTM instruction set not enabled"
#endif /* __HTM__ */
#ifndef _HTMXLINTRIN_H
#define _HTMXLINTRIN_H
#include <stdint.h>
#include <htmintrin.h>
#ifdef __cplusplus
extern "C" {
#endif
#define _TEXASR_PTR(TM_BUF) \
((texasr_t *)((TM_BUF)+0))
#define _TEXASRU_PTR(TM_BUF) \
((texasru_t *)((TM_BUF)+0))
#define _TEXASRL_PTR(TM_BUF) \
((texasrl_t *)((TM_BUF)+4))
#define _TFIAR_PTR(TM_BUF) \
((tfiar_t *)((TM_BUF)+8))
typedef char TM_buff_type[16];
/* Compatibility macro with s390. This macro can be used to determine
whether a transaction was successfully started from the __TM_begin()
and __TM_simple_begin() intrinsic functions below. */
#define _HTM_TBEGIN_STARTED 1
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_simple_begin (void)
{
if (__builtin_expect (__builtin_tbegin (0), 1))
return _HTM_TBEGIN_STARTED;
return 0;
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_begin (void* const TM_buff)
{
*_TEXASRL_PTR (TM_buff) = 0;
if (__builtin_expect (__builtin_tbegin (0), 1))
return _HTM_TBEGIN_STARTED;
#ifdef __powerpc64__
*_TEXASR_PTR (TM_buff) = __builtin_get_texasr ();
#else
*_TEXASRU_PTR (TM_buff) = __builtin_get_texasru ();
*_TEXASRL_PTR (TM_buff) = __builtin_get_texasr ();
#endif
*_TFIAR_PTR (TM_buff) = __builtin_get_tfiar ();
return 0;
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_end (void)
{
unsigned char status = _HTM_STATE (__builtin_tend (0));
if (__builtin_expect (status, _HTM_TRANSACTIONAL))
return 1;
return 0;
}
extern __inline void
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_abort (void)
{
__builtin_tabort (0);
}
extern __inline void
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_named_abort (unsigned char const code)
{
__builtin_tabort (code);
}
extern __inline void
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_resume (void)
{
__builtin_tresume ();
}
extern __inline void
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_suspend (void)
{
__builtin_tsuspend ();
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_user_abort (void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
return _TEXASRU_ABORT (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_named_user_abort (void* const TM_buff, unsigned char *code)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
*code = _TEXASRU_FAILURE_CODE (texasru);
return _TEXASRU_ABORT (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_illegal (void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
return _TEXASRU_DISALLOWED (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_footprint_exceeded (void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
return _TEXASRU_FOOTPRINT_OVERFLOW (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_nesting_depth (void* const TM_buff)
{
texasrl_t texasrl;
if (_HTM_STATE (__builtin_ttest ()) == _HTM_NONTRANSACTIONAL)
{
texasrl = *_TEXASRL_PTR (TM_buff);
if (!_TEXASR_FAILURE_SUMMARY (texasrl))
texasrl = 0;
}
else
texasrl = (texasrl_t) __builtin_get_texasr ();
return _TEXASR_TRANSACTION_LEVEL (texasrl);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_nested_too_deep(void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
return _TEXASRU_NESTING_OVERFLOW (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_conflict(void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
/* Return TEXASR bits 11 (Self-Induced Conflict) through
14 (Translation Invalidation Conflict). */
return (_TEXASRU_EXTRACT_BITS (texasru, 14, 4)) ? 1 : 0;
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_is_failure_persistent(void* const TM_buff)
{
texasru_t texasru = *_TEXASRU_PTR (TM_buff);
return _TEXASRU_FAILURE_PERSISTENT (texasru);
}
extern __inline long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_failure_address(void* const TM_buff)
{
return *_TFIAR_PTR (TM_buff);
}
extern __inline long long
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
__TM_failure_code(void* const TM_buff)
{
return *_TEXASR_PTR (TM_buff);
}
#ifdef __cplusplus
}
#endif
#endif /* _HTMXLINTRIN_H */

153
gcc/config/powerpcspe/linux.h
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@ -1,153 +0,0 @@
/* Definitions of target machine for GNU compiler,
for PowerPC machines running Linux.
Copyright (C) 1996-2018 Free Software Foundation, Inc.
Contributed by Michael Meissner (meissner@cygnus.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Linux doesn't support saving and restoring 64-bit regs in a 32-bit
process. */
#define OS_MISSING_POWERPC64 1
/* We use glibc _mcount for profiling. */
#define NO_PROFILE_COUNTERS 1
#ifdef SINGLE_LIBC
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
#undef OPTION_MUSL
#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
#undef OPTION_MUSL
#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
/* Determine what functions are present at the runtime;
this includes full c99 runtime and sincos. */
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION linux_libc_has_function
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("PPC"); \
builtin_define_std ("powerpc"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
while (0)
#define GNU_USER_TARGET_D_OS_VERSIONS() \
do { \
builtin_version ("linux"); \
if (OPTION_GLIBC) \
builtin_version ("CRuntime_Glibc"); \
else if (OPTION_UCLIBC) \
builtin_version ("CRuntime_UClibc"); \
else if (OPTION_BIONIC) \
builtin_version ("CRuntime_Bionic"); \
else if (OPTION_MUSL) \
builtin_version ("CRuntime_Musl"); \
} while (0)
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
#undef LINK_SHLIB_SPEC
#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "%(lib_linux)"
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "%(startfile_linux)"
#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "%(endfile_linux)"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "%(link_start_linux)"
#undef LINK_OS_DEFAULT_SPEC
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
#undef DEFAULT_ASM_ENDIAN
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#define DEFAULT_ASM_ENDIAN " -mlittle"
#define LINK_OS_LINUX_EMUL ENDIAN_SELECT(" -m elf32ppclinux", \
" -m elf32lppclinux", \
" -m elf32lppclinux")
#else
#define DEFAULT_ASM_ENDIAN " -mbig"
#define LINK_OS_LINUX_EMUL ENDIAN_SELECT(" -m elf32ppclinux", \
" -m elf32lppclinux", \
" -m elf32ppclinux")
#endif
#undef LINK_OS_LINUX_SPEC
#define LINK_OS_LINUX_SPEC LINK_OS_LINUX_EMUL " %{!shared: %{!static: \
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
/* For backward compatibility, we must continue to use the AIX
structure return convention. */
#undef DRAFT_V4_STRUCT_RET
#define DRAFT_V4_STRUCT_RET 1
/* We are 32-bit all the time, so optimize a little. */
#undef TARGET_64BIT
#define TARGET_64BIT 0
/* We don't need to generate entries in .fixup, except when
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
(rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#ifdef TARGET_LIBC_PROVIDES_SSP
/* ppc32 glibc provides __stack_chk_guard in -0x7008(2). */
#define TARGET_THREAD_SSP_OFFSET -0x7008
#endif
#define POWERPC_LINUX
/* ppc linux has 128-bit long double support in glibc 2.4 and later. */
#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 128
#endif
/* Static stack checking is supported by means of probes. */
#define STACK_CHECK_STATIC_BUILTIN 1
/* Software floating point support for exceptions and rounding modes
depends on the C library in use. */
#undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
#define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
rs6000_linux_float_exceptions_rounding_supported_p
/* Support for TARGET_ATOMIC_ASSIGN_EXPAND_FENV without FPRs depends
on glibc 2.19 or greater. */
#if TARGET_GLIBC_MAJOR > 2 \
|| (TARGET_GLIBC_MAJOR == 2 && TARGET_GLIBC_MINOR >= 19)
#define RS6000_GLIBC_ATOMIC_FENV 1
#endif

655
gcc/config/powerpcspe/linux64.h
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@ -1,655 +0,0 @@
/* Definitions of target machine for GNU compiler,
for 64 bit PowerPC linux.
Copyright (C) 2000-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef RS6000_BI_ARCH
#undef TARGET_64BIT
#define TARGET_64BIT 1
#define DEFAULT_ARCH64_P 1
#define RS6000_BI_ARCH_P 0
#else
#define DEFAULT_ARCH64_P (TARGET_DEFAULT & MASK_64BIT)
#define RS6000_BI_ARCH_P 1
#endif
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __powerpc64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
#undef TARGET_AIX
#define TARGET_AIX TARGET_64BIT
#ifdef HAVE_LD_NO_DOT_SYMS
/* New ABI uses a local sym for the function entry point. */
extern int dot_symbols;
#undef DOT_SYMBOLS
#define DOT_SYMBOLS dot_symbols
#endif
#define TARGET_PROFILE_KERNEL profile_kernel
#undef TARGET_KEEP_LEAF_WHEN_PROFILED
#define TARGET_KEEP_LEAF_WHEN_PROFILED rs6000_keep_leaf_when_profiled
#define TARGET_USES_LINUX64_OPT 1
#ifdef HAVE_LD_LARGE_TOC
#undef TARGET_CMODEL
#define TARGET_CMODEL rs6000_current_cmodel
#define SET_CMODEL(opt) rs6000_current_cmodel = opt
#else
#define SET_CMODEL(opt) do {} while (0)
#endif
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
#undef PROCESSOR_DEFAULT64
#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8
/* We don't need to generate entries in .fixup, except when
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
(rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#undef RS6000_ABI_NAME
#define RS6000_ABI_NAME "linux"
#define INVALID_64BIT "-m%s not supported in this configuration"
#define INVALID_32BIT INVALID_64BIT
#ifdef LINUX64_DEFAULT_ABI_ELFv2
#define ELFv2_ABI_CHECK (rs6000_elf_abi != 1)
#else
#define ELFv2_ABI_CHECK (rs6000_elf_abi == 2)
#endif
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
do \
{ \
if (!global_options_set.x_rs6000_alignment_flags) \
rs6000_alignment_flags = MASK_ALIGN_NATURAL; \
if (rs6000_isa_flags & OPTION_MASK_64BIT) \
{ \
if (DEFAULT_ABI != ABI_AIX) \
{ \
rs6000_current_abi = ABI_AIX; \
error (INVALID_64BIT, "call"); \
} \
dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \
if (ELFv2_ABI_CHECK) \
{ \
rs6000_current_abi = ABI_ELFv2; \
if (dot_symbols) \
error ("-mcall-aixdesc incompatible with -mabi=elfv2"); \
} \
if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
{ \
rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
error (INVALID_64BIT, "relocatable"); \
} \
if (rs6000_isa_flags & OPTION_MASK_EABI) \
{ \
rs6000_isa_flags &= ~OPTION_MASK_EABI; \
error (INVALID_64BIT, "eabi"); \
} \
if (TARGET_PROTOTYPE) \
{ \
target_prototype = 0; \
error (INVALID_64BIT, "prototype"); \
} \
if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \
{ \
rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
error ("-m64 requires a PowerPC64 cpu"); \
} \
if ((rs6000_isa_flags_explicit \
& OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
error ("-mcmodel incompatible with other toc options"); \
SET_CMODEL (CMODEL_SMALL); \
} \
else \
{ \
if (!global_options_set.x_rs6000_current_cmodel) \
SET_CMODEL (CMODEL_MEDIUM); \
if (rs6000_current_cmodel != CMODEL_SMALL) \
{ \
if (!global_options_set.x_TARGET_NO_FP_IN_TOC) \
TARGET_NO_FP_IN_TOC \
= rs6000_current_cmodel == CMODEL_MEDIUM; \
if (!global_options_set.x_TARGET_NO_SUM_IN_TOC) \
TARGET_NO_SUM_IN_TOC = 0; \
} \
} \
} \
else \
{ \
if (!RS6000_BI_ARCH_P) \
error (INVALID_32BIT, "32"); \
if (TARGET_PROFILE_KERNEL) \
{ \
TARGET_PROFILE_KERNEL = 0; \
error (INVALID_32BIT, "profile-kernel"); \
} \
if (global_options_set.x_rs6000_current_cmodel) \
{ \
SET_CMODEL (CMODEL_SMALL); \
error (INVALID_32BIT, "cmodel"); \
} \
} \
} \
while (0)
#undef ASM_DEFAULT_SPEC
#undef ASM_SPEC
#undef LINK_OS_LINUX_SPEC
#undef LINK_SECURE_PLT_SPEC
#ifndef RS6000_BI_ARCH
#define ASM_DEFAULT_SPEC "-mppc64"
#define ASM_SPEC "%(asm_spec64) %(asm_spec_common)"
#define LINK_OS_LINUX_SPEC "%(link_os_linux_spec64)"
#define LINK_SECURE_PLT_SPEC ""
#else
#if DEFAULT_ARCH64_P
#define ASM_DEFAULT_SPEC "-mppc%{!m32:64}"
#define ASM_SPEC "%{m32:%(asm_spec32)}%{!m32:%(asm_spec64)} %(asm_spec_common)"
#define LINK_OS_LINUX_SPEC "%{m32:%(link_os_linux_spec32)}%{!m32:%(link_os_linux_spec64)}"
#define LINK_SECURE_PLT_SPEC "%{m32: " LINK_SECURE_PLT_DEFAULT_SPEC "}"
#else
#define ASM_DEFAULT_SPEC "-mppc%{m64:64}"
#define ASM_SPEC "%{!m64:%(asm_spec32)}%{m64:%(asm_spec64)} %(asm_spec_common)"
#define LINK_OS_LINUX_SPEC "%{!m64:%(link_os_linux_spec32)}%{m64:%(link_os_linux_spec64)}"
#define LINK_SECURE_PLT_SPEC "%{!m64: " LINK_SECURE_PLT_DEFAULT_SPEC "}"
#endif
#endif
#define ASM_SPEC32 "-a32 \
%{mrelocatable} %{mrelocatable-lib} %{" FPIE_OR_FPIC_SPEC ":-K PIC} \
%{memb|msdata=eabi: -memb}"
#define ASM_SPEC64 "-a64"
#define ASM_SPEC_COMMON "%(asm_cpu) \
%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \
ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#undef SUBSUBTARGET_EXTRA_SPECS
#define SUBSUBTARGET_EXTRA_SPECS \
{ "asm_spec_common", ASM_SPEC_COMMON }, \
{ "asm_spec32", ASM_SPEC32 }, \
{ "asm_spec64", ASM_SPEC64 }, \
{ "link_os_linux_spec32", LINK_OS_LINUX_SPEC32 }, \
{ "link_os_linux_spec64", LINK_OS_LINUX_SPEC64 }, \
{ "link_os_extra_spec32", LINK_OS_EXTRA_SPEC32 }, \
{ "link_os_extra_spec64", LINK_OS_EXTRA_SPEC64 }, \
{ "link_os_new_dtags", LINK_OS_NEW_DTAGS_SPEC }, \
{ "include_extra", INCLUDE_EXTRA_SPEC }, \
{ "dynamic_linker_prefix", DYNAMIC_LINKER_PREFIX },
/* Optional specs used for overriding the system include directory, default
-rpath links, and prefix for the dynamic linker. Normally, there are not
defined, but if the user configure with the --with-advance-toolchain=<xxx>
option, the advance-toolchain.h file will override these. */
#ifndef INCLUDE_EXTRA_SPEC
#define INCLUDE_EXTRA_SPEC ""
#endif
#ifndef LINK_OS_EXTRA_SPEC32
#define LINK_OS_EXTRA_SPEC32 ""
#endif
#ifndef LINK_OS_EXTRA_SPEC64
#define LINK_OS_EXTRA_SPEC64 ""
#endif
#ifndef LINK_OS_NEW_DTAGS_SPEC
#define LINK_OS_NEW_DTAGS_SPEC ""
#endif
#ifndef DYNAMIC_LINKER_PREFIX
#define DYNAMIC_LINKER_PREFIX ""
#endif
#undef MULTILIB_DEFAULTS
#if DEFAULT_ARCH64_P
#define MULTILIB_DEFAULTS { "m64" }
#else
#define MULTILIB_DEFAULTS { "m32" }
#endif
/* Split stack is only supported for 64 bit, and requires glibc >= 2.18. */
#if TARGET_GLIBC_MAJOR * 1000 + TARGET_GLIBC_MINOR >= 2018
# ifndef RS6000_BI_ARCH
# define TARGET_CAN_SPLIT_STACK
# else
# if DEFAULT_ARCH64_P
/* Supported, and the default is -m64 */
# define TARGET_CAN_SPLIT_STACK_64BIT 1
# else
/* Supported, and the default is -m32 */
# define TARGET_CAN_SPLIT_STACK_64BIT 0
# endif
# endif
#endif
#ifndef RS6000_BI_ARCH
/* 64-bit PowerPC Linux always has a TOC. */
#undef TARGET_TOC
#define TARGET_TOC 1
/* Some things from sysv4.h we don't do when 64 bit. */
#undef OPTION_RELOCATABLE
#define OPTION_RELOCATABLE 0
#undef OPTION_EABI
#define OPTION_EABI 0
#undef OPTION_PROTOTYPE
#define OPTION_PROTOTYPE 0
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP 0
#endif
/* We use glibc _mcount for profiling. */
#define NO_PROFILE_COUNTERS 1
#define PROFILE_HOOK(LABEL) \
do { if (TARGET_64BIT) output_profile_hook (LABEL); } while (0)
/* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */
#undef ADJUST_FIELD_ALIGN
#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
(rs6000_special_adjust_field_align_p ((TYPE), (COMPUTED)) \
? 128 \
: (TARGET_64BIT \
&& TARGET_ALIGN_NATURAL == 0 \
&& TYPE_MODE (strip_array_types (TYPE)) == DFmode) \
? MIN ((COMPUTED), 32) \
: (COMPUTED))
/* PowerPC64 Linux increases natural record alignment to doubleword if
the first field is an FP double, only if in power alignment mode. */
#undef ROUND_TYPE_ALIGN
#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
((TARGET_64BIT \
&& (TREE_CODE (STRUCT) == RECORD_TYPE \
|| TREE_CODE (STRUCT) == UNION_TYPE \
|| TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
&& TARGET_ALIGN_NATURAL == 0) \
? rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED) \
: MAX ((COMPUTED), (SPECIFIED)))
/* Use the default for compiling target libs. */
#ifdef IN_TARGET_LIBS
#undef TARGET_ALIGN_NATURAL
#define TARGET_ALIGN_NATURAL 1
#endif
/* Indicate that jump tables go in the text section. */
#undef JUMP_TABLES_IN_TEXT_SECTION
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_64BIT
/* The linux ppc64 ABI isn't explicit on whether aggregates smaller
than a doubleword should be padded upward or downward. You could
reasonably assume that they follow the normal rules for structure
layout treating the parameter area as any other block of memory,
then map the reg param area to registers. i.e. pad upward.
Setting both of the following defines results in this behavior.
Setting just the first one will result in aggregates that fit in a
doubleword being padded downward, and others being padded upward.
Not a bad idea as this results in struct { int x; } being passed
the same way as an int. */
#define AGGREGATE_PADDING_FIXED TARGET_64BIT
#define AGGREGATES_PAD_UPWARD_ALWAYS 0
/* Specify padding for the last element of a block move between
registers and memory. FIRST is nonzero if this is the only
element. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(!(FIRST) ? PAD_UPWARD : targetm.calls.function_arg_padding (MODE, TYPE))
/* Linux doesn't support saving and restoring 64-bit regs in a 32-bit
process. */
#define OS_MISSING_POWERPC64 !TARGET_64BIT
#ifdef SINGLE_LIBC
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
#undef OPTION_MUSL
#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
#undef OPTION_MUSL
#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
/* Determine what functions are present at the runtime;
this includes full c99 runtime and sincos. */
#undef TARGET_LIBC_HAS_FUNCTION
#define TARGET_LIBC_HAS_FUNCTION linux_libc_has_function
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
if (TARGET_64BIT) \
{ \
builtin_define ("__PPC__"); \
builtin_define ("__PPC64__"); \
builtin_define ("__powerpc__"); \
builtin_define ("__powerpc64__"); \
if (!DOT_SYMBOLS) \
builtin_define ("_CALL_LINUX"); \
builtin_assert ("cpu=powerpc64"); \
builtin_assert ("machine=powerpc64"); \
} \
else \
{ \
builtin_define_std ("PPC"); \
builtin_define_std ("powerpc"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
} \
while (0)
#define GNU_USER_TARGET_D_OS_VERSIONS() \
do { \
builtin_version ("linux"); \
if (OPTION_GLIBC) \
builtin_version ("CRuntime_Glibc"); \
else if (OPTION_UCLIBC) \
builtin_version ("CRuntime_UClibc"); \
else if (OPTION_BIONIC) \
builtin_version ("CRuntime_Bionic"); \
else if (OPTION_MUSL) \
builtin_version ("CRuntime_Musl"); \
} while (0)
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux) %(include_extra)"
#undef LINK_SHLIB_SPEC
#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}"
#undef LIB_DEFAULT_SPEC
#define LIB_DEFAULT_SPEC "%(lib_linux)"
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "%(startfile_linux)"
#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "%(endfile_linux)"
#undef LINK_START_DEFAULT_SPEC
#define LINK_START_DEFAULT_SPEC "%(link_start_linux)"
#undef LINK_OS_DEFAULT_SPEC
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
#define GLIBC_DYNAMIC_LINKER32 "%(dynamic_linker_prefix)/lib/ld.so.1"
#ifdef LINUX64_DEFAULT_ABI_ELFv2
#define GLIBC_DYNAMIC_LINKER64 \
"%{mabi=elfv1:%(dynamic_linker_prefix)/lib64/ld64.so.1;" \
":%(dynamic_linker_prefix)/lib64/ld64.so.2}"
#else
#define GLIBC_DYNAMIC_LINKER64 \
"%{mabi=elfv2:%(dynamic_linker_prefix)/lib64/ld64.so.2;" \
":%(dynamic_linker_prefix)/lib64/ld64.so.1}"
#endif
#define MUSL_DYNAMIC_LINKER32 \
"/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
#define MUSL_DYNAMIC_LINKER64 \
"/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
#if DEFAULT_LIBC == LIBC_UCLIBC
#define CHOOSE_DYNAMIC_LINKER(G, U, M) \
"%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
#elif DEFAULT_LIBC == LIBC_GLIBC
#define CHOOSE_DYNAMIC_LINKER(G, U, M) \
"%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
#elif DEFAULT_LIBC == LIBC_MUSL
#define CHOOSE_DYNAMIC_LINKER(G, U, M) \
"%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
#else
#error "Unsupported DEFAULT_LIBC"
#endif
#define GNU_USER_DYNAMIC_LINKER32 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \
MUSL_DYNAMIC_LINKER32)
#define GNU_USER_DYNAMIC_LINKER64 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \
MUSL_DYNAMIC_LINKER64)
#undef DEFAULT_ASM_ENDIAN
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#define DEFAULT_ASM_ENDIAN " -mlittle"
#define LINK_OS_LINUX_EMUL32 ENDIAN_SELECT(" -m elf32ppclinux", \
" -m elf32lppclinux", \
" -m elf32lppclinux")
#define LINK_OS_LINUX_EMUL64 ENDIAN_SELECT(" -m elf64ppc", \
" -m elf64lppc", \
" -m elf64lppc")
#else
#define DEFAULT_ASM_ENDIAN " -mbig"
#define LINK_OS_LINUX_EMUL32 ENDIAN_SELECT(" -m elf32ppclinux", \
" -m elf32lppclinux", \
" -m elf32ppclinux")
#define LINK_OS_LINUX_EMUL64 ENDIAN_SELECT(" -m elf64ppc", \
" -m elf64lppc", \
" -m elf64ppc")
#endif
#define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
%(link_os_extra_spec32)"
#define LINK_OS_LINUX_SPEC64 LINK_OS_LINUX_EMUL64 " %{!shared: %{!static: \
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "}} \
%(link_os_extra_spec64)"
#undef TOC_SECTION_ASM_OP
#define TOC_SECTION_ASM_OP \
(TARGET_64BIT \
? "\t.section\t\".toc\",\"aw\"" \
: "\t.section\t\".got\",\"aw\"")
#undef MINIMAL_TOC_SECTION_ASM_OP
#define MINIMAL_TOC_SECTION_ASM_OP \
(TARGET_64BIT \
? "\t.section\t\".toc1\",\"aw\"" \
: (flag_pic \
? "\t.section\t\".got2\",\"aw\"" \
: "\t.section\t\".got1\",\"aw\""))
/* Must be at least as big as our pointer type. */
#undef SIZE_TYPE
#define SIZE_TYPE (TARGET_64BIT ? "long unsigned int" : "unsigned int")
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int")
#undef WCHAR_TYPE
#define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int")
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
#undef RS6000_MCOUNT
#define RS6000_MCOUNT "_mcount"
#ifdef __powerpc64__
/* _init and _fini functions are built from bits spread across many
object files, each potentially with a different TOC pointer. For
that reason, place a nop after the call so that the linker can
restore the TOC pointer if a TOC adjusting call stub is needed. */
#if DOT_SYMBOLS
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n" \
" bl ." #FUNC "\n" \
" nop\n" \
" .previous");
#else
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n" \
" bl " #FUNC "\n" \
" nop\n" \
" .previous");
#endif
#endif
/* FP save and restore routines. */
#undef SAVE_FP_PREFIX
#define SAVE_FP_PREFIX (TARGET_64BIT ? "._savef" : "_savefpr_")
#undef SAVE_FP_SUFFIX
#define SAVE_FP_SUFFIX ""
#undef RESTORE_FP_PREFIX
#define RESTORE_FP_PREFIX (TARGET_64BIT ? "._restf" : "_restfpr_")
#undef RESTORE_FP_SUFFIX
#define RESTORE_FP_SUFFIX ""
/* Dwarf2 debugging. */
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* This is how to declare the size of a function. */
#undef ASM_DECLARE_FUNCTION_SIZE
#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
do \
{ \
if (!flag_inhibit_size_directive) \
{ \
fputs ("\t.size\t", (FILE)); \
if (TARGET_64BIT && DOT_SYMBOLS) \
putc ('.', (FILE)); \
assemble_name ((FILE), (FNAME)); \
fputs (",.-", (FILE)); \
rs6000_output_function_entry (FILE, FNAME); \
putc ('\n', (FILE)); \
} \
} \
while (0)
/* Return nonzero if this entry is to be written into the constant
pool in a special way. We do so if this is a SYMBOL_REF, LABEL_REF
or a CONST containing one of them. If -mfp-in-toc (the default),
we also do this for floating-point constants. We actually can only
do this if the FP formats of the target and host machines are the
same, but we can't check that since not every file that uses
the macros includes real.h. We also do this when we can write the
entry into the TOC and the entry is not larger than a TOC entry. */
#undef ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE) \
(TARGET_TOC \
&& (GET_CODE (X) == SYMBOL_REF \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF) \
|| GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST_INT \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (GET_CODE (X) == CONST_DOUBLE \
&& ((TARGET_64BIT \
&& (TARGET_MINIMAL_TOC \
|| (SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
&& ! TARGET_NO_FP_IN_TOC))) \
|| (!TARGET_64BIT \
&& !TARGET_NO_FP_IN_TOC \
&& SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
&& BITS_PER_WORD == HOST_BITS_PER_INT)))))
/* Select a format to encode pointers in exception handling data. CODE
is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
true if the symbol may be affected by dynamic relocations. */
#undef ASM_PREFERRED_EH_DATA_FORMAT
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(TARGET_64BIT || flag_pic \
? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel \
| (TARGET_64BIT ? DW_EH_PE_udata8 : DW_EH_PE_sdata4)) \
: DW_EH_PE_absptr)
/* For backward compatibility, we must continue to use the AIX
structure return convention. */
#undef DRAFT_V4_STRUCT_RET
#define DRAFT_V4_STRUCT_RET (!TARGET_64BIT)
#ifdef TARGET_LIBC_PROVIDES_SSP
/* ppc32 glibc provides __stack_chk_guard in -0x7008(2),
ppc64 glibc provides it at -0x7010(13). */
#define TARGET_THREAD_SSP_OFFSET (TARGET_64BIT ? -0x7010 : -0x7008)
#endif
#define POWERPC_LINUX
/* ppc{32,64} linux has 128-bit long double support in glibc 2.4 and later. */
#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 128
#endif
/* Static stack checking is supported by means of probes. */
#define STACK_CHECK_STATIC_BUILTIN 1
/* The default value isn't sufficient in 64-bit mode. */
#define STACK_CHECK_PROTECT (TARGET_64BIT ? 16 * 1024 : 12 * 1024)
/* Software floating point support for exceptions and rounding modes
depends on the C library in use. */
#undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
#define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
rs6000_linux_float_exceptions_rounding_supported_p
/* Support for TARGET_ATOMIC_ASSIGN_EXPAND_FENV without FPRs depends
on glibc 2.19 or greater. */
#if TARGET_GLIBC_MAJOR > 2 \
|| (TARGET_GLIBC_MAJOR == 2 && TARGET_GLIBC_MINOR >= 19)
#define RS6000_GLIBC_ATOMIC_FENV 1
#endif
/* The IEEE 128-bit emulator is only built on Linux systems. Flag that we
should enable the type handling for KFmode on VSX systems even if we are not
enabling the __float128 keyword. */
#undef TARGET_FLOAT128_ENABLE_TYPE
#define TARGET_FLOAT128_ENABLE_TYPE 1

42
gcc/config/powerpcspe/linux64.opt
View file

@ -1,42 +0,0 @@
; Options for 64-bit PowerPC Linux.
;
; Copyright (C) 2005-2018 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
mprofile-kernel
Target Report Var(profile_kernel) Save
Call mcount for profiling before a function prologue.
mcmodel=
Target RejectNegative Joined Enum(rs6000_cmodel) Var(rs6000_current_cmodel)
Select code model.
Enum
Name(rs6000_cmodel) Type(enum rs6000_cmodel)
Known code models (for use with the -mcmodel= option):
EnumValue
Enum(rs6000_cmodel) String(small) Value(CMODEL_SMALL)
EnumValue
Enum(rs6000_cmodel) String(medium) Value(CMODEL_MEDIUM)
EnumValue
Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE)

32
gcc/config/powerpcspe/linuxaltivec.h
View file

@ -1,32 +0,0 @@
/* Definitions of target machine for GNU compiler,
for AltiVec enhanced PowerPC machines running GNU/Linux.
Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Override rs6000.h and sysv4.h definition. */
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_ALTIVEC | MASK_LITTLE_ENDIAN)
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_ALTIVEC
#endif
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1

32
gcc/config/powerpcspe/linuxspe.h
View file

@ -1,32 +0,0 @@
/* Definitions of target machine for GNU compiler,
for PowerPC e500 machines running GNU/Linux.
Copyright (C) 2003-2018 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldy@quesejoda.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Override rs6000.h and sysv4.h definition. */
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_LITTLE_ENDIAN)
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_STRICT_ALIGN
#endif
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

120
gcc/config/powerpcspe/lynx.h
View file

@ -1,120 +0,0 @@
/* Definitions for Rs6000 running LynxOS.
Copyright (C) 1995-2018 Free Software Foundation, Inc.
Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
Rewritten by Adam Nemet, LynuxWorks Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Undefine the definition to enable the LynxOS default from the
top-level lynx.h. */
#undef SUBTARGET_EXTRA_SPECS
/* Get rid off the spec definitions from rs6000/sysv4.h. */
#undef CPP_SPEC
#define CPP_SPEC \
"%{msoft-float: -D_SOFT_FLOAT} \
%(cpp_cpu) \
%(cpp_os_lynx)"
/* LynxOS only supports big-endian on PPC so we override the
definition from sysv4.h. Since the LynxOS 4.0 compiler was set to
return every structure in memory regardless of their size we have
to emulate the same behavior here with disabling the SVR4 structure
returning. */
#undef CC1_SPEC
#define CC1_SPEC \
"%{G*} %{mno-sdata:-msdata=none} \
%{maltivec:-mabi=altivec} \
-maix-struct-return"
#undef ASM_SPEC
#define ASM_SPEC \
"%(asm_cpu) \
%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}"
#undef STARTFILE_SPEC
#undef ENDFILE_SPEC
#undef LIB_SPEC
#undef LINK_SPEC
#define LINK_SPEC \
"%{!msdata=none:%{G*}} %{msdata=none:-G0} \
%(link_os_lynx)"
/* Override the definition from sysv4.h. */
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define ("__BIG_ENDIAN__"); \
builtin_define ("__powerpc__"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
builtin_define ("__PPC__"); \
} \
while (0)
/* Override the rs6000.h definition. */
#undef ASM_APP_ON
#define ASM_APP_ON "#APP\n"
/* Override the rs6000.h definition. */
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
/* LynxOS does not do anything with .fixup plus let's not create
writable section for linkonce.r and linkonce.t. */
#undef RELOCATABLE_NEEDS_FIXUP
/* Override these from rs6000.h with the generic definition. */
#undef SIZE_TYPE
#undef ASM_OUTPUT_ALIGN
#undef PREFERRED_DEBUGGING_TYPE
/* The file rs6000.c defines TARGET_HAVE_TLS unconditionally to the
value of HAVE_AS_TLS. HAVE_AS_TLS is true as gas support for TLS
is detected by configure. Override the definition to false. */
#undef HAVE_AS_TLS
#define HAVE_AS_TLS 0
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING
#ifdef CRT_BEGIN
/* This function is part of crtbegin*.o which is at the beginning of
the link and is called from .fini which is usually toward the end
of the executable. Make it longcall so that we don't limit the
text size of the executables to 32M. */
static void __do_global_dtors_aux (void) __attribute__ ((longcall));
#endif /* CRT_BEGIN */
#ifdef CRT_END
/* Similarly here. This function resides in crtend*.o which is toward
to end of the link and is called from .init which is at the
beginning. */
static void __do_global_ctors_aux (void) __attribute__ ((longcall));
#endif /* CRT_END */

7
gcc/config/powerpcspe/milli.exp
View file

@ -1,7 +0,0 @@
#!
__mulh 0x3100
__mull 0x3180
__divss 0x3200
__divus 0x3280
__quoss 0x3300
__quous 0x3380

112
gcc/config/powerpcspe/mpc.md
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@ -1,112 +0,0 @@
;; Scheduling description for Motorola PowerPC processor cores.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "mpc,mpcfp")
(define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
(define_cpu_unit "fpu_mpc" "mpcfp")
(define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
;; 505/801/821/823
(define_insn_reservation "mpccore-load" 2
(and (eq_attr "type" "load,load_l,store_c,sync")
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
(define_insn_reservation "mpccore-store" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
(define_insn_reservation "mpccore-fpload" 2
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
(define_insn_reservation "mpccore-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "mpccore"))
"iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "mpccore"))
"iu_mpc,iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-imul" 2
(and (eq_attr "type" "mul")
(eq_attr "cpu" "mpccore"))
"mciu_mpc")
; Divide latency varies greatly from 2-11, use 6 as average
(define_insn_reservation "mpccore-idiv" 6
(and (eq_attr "type" "div")
(eq_attr "cpu" "mpccore"))
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
(define_insn_reservation "mpccore-fpcompare" 2
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "mpccore"))
"fpu_mpc,bpu_mpc")
(define_insn_reservation "mpccore-fp" 4
(and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*2")
(define_insn_reservation "mpccore-dmul" 5
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*5")
(define_insn_reservation "mpccore-sdiv" 10
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*10")
(define_insn_reservation "mpccore-ddiv" 17
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*17")
(define_insn_reservation "mpccore-mtjmpr" 4
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "mpccore"))
"bpu_mpc")
(define_insn_reservation "mpccore-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
(eq_attr "cpu" "mpccore"))
"bpu_mpc")

92
gcc/config/powerpcspe/netbsd.h
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@ -1,92 +0,0 @@
/* Definitions of target machine for GNU compiler,
for PowerPC NetBSD systems.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by Wasabi Systems, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_OS_CPP_BUILTINS /* FIXME: sysv4.h should not define this! */
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
NETBSD_OS_CPP_BUILTINS_ELF(); \
builtin_define ("__powerpc__"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
} \
while (0)
/* Override the default from rs6000.h to avoid conflicts with macros
defined in NetBSD header files. */
#undef RS6000_CPU_CPP_ENDIAN_BUILTINS
#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
do \
{ \
if (BYTES_BIG_ENDIAN) \
{ \
builtin_define ("__BIG_ENDIAN__"); \
builtin_assert ("machine=bigendian"); \
} \
else \
{ \
builtin_define ("__LITTLE_ENDIAN__"); \
builtin_assert ("machine=littleendian"); \
} \
} \
while (0)
/* Make GCC agree with <machine/ansi.h>. */
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
/* Undo the spec mess from sysv4.h, and just define the specs
the way NetBSD systems actually expect. */
#undef CPP_SPEC
#define CPP_SPEC NETBSD_CPP_SPEC
#undef LINK_SPEC
#define LINK_SPEC \
"%{!msdata=none:%{G*}} %{msdata=none:-G0} \
%(netbsd_link_spec)"
#define NETBSD_ENTRY_POINT "_start"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC NETBSD_STARTFILE_SPEC
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "%(netbsd_endfile_spec)"
#undef LIB_SPEC
#define LIB_SPEC NETBSD_LIB_SPEC
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "netbsd_link_spec", NETBSD_LINK_SPEC_ELF }, \
{ "netbsd_entry_point", NETBSD_ENTRY_POINT }, \
{ "netbsd_endfile_spec", NETBSD_ENDFILE_SPEC },
/* Use standard DWARF numbering for DWARF debugging information. */
#define RS6000_USE_DWARF_NUMBERING

64
gcc/config/powerpcspe/option-defaults.h
View file

@ -1,64 +0,0 @@
/* Definitions of default options for config/rs6000 configurations.
Copyright (C) 1992-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This header needs to be included after any other headers affecting
TARGET_DEFAULT. */
#if TARGET_AIX_OS
#define OPT_64 "maix64"
#define OPT_32 "maix32"
#else
#define OPT_64 "m64"
#define OPT_32 "m32"
#endif
#ifndef OPTION_MASK_64BIT
#define OPTION_MASK_64BIT 0
#define MASK_64BIT 0
#endif
#if TARGET_DEFAULT & OPTION_MASK_64BIT
#define OPT_ARCH64 "!" OPT_32
#define OPT_ARCH32 OPT_32
#else
#define OPT_ARCH64 OPT_64
#define OPT_ARCH32 "!" OPT_64
#endif
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-cpu is ignored if -mcpu is specified; likewise --with-cpu-32
and --with-cpu-64.
--with-tune is ignored if -mtune or -mcpu is specified; likewise
--with-tune-32 and --with-tune-64.
--with-float is ignored if -mhard-float or -msoft-float are
specified. */
#define OPTION_DEFAULT_SPECS \
{"abi", "%{!mabi=elfv*:-mabi=%(VALUE)}" }, \
{"tune", "%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}" }, \
{"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \
{"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:-mtune=%(VALUE)}}}" }, \
{"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
{"cpu_32", "%{" OPT_ARCH32 ":%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
{"cpu_64", "%{" OPT_ARCH64 ":%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }

75
gcc/config/powerpcspe/paired.h
View file

@ -1,75 +0,0 @@
/* PowerPC 750CL user include file.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
Contributed by Revital Eres (eres@il.ibm.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _PAIRED_H
#define _PAIRED_H
#define vector __attribute__((vector_size(8)))
#define paired_msub __builtin_paired_msub
#define paired_madd __builtin_paired_madd
#define paired_nmsub __builtin_paired_nmsub
#define paired_nmadd __builtin_paired_nmadd
#define paired_sum0 __builtin_paired_sum0
#define paired_sum1 __builtin_paired_sum1
#define paired_div __builtin_paired_divv2sf3
#define paired_add __builtin_paired_addv2sf3
#define paired_sub __builtin_paired_subv2sf3
#define paired_mul __builtin_paired_mulv2sf3
#define paired_muls0 __builtin_paired_muls0
#define paired_muls1 __builtin_paired_muls1
#define paired_madds0 __builtin_paired_madds0
#define paired_madds1 __builtin_paired_madds1
#define paired_merge00 __builtin_paired_merge00
#define paired_merge01 __builtin_paired_merge01
#define paired_merge10 __builtin_paired_merge10
#define paired_merge11 __builtin_paired_merge11
#define paired_abs __builtin_paired_absv2sf2
#define paired_nabs __builtin_paired_nabsv2sf2
#define paired_neg __builtin_paired_negv2sf2
#define paired_sqrt __builtin_paired_sqrtv2sf2
#define paired_res __builtin_paired_resv2sf2
#define paired_stx __builtin_paired_stx
#define paired_lx __builtin_paired_lx
#define paired_cmpu0 __builtin_paired_cmpu0
#define paired_cmpu1 __builtin_paired_cmpu1
#define paired_sel __builtin_paired_selv2sf4
/* Condition register codes for Paired predicates. */
#define LT 0
#define GT 1
#define EQ 2
#define UN 3
#define paired_cmpu0_un(a,b) __builtin_paired_cmpu0 (UN, (a), (b))
#define paired_cmpu0_eq(a,b) __builtin_paired_cmpu0 (EQ, (a), (b))
#define paired_cmpu0_lt(a,b) __builtin_paired_cmpu0 (LT, (a), (b))
#define paired_cmpu0_gt(a,b) __builtin_paired_cmpu0 (GT, (a), (b))
#define paired_cmpu1_un(a,b) __builtin_paired_cmpu1 (UN, (a), (b))
#define paired_cmpu1_eq(a,b) __builtin_paired_cmpu1 (EQ, (a), (b))
#define paired_cmpu1_lt(a,b) __builtin_paired_cmpu1 (LT, (a), (b))
#define paired_cmpu1_gt(a,b) __builtin_paired_cmpu1 (GT, (a), (b))
#endif /* _PAIRED_H */

492
gcc/config/powerpcspe/paired.md
View file

@ -1,492 +0,0 @@
;; PowerPC paired single and double hummer description
;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
;; Contributed by David Edelsohn <edelsohn@gnu.org> and Revital Eres
;; <eres@il.ibm.com>
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_c_enum "unspec"
[UNSPEC_INTERHI_V2SF
UNSPEC_INTERLO_V2SF
UNSPEC_EXTEVEN_V2SF
UNSPEC_EXTODD_V2SF
])
(define_insn "paired_negv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_neg %0,%1"
[(set_attr "type" "fp")])
(define_insn "sqrtv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(sqrt:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_rsqrte %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_absv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_abs %0,%1"
[(set_attr "type" "fp")])
(define_insn "nabsv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_nabs %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_addv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_add %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "paired_subv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_sub %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "paired_mulv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_mul %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "resv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
"TARGET_PAIRED_FLOAT && flag_finite_math_only"
"ps_res %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_divv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_div %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn "paired_madds0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(fma:SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(fma:SF
(vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 2)
(parallel [(const_int 0)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_madds0 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_madds1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(fma:SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(fma:SF
(vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 2)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_madds1 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_madd"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(match_operand:V2SF 3 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_madd %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_msub"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_msub %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_nmadd"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(match_operand:V2SF 3 "gpc_reg_operand" "f"))))]
"TARGET_PAIRED_FLOAT"
"ps_nmadd %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*paired_nmsub"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF
(fma:V2SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(neg:V2SF (match_operand:V2SF 3 "gpc_reg_operand" "f")))))]
"TARGET_PAIRED_FLOAT"
"ps_nmsub %0,%1,%2,%3"
[(set_attr "type" "dmul")])
(define_insn "selv2sf4"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(if_then_else:SF (ge (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(match_operand:SF 4 "zero_fp_constant" "F"))
(vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))
(if_then_else:SF (ge (vec_select:SF (match_dup 1)
(parallel [(const_int 1)]))
(match_dup 4))
(vec_select:SF (match_dup 2)
(parallel [(const_int 1)]))
(vec_select:SF (match_dup 3)
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_sel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "*movv2sf_paired"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=Z,f,f,Y,r,r,f")
(match_operand:V2SF 1 "input_operand" "f,Z,f,r,Y,r,W"))]
"TARGET_PAIRED_FLOAT
&& (register_operand (operands[0], V2SFmode)
|| register_operand (operands[1], V2SFmode))"
{
switch (which_alternative)
{
case 0: return "psq_stx %1,%y0,0,0";
case 1: return "psq_lx %0,%y1,0,0";
case 2: return "ps_mr %0,%1";
case 3: return "#";
case 4: return "#";
case 5: return "#";
case 6: return "#";
default: gcc_unreachable ();
}
}
[(set_attr "type" "fpstore,fpload,fp,*,*,*,*")])
(define_insn "paired_stx"
[(set (match_operand:V2SF 0 "memory_operand" "=Z")
(match_operand:V2SF 1 "gpc_reg_operand" "f"))]
"TARGET_PAIRED_FLOAT"
"psq_stx %1,%y0,0,0"
[(set_attr "type" "fpstore")])
(define_insn "paired_lx"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "memory_operand" "Z"))]
"TARGET_PAIRED_FLOAT"
"psq_lx %0,%y1,0,0"
[(set_attr "type" "fpload")])
(define_split
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
(match_operand:V2SF 1 "input_operand" ""))]
"TARGET_PAIRED_FLOAT && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
{
rs6000_split_multireg_move (operands[0], operands[1]); DONE;
})
(define_insn "paired_cmpu0"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))))]
"TARGET_PAIRED_FLOAT"
"ps_cmpu0 %0,%1,%2"
[(set_attr "type" "fpcompare")])
(define_insn "paired_cmpu1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))))]
"TARGET_PAIRED_FLOAT"
"ps_cmpu1 %0,%1,%2"
[(set_attr "type" "fpcompare")])
(define_insn "paired_merge00"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 0) (const_int 2)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge00 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge01"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 0) (const_int 3)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge01 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge10"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 1) (const_int 2)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge10 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_merge11"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_select:V2SF
(vec_concat:V4SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f"))
(parallel [(const_int 1) (const_int 3)])))]
"TARGET_PAIRED_FLOAT"
"ps_merge11 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_sum0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF (plus:SF (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))
(vec_select:SF
(match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))))]
"TARGET_PAIRED_FLOAT"
"ps_sum0 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_sum1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF (vec_select:SF
(match_operand:V2SF 2 "gpc_reg_operand" "f")
(parallel [(const_int 1)]))
(plus:SF (vec_select:SF
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)]))
(vec_select:SF
(match_operand:V2SF 3 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_sum1 %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "paired_muls0"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(vec_duplicate:V2SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 0)])))))]
"TARGET_PAIRED_FLOAT"
"ps_muls0 %0, %1, %2"
[(set_attr "type" "fp")])
(define_insn "paired_muls1"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
(vec_duplicate:V2SF
(vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(parallel [(const_int 1)])))))]
"TARGET_PAIRED_FLOAT"
"ps_muls1 %0, %1, %2"
[(set_attr "type" "fp")])
(define_expand "vec_initv2sfsf"
[(match_operand:V2SF 0 "gpc_reg_operand" "=f")
(match_operand 1 "" "")]
"TARGET_PAIRED_FLOAT"
{
paired_expand_vector_init (operands[0], operands[1]);
DONE;
})
(define_insn "*vconcatsf"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(vec_concat:V2SF
(match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
"ps_merge00 %0, %1, %2"
[(set_attr "type" "fp")])
(define_expand "sminv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(smin:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
{
rtx tmp = gen_reg_rtx (V2SFmode);
emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
emit_insn (gen_selv2sf4 (operands[0], tmp, operands[2], operands[1], CONST0_RTX (SFmode)));
DONE;
})
(define_expand "smaxv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(smax:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
{
rtx tmp = gen_reg_rtx (V2SFmode);
emit_insn (gen_subv2sf3 (tmp, operands[1], operands[2]));
emit_insn (gen_selv2sf4 (operands[0], tmp, operands[1], operands[2], CONST0_RTX (SFmode)));
DONE;
})
(define_expand "reduc_smax_scal_v2sf"
[(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT"
{
rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (vec_res, tmp, operands[1], tmp_swap,
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "reduc_smin_scal_v2sf"
[(match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f")]
"TARGET_PAIRED_FLOAT"
{
rtx tmp_swap = gen_reg_rtx (V2SFmode);
rtx tmp = gen_reg_rtx (V2SFmode);
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1]));
emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap));
emit_insn (gen_selv2sf4 (vec_res, tmp, tmp_swap, operands[1],
CONST0_RTX (SFmode)));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "reduc_plus_scal_v2sf"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(match_operand:V2SF 1 "gpc_reg_operand" "f"))]
"TARGET_PAIRED_FLOAT"
{
rtx vec_res = gen_reg_rtx (V2SFmode);
rtx di_res = gen_reg_rtx (DImode);
emit_insn (gen_paired_sum1 (vec_res, operands[1], operands[1], operands[1]));
emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0));
emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode,
BYTES_BIG_ENDIAN ? 4 : 0));
DONE;
})
(define_expand "movmisalignv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
(match_operand:V2SF 1 "any_operand" ""))]
"TARGET_PAIRED_FLOAT"
{
paired_expand_vector_move (operands);
DONE;
})
(define_expand "vcondv2sfv2sf"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(if_then_else:V2SF
(match_operator 3 "gpc_reg_operand"
[(match_operand:V2SF 4 "gpc_reg_operand" "f")
(match_operand:V2SF 5 "gpc_reg_operand" "f")])
(match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT && flag_unsafe_math_optimizations"
{
if (paired_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
})

451
gcc/config/powerpcspe/power4.md
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@ -1,451 +0,0 @@
;; Scheduling description for IBM Power4 and PowerPC 970 processors.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Sources: IBM Red Book and White Paper on POWER4
;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
;; Instructions that update more than one register get broken into two
;; (split) or more internal ops. The chip can issue up to 5
;; internal ops per cycle.
(define_automaton "power4iu,power4fpu,power4vec,power4misc")
(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
"power4misc")
(define_reservation "lsq_power4"
"(du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\
|(du3_power4,lsu2_power4)\
|(du4_power4,lsu1_power4)")
(define_reservation "lsuq_power4"
"((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\
|(du3_power4+du4_power4,lsu2_power4))\
+(nothing,iu2_power4|nothing,iu1_power4)")
(define_reservation "iq_power4"
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4|iu2_power4)")
(define_reservation "fpq_power4"
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(fpu1_power4|fpu2_power4)")
(define_reservation "vq_power4"
"(du1_power4,vec_power4)\
|(du2_power4,vec_power4)\
|(du3_power4,vec_power4)\
|(du4_power4,vec_power4)")
(define_reservation "vpq_power4"
"(du1_power4,vecperm_power4)\
|(du2_power4,vecperm_power4)\
|(du3_power4,vecperm_power4)\
|(du4_power4,vecperm_power4)")
; Dispatch slots are allocated in order conforming to program order.
(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
(absence_set "du3_power4" "du4_power4,du5_power4")
(absence_set "du4_power4" "du5_power4")
; Load/store
(define_insn_reservation "power4-load" 4 ; 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power4"))
"lsq_power4")
(define_insn_reservation "power4-load-ext" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,lsu1_power4\
|du2_power4+du3_power4,lsu2_power4\
|du3_power4+du4_power4,lsu2_power4),\
nothing,nothing,\
(iu2_power4|iu1_power4)")
(define_insn_reservation "power4-load-ext-update" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-ext-update-indexed" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
(define_insn_reservation "power4-load-update-indexed" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4")
(define_insn_reservation "power4-load-update" 4 ; 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4"))
"lsuq_power4")
(define_insn_reservation "power4-fpload" 6 ; 5
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power4"))
"lsq_power4")
(define_insn_reservation "power4-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4"))
"lsuq_power4")
(define_insn_reservation "power4-vecload" 6 ; 5
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "power4"))
"lsq_power4")
(define_insn_reservation "power4-store" 12
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\
|(du3_power4,lsu2_power4)\
|(du4_power4,lsu1_power4)),\
(iu1_power4|iu2_power4)")
(define_insn_reservation "power4-store-update" 12
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\
|(du3_power4+du4_power4,lsu2_power4))+\
((nothing,iu1_power4,iu2_power4)\
|(nothing,iu2_power4,iu2_power4)\
|(nothing,iu2_power4,iu1_power4))")
(define_insn_reservation "power4-store-update-indexed" 12
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
(define_insn_reservation "power4-fpstore" 12
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power4"))
"((du1_power4,lsu1_power4)\
|(du2_power4,lsu2_power4)\
|(du3_power4,lsu2_power4)\
|(du4_power4,lsu1_power4)),\
(fpu1_power4|fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 12
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power4"))
"((du1_power4+du2_power4,lsu1_power4)\
|(du2_power4+du3_power4,lsu2_power4)\
|(du3_power4+du4_power4,lsu2_power4))\
+(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))")
(define_insn_reservation "power4-vecstore" 12
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
"(du1_power4,lsu1_power4,vec_power4)\
|(du2_power4,lsu2_power4,vec_power4)\
|(du3_power4,lsu2_power4,vec_power4)\
|(du4_power4,lsu1_power4,vec_power4)")
(define_insn_reservation "power4-llsc" 11
(and (eq_attr "type" "load_l,store_c,sync")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power4"))
"iq_power4")
(define_insn_reservation "power4-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power4"))
"((du1_power4+du2_power4)\
|(du2_power4+du3_power4)\
|(du3_power4+du4_power4)\
|(du4_power4+du1_power4)),\
((iu1_power4,nothing,iu2_power4)\
|(iu2_power4,nothing,iu2_power4)\
|(iu2_power4,nothing,iu1_power4)\
|(iu1_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-three" 2
(and (eq_attr "type" "three")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\
|du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\
((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
|(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
|(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
|(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
(define_insn_reservation "power4-insert" 4
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,nothing,iu2_power4)\
|(iu2_power4,nothing,iu2_power4)\
|(iu2_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-cmp" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"iq_power4")
(define_insn_reservation "power4-compare" 2
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,iu2_power4)\
|(iu2_power4,iu2_power4)\
|(iu2_power4,iu1_power4))")
(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul-cmp" 7
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*6,iu2_power4)\
|(iu2_power4*6,iu2_power4)\
|(iu2_power4*6,iu1_power4))")
(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-imul-cmp" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*4,iu2_power4)\
|(iu2_power4*4,iu2_power4)\
|(iu2_power4*4,iu1_power4))")
(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul" 7
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*6|iu2_power4*6)")
(define_insn_reservation "power4-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*4|iu2_power4*4)")
(define_insn_reservation "power4-imul3" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*3|iu2_power4*3)")
; SPR move only executes in first IU.
; Integer division only executes in second IU.
(define_insn_reservation "power4-idiv" 36
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,iu2_power4*35")
(define_insn_reservation "power4-ldiv" 68
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,iu2_power4*67")
(define_insn_reservation "power4-mtjmpr" 3
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "power4"))
"du1_power4,bpu_power4")
; Branches take dispatch Slot 4. The presence_sets prevent other insn from
; grabbing previous dispatch slots once this is assigned.
(define_insn_reservation "power4-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power4"))
"(du5_power4\
|du4_power4+du5_power4\
|du3_power4+du4_power4+du5_power4\
|du2_power4+du3_power4+du4_power4+du5_power4\
|du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
; Condition Register logical ops are split if non-destructive (RT != RB)
(define_insn_reservation "power4-crlogical" 2
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power4"))
"du1_power4,cru_power4")
(define_insn_reservation "power4-delayedcr" 4
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4,cru_power4,cru_power4")
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
(define_insn_reservation "power4-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
cru_power4,cru_power4,cru_power4")
; mfcrf (1 field)
(define_insn_reservation "power4-mfcrf" 3
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power4"))
"du1_power4,cru_power4")
; mtcrf (1 field)
(define_insn_reservation "power4-mtcr" 4
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power4"))
"du1_power4,iu1_power4")
; Basic FP latency is 6 cycles
(define_insn_reservation "power4-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power4"))
"fpq_power4")
(define_insn_reservation "power4-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power4"))
"fpq_power4")
(define_insn_reservation "power4-sdiv" 33
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(fpu1_power4*28|fpu2_power4*28)")
(define_insn_reservation "power4-sqrt" 40
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(fpu1_power4*35|fpu2_power4*35)")
(define_insn_reservation "power4-isync" 2
(and (eq_attr "type" "isync")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4")
; VMX
(define_insn_reservation "power4-vecsimple" 2
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power4"))
"vq_power4")
(define_insn_reservation "power4-veccomplex" 5
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "power4"))
"vq_power4")
; vecfp compare
(define_insn_reservation "power4-veccmp" 8
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power4"))
"vq_power4")
(define_insn_reservation "power4-vecfloat" 8
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "power4"))
"vq_power4")
(define_insn_reservation "power4-vecperm" 2
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "power4"))
"vpq_power4")
(define_bypass 4 "power4-vecload" "power4-vecperm")
(define_bypass 3 "power4-vecsimple" "power4-vecperm")
(define_bypass 6 "power4-veccomplex" "power4-vecperm")
(define_bypass 3 "power4-vecperm"
"power4-vecsimple,power4-veccomplex,power4-vecfloat")
(define_bypass 9 "power4-vecfloat" "power4-vecperm")
(define_bypass 5 "power4-vecsimple,power4-veccomplex"
"power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
(define_bypass 7 "power4-veccomplex" "power4-vecstore")
(define_bypass 10 "power4-vecfloat" "power4-vecstore")

351
gcc/config/powerpcspe/power5.md
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@ -1,351 +0,0 @@
;; Scheduling description for IBM POWER5 processor.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Sources: IBM Red Book and White Paper on POWER5
;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
;; Instructions that update more than one register get broken into two
;; (split) or more internal ops. The chip can issue up to 5
;; internal ops per cycle.
(define_automaton "power5iu,power5fpu,power5misc")
(define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
(define_cpu_unit "bpu_power5,cru_power5" "power5misc")
(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
"power5misc")
(define_reservation "lsq_power5"
"(du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\
|(du3_power5,lsu2_power5)\
|(du4_power5,lsu1_power5)")
(define_reservation "iq_power5"
"(du1_power5|du2_power5|du3_power5|du4_power5),\
(iu1_power5|iu2_power5)")
(define_reservation "fpq_power5"
"(du1_power5|du2_power5|du3_power5|du4_power5),\
(fpu1_power5|fpu2_power5)")
; Dispatch slots are allocated in order conforming to program order.
(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
(absence_set "du3_power5" "du4_power5,du5_power5")
(absence_set "du4_power5" "du5_power5")
; Load/store
(define_insn_reservation "power5-load" 4 ; 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power5"))
"lsq_power5")
(define_insn_reservation "power5-load-ext" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-ext-update-indexed" 5
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
(define_insn_reservation "power5-load-update-indexed" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5")
(define_insn_reservation "power5-load-update" 4 ; 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-fpload" 6 ; 5
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power5"))
"lsq_power5")
(define_insn_reservation "power5-fpload-update" 6 ; 5
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5")
(define_insn_reservation "power5-store" 12
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\
|(du3_power5,lsu2_power5)\
|(du4_power5,lsu1_power5)),\
(iu1_power5|iu2_power5)")
(define_insn_reservation "power5-store-update" 12
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
(define_insn_reservation "power5-store-update-indexed" 12
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
(define_insn_reservation "power5-fpstore" 12
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power5"))
"((du1_power5,lsu1_power5)\
|(du2_power5,lsu2_power5)\
|(du3_power5,lsu2_power5)\
|(du4_power5,lsu1_power5)),\
(fpu1_power5|fpu2_power5)")
(define_insn_reservation "power5-fpstore-update" 12
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
(define_insn_reservation "power5-llsc" 11
(and (eq_attr "type" "load_l,store_c,sync")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
lsu1_power5")
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,isel,popcnt")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power5"))
"iq_power5")
(define_insn_reservation "power5-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power5"))
"((du1_power5+du2_power5)\
|(du2_power5+du3_power5)\
|(du3_power5+du4_power5)\
|(du4_power5+du1_power5)),\
((iu1_power5,nothing,iu2_power5)\
|(iu2_power5,nothing,iu2_power5)\
|(iu2_power5,nothing,iu1_power5)\
|(iu1_power5,nothing,iu1_power5))")
(define_insn_reservation "power5-three" 2
(and (eq_attr "type" "three")
(eq_attr "cpu" "power5"))
"(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
|du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
|(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
|(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
|(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
(define_insn_reservation "power5-insert" 4
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
(define_insn_reservation "power5-cmp" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"iq_power5")
(define_insn_reservation "power5-compare" 2
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")
(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul-cmp" 7
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*6,iu2_power5")
(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-imul-cmp" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*4,iu2_power5")
(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul" 7
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
(define_insn_reservation "power5-imul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
(define_insn_reservation "power5-imul3" 4
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
; SPR move only executes in first IU.
; Integer division only executes in second IU.
(define_insn_reservation "power5-idiv" 36
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu2_power5*35")
(define_insn_reservation "power5-ldiv" 68
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu2_power5*67")
(define_insn_reservation "power5-mtjmpr" 3
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "power5"))
"du1_power5,bpu_power5")
; Branches take dispatch Slot 4. The presence_sets prevent other insn from
; grabbing previous dispatch slots once this is assigned.
(define_insn_reservation "power5-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power5"))
"(du5_power5\
|du4_power5+du5_power5\
|du3_power5+du4_power5+du5_power5\
|du2_power5+du3_power5+du4_power5+du5_power5\
|du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
; Condition Register logical ops are split if non-destructive (RT != RB)
(define_insn_reservation "power5-crlogical" 2
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power5"))
"du1_power5,cru_power5")
(define_insn_reservation "power5-delayedcr" 4
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,cru_power5,cru_power5")
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
(define_insn_reservation "power5-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
cru_power5,cru_power5,cru_power5")
; mfcrf (1 field)
(define_insn_reservation "power5-mfcrf" 3
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power5"))
"du1_power5,cru_power5")
; mtcrf (1 field)
(define_insn_reservation "power5-mtcr" 4
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power5"))
"du1_power5,iu1_power5")
; Basic FP latency is 6 cycles
(define_insn_reservation "power5-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "power5"))
"fpq_power5")
(define_insn_reservation "power5-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power5"))
"fpq_power5")
(define_insn_reservation "power5-sdiv" 33
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),\
(fpu1_power5*28|fpu2_power5*28)")
(define_insn_reservation "power5-sqrt" 40
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),\
(fpu1_power5*35|fpu2_power5*35)")
(define_insn_reservation "power5-isync" 2
(and (eq_attr "type" "isync")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5+du3_power5+du4_power5,\
lsu1_power5")

629
gcc/config/powerpcspe/power6.md
View file

@ -1,629 +0,0 @@
;; Scheduling description for IBM POWER6 processor.
;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Sources:
;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
;; (2 engines per chip). The chip can issue up to 5 internal ops
;; per cycle.
(define_automaton "power6iu,power6lsu,power6fpu,power6bu")
(define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
(define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
(define_cpu_unit "bpu_power6" "power6bu")
(define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
(define_reservation "LS2_power6"
"lsu1_power6+lsu2_power6")
(define_reservation "FPU_power6"
"fpu1_power6|fpu2_power6")
(define_reservation "BRU_power6"
"bpu_power6")
(define_reservation "LSU_power6"
"lsu1_power6|lsu2_power6")
(define_reservation "LSF_power6"
"(lsu1_power6+fpu1_power6)\
|(lsu1_power6+fpu2_power6)\
|(lsu2_power6+fpu1_power6)\
|(lsu2_power6+fpu2_power6)")
(define_reservation "LX2_power6"
"(iu1_power6+iu2_power6+lsu1_power6)\
|(iu1_power6+iu2_power6+lsu2_power6)")
(define_reservation "FX2_power6"
"iu1_power6+iu2_power6")
(define_reservation "X2F_power6"
"(iu1_power6+iu2_power6+fpu1_power6)\
|(iu1_power6+iu2_power6+fpu2_power6)")
(define_reservation "BX2_power6"
"iu1_power6+iu2_power6+bpu_power6")
(define_reservation "LSX_power6"
"(iu1_power6+lsu1_power6)\
|(iu1_power6+lsu2_power6)\
|(iu2_power6+lsu1_power6)\
|(iu2_power6+lsu2_power6)")
(define_reservation "FXU_power6"
"iu1_power6|iu2_power6")
(define_reservation "XLF_power6"
"(iu1_power6+lsu1_power6+fpu1_power6)\
|(iu1_power6+lsu1_power6+fpu2_power6)\
|(iu1_power6+lsu2_power6+fpu1_power6)\
|(iu1_power6+lsu2_power6+fpu2_power6)\
|(iu2_power6+lsu1_power6+fpu1_power6)\
|(iu2_power6+lsu1_power6+fpu2_power6)\
|(iu2_power6+lsu2_power6+fpu1_power6)\
|(iu2_power6+lsu2_power6+fpu2_power6)")
(define_reservation "BRX_power6"
"(bpu_power6+iu1_power6)\
|(bpu_power6+iu2_power6)")
; Load/store
; The default for a value written by a fixed point load
; that is read/written by a subsequent fixed point op.
(define_insn_reservation "power6-load" 2 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power6"))
"LSU_power6")
; define the bypass for the case where the value written
; by a fixed point load is used as the source value on
; a store.
(define_bypass 1 "power6-load,\
power6-load-update,\
power6-load-update-indexed"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-load-ext" 4 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power6"))
"LSU_power6")
; define the bypass for the case where the value written
; by a fixed point load ext is used as the source value on
; a store.
(define_bypass 1 "power6-load-ext,\
power6-load-ext-update,\
power6-load-ext-update-indexed"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-load-update" 2 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-update-indexed" 2 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-ext-update" 4 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-fpload" 1
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-fpload-update" 1
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-store" 14
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-store-update" 14
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-store-update-indexed" 14
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power6"))
"LX2_power6")
(define_insn_reservation "power6-fpstore" 14
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power6"))
"LSF_power6")
(define_insn_reservation "power6-fpstore-update" 14
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power6"))
"XLF_power6")
(define_insn_reservation "power6-larx" 3
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "power6"))
"LS2_power6")
(define_insn_reservation "power6-stcx" 10 ; best case
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "power6"))
"LSX_power6")
(define_insn_reservation "power6-sync" 11 ; N/A
(and (eq_attr "type" "sync")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-integer" 1
(and (ior (eq_attr "type" "integer")
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-isel" 1
(and (eq_attr "type" "isel")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-exts" 1
(and (eq_attr "type" "exts")
(eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-shift" 1
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")
(eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-popcnt" 1
(and (eq_attr "type" "popcnt")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-insert" 1
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"FX2_power6")
(define_insn_reservation "power6-insert-dword" 1
(and (eq_attr "type" "insert")
(eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"FX2_power6")
; define the bypass for the case where the value written
; by a fixed point op is used as the source value on a
; store.
(define_bypass 1 "power6-integer,\
power6-exts,\
power6-shift,\
power6-insert,\
power6-insert-dword"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-cntlz" 2
(and (eq_attr "type" "cntlz")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_bypass 1 "power6-cntlz"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-var-rotate" 4
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-trap" 1 ; N/A
(and (eq_attr "type" "trap")
(eq_attr "cpu" "power6"))
"BRX_power6")
(define_insn_reservation "power6-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "power6"))
"(iu1_power6,iu1_power6)\
|(iu1_power6+iu2_power6,nothing)\
|(iu1_power6,iu2_power6)\
|(iu2_power6,iu1_power6)\
|(iu2_power6,iu2_power6)")
(define_insn_reservation "power6-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "power6"))
"(iu1_power6,iu1_power6,iu1_power6)\
|(iu1_power6,iu1_power6,iu2_power6)\
|(iu1_power6,iu2_power6,iu1_power6)\
|(iu1_power6,iu2_power6,iu2_power6)\
|(iu2_power6,iu1_power6,iu1_power6)\
|(iu2_power6,iu1_power6,iu2_power6)\
|(iu2_power6,iu2_power6,iu1_power6)\
|(iu2_power6,iu2_power6,iu2_power6)\
|(iu1_power6+iu2_power6,iu1_power6)\
|(iu1_power6+iu2_power6,iu2_power6)\
|(iu1_power6,iu1_power6+iu2_power6)\
|(iu2_power6,iu1_power6+iu2_power6)")
(define_insn_reservation "power6-cmp" 1
(and (eq_attr "type" "cmp")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-compare" 1
(and (eq_attr "type" "exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
; define the bypass for the case where the value written
; by a fixed point rec form op is used as the source value
; on a store.
(define_bypass 1 "power6-compare,\
power6-fast-compare"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-delayed-compare" 2 ; N/A
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-var-delayed-compare" 4
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "yes")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-lmul-cmp" 16
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul-cmp" 16
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-lmul" 16
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul" 16
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul3" 16
(and (eq_attr "type" "mul")
(eq_attr "size" "8,16")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_bypass 9 "power6-imul,\
power6-lmul,\
power6-imul-cmp,\
power6-lmul-cmp,\
power6-imul3"
"power6-store,\
power6-store-update,\
power6-store-update-indexed,\
power6-fpstore,\
power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-idiv" 44
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
|(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
; The latency for this bypass is yet to be defined
;(define_bypass ? "power6-idiv"
; "power6-store,\
; power6-store-update,\
; power6-store-update-indexed,\
; power6-fpstore,\
; power6-fpstore-update"
; "rs6000_store_data_bypass_p")
(define_insn_reservation "power6-ldiv" 56
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
|(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
; The latency for this bypass is yet to be defined
;(define_bypass ? "power6-ldiv"
; "power6-store,\
; power6-store-update,\
; power6-store-update-indexed,\
; power6-fpstore,\
; power6-fpstore-update"
; "rs6000_store_data_bypass_p")
(define_insn_reservation "power6-mtjmpr" 2
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "power6"))
"BX2_power6")
(define_bypass 5 "power6-mtjmpr" "power6-branch")
(define_insn_reservation "power6-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_bypass 5 "power6-branch" "power6-mtjmpr")
(define_insn_reservation "power6-crlogical" 3
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_bypass 3 "power6-crlogical" "power6-branch")
(define_insn_reservation "power6-delayedcr" 3
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power6"))
"BRU_power6")
(define_insn_reservation "power6-mfcr" 6 ; N/A
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power6"))
"BX2_power6")
; mfcrf (1 field)
(define_insn_reservation "power6-mfcrf" 3 ; N/A
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power6"))
"BX2_power6") ;
; mtcrf (1 field)
(define_insn_reservation "power6-mtcr" 4 ; N/A
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power6"))
"BX2_power6")
(define_bypass 9 "power6-mtcr" "power6-branch")
(define_insn_reservation "power6-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power6"))
"FPU_power6")
; Any fp instruction that updates a CR has a latency
; of 6 to a dependent branch
(define_bypass 6 "power6-fp" "power6-branch")
(define_bypass 1 "power6-fp"
"power6-fpstore,power6-fpstore-update"
"rs6000_store_data_bypass_p")
(define_insn_reservation "power6-fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 12 "power6-fpcompare"
"power6-branch,power6-crlogical")
(define_insn_reservation "power6-sdiv" 26
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-ddiv" 32
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-sqrt" 30
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-dsqrt" 42
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_insn_reservation "power6-isync" 2 ; N/A
(and (eq_attr "type" "isync")
(eq_attr "cpu" "power6"))
"FXU_power6")
(define_insn_reservation "power6-vecload" 1
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "power6"))
"LSU_power6")
(define_insn_reservation "power6-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power6"))
"LSF_power6")
(define_insn_reservation "power6-vecsimple" 3
(and (eq_attr "type" "vecsimple,veclogical,vecmove")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
power6-vecperm")
(define_bypass 5 "power6-vecsimple" "power6-vecfloat")
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
(define_insn_reservation "power6-veccmp" 1
(and (eq_attr "type" "veccmp,veccmpfx")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-veccmp" "power6-branch")
(define_insn_reservation "power6-vecfloat" 7
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-vecfloat" "power6-vecsimple")
(define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
power6-vecperm")
(define_bypass 9 "power6-vecfloat" "power6-vecstore" )
(define_insn_reservation "power6-veccomplex" 7
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
power6-vecfloat" )
(define_bypass 9 "power6-veccomplex" "power6-vecperm" )
(define_bypass 8 "power6-veccomplex" "power6-vecstore" )
(define_insn_reservation "power6-vecperm" 4
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "power6"))
"FPU_power6")
(define_bypass 7 "power6-vecperm" "power6-vecsimple,\
power6-vecfloat" )
(define_bypass 6 "power6-vecperm" "power6-veccomplex" )
(define_bypass 5 "power6-vecperm" "power6-vecstore" )
(define_insn_reservation "power6-mftgpr" 8
(and (eq_attr "type" "mftgpr")
(eq_attr "cpu" "power6"))
"X2F_power6")
(define_insn_reservation "power6-mffgpr" 14
(and (eq_attr "type" "mffgpr")
(eq_attr "cpu" "power6"))
"LX2_power6")
(define_bypass 4 "power6-mftgpr" "power6-imul,\
power6-lmul,\
power6-imul-cmp,\
power6-lmul-cmp,\
power6-imul3,\
power6-idiv,\
power6-ldiv" )

366
gcc/config/powerpcspe/power7.md
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@ -1,366 +0,0 @@
;; Scheduling description for IBM POWER7 processor.
;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "power7iu,power7lsu,power7vsu,power7misc")
(define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
(define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
(define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
(define_cpu_unit "bpu_power7,cru_power7" "power7misc")
(define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
"power7misc")
(define_reservation "DU_power7"
"du1_power7|du2_power7|du3_power7|du4_power7")
(define_reservation "DU2F_power7"
"du1_power7+du2_power7")
(define_reservation "DU4_power7"
"du1_power7+du2_power7+du3_power7+du4_power7")
(define_reservation "FXU_power7"
"iu1_power7|iu2_power7")
(define_reservation "VSU_power7"
"vsu1_power7|vsu2_power7")
(define_reservation "LSU_power7"
"lsu1_power7|lsu2_power7")
; Dispatch slots are allocated in order conforming to program order.
(absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
(absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
(absence_set "du3_power7" "du4_power7,du5_power7")
(absence_set "du4_power7" "du5_power7")
; LS Unit
(define_insn_reservation "power7-load" 2
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7")
(define_insn_reservation "power7-load-ext" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7,FXU_power7")
(define_insn_reservation "power7-load-update" 2
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-update-indexed" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-load-ext-update" 4
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-load-ext-update-indexed" 4
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7")
(define_insn_reservation "power7-fpload-update" 3
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store" 6 ; store-forwarding latency
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+FXU_power7")
(define_insn_reservation "power7-store-update" 6
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power7"))
"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-store-update-indexed" 6
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7+FXU_power7,FXU_power7")
(define_insn_reservation "power7-fpstore" 6
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7")
(define_insn_reservation "power7-fpstore-update" 6
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+VSU_power7+FXU_power7")
(define_insn_reservation "power7-larx" 3
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7")
(define_insn_reservation "power7-stcx" 10
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7")
(define_insn_reservation "power7-vecload" 3
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7")
(define_insn_reservation "power7-vecstore" 6
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power7"))
"DU_power7,LSU_power7+vsu2_power7")
(define_insn_reservation "power7-sync" 11
(and (eq_attr "type" "sync")
(eq_attr "cpu" "power7"))
"DU4_power7,LSU_power7")
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,isel,popcnt")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-cntlz" 2
(and (eq_attr "type" "cntlz")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power7"))
"DU_power7+DU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "power7"))
"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-cmp" 1
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-compare" 2
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
(define_insn_reservation "power7-mul" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-mul-compare" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
(define_insn_reservation "power7-idiv" 36
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power7"))
"DU2F_power7,iu1_power7*36|iu2_power7*36")
(define_insn_reservation "power7-ldiv" 68
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power7"))
"DU2F_power7,iu1_power7*68|iu2_power7*68")
(define_insn_reservation "power7-isync" 1 ;
(and (eq_attr "type" "isync")
(eq_attr "cpu" "power7"))
"DU4_power7,FXU_power7")
; CR Unit
(define_insn_reservation "power7-mtjmpr" 4
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "power7"))
"du1_power7,FXU_power7")
(define_insn_reservation "power7-mfjmpr" 5
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7+FXU_power7")
(define_insn_reservation "power7-crlogical" 3
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7")
(define_insn_reservation "power7-delayedcr" 3
(and (eq_attr "type" "delayed_cr")
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7")
(define_insn_reservation "power7-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7")
(define_insn_reservation "power7-mfcrf" 3
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power7"))
"du1_power7,cru_power7")
(define_insn_reservation "power7-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power7"))
"DU4_power7,cru_power7+FXU_power7")
; BR Unit
; Branches take dispatch Slot 4. The presence_sets prevent other insn from
; grabbing previous dispatch slots once this is assigned.
(define_insn_reservation "power7-branch" 3
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power7"))
"(du5_power7\
|du4_power7+du5_power7\
|du3_power7+du4_power7+du5_power7\
|du2_power7+du3_power7+du4_power7+du5_power7\
|du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
; VS Unit (includes FP/VSX/VMX/DFP)
(define_insn_reservation "power7-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_bypass 8 "power7-fp" "power7-branch")
(define_insn_reservation "power7-fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-sdiv" 27
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-sqrt" 32
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-dsqrt" 44
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-vecsimple" 2
(and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
(define_insn_reservation "power7-vecfloat" 6
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
(define_bypass 7 "power7-vecfloat" "power7-vecsimple,power7-veccomplex,\
power7-vecperm")
(define_insn_reservation "power7-veccomplex" 7
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "power7"))
"DU_power7,vsu1_power7")
(define_insn_reservation "power7-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "power7"))
"DU_power7,vsu2_power7")
(define_insn_reservation "power7-vecdouble" 6
(and (eq_attr "type" "vecdouble")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_bypass 7 "power7-vecdouble" "power7-vecsimple,power7-veccomplex,\
power7-vecperm")
(define_insn_reservation "power7-vecfdiv" 26
(and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")
(define_insn_reservation "power7-vecdiv" 32
(and (eq_attr "type" "vecdiv")
(eq_attr "cpu" "power7"))
"DU_power7,VSU_power7")

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gcc/config/powerpcspe/power8.md
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@ -1,396 +0,0 @@
;; Scheduling description for IBM POWER8 processor.
;; Copyright (C) 2013-2018 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "power8fxu,power8lsu,power8vsu,power8misc")
(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu")
(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu")
(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu")
(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu")
(define_cpu_unit "bpu_power8,cru_power8" "power8misc")
(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\
du5_power8,du6_power8" "power8misc")
; Dispatch group reservations
(define_reservation "DU_any_power8"
"du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\
du5_power8")
; 2-way Cracked instructions go in slots 0-1
; (can also have a second in slots 3-4 if insns are adjacent)
(define_reservation "DU_cracked_power8"
"du0_power8+du1_power8")
; Insns that are first in group
(define_reservation "DU_first_power8"
"du0_power8")
; Insns that are first and last in group
(define_reservation "DU_both_power8"
"du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\
du5_power8+du6_power8")
; Dispatch slots are allocated in order conforming to program order.
(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\
du5_power8,du6_power8")
(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\
du6_power8")
(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8")
(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8")
(absence_set "du4_power8" "du5_power8,du6_power8")
(absence_set "du5_power8" "du6_power8")
; Execution unit reservations
(define_reservation "FXU_power8"
"fxu0_power8|fxu1_power8")
(define_reservation "LU_power8"
"lu0_power8|lu1_power8")
(define_reservation "LSU_power8"
"lsu0_power8|lsu1_power8")
(define_reservation "LU_or_LSU_power8"
"lu0_power8|lu1_power8|lsu0_power8|lsu1_power8")
(define_reservation "VSU_power8"
"vsu0_power8|vsu1_power8")
; LS Unit
(define_insn_reservation "power8-load" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,LU_or_LSU_power8")
(define_insn_reservation "power8-load-update" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
(define_insn_reservation "power8-load-ext" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
(define_insn_reservation "power8-load-ext-update" 3
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
(define_insn_reservation "power8-fpload" 5
(and (ior (eq_attr "type" "vecload")
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,LU_power8")
(define_insn_reservation "power8-fpload-update" 5
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_power8+FXU_power8")
(define_insn_reservation "power8-store" 5 ; store-forwarding latency
(and (eq_attr "type" "store")
(not (and (eq_attr "update" "yes")
(eq_attr "indexed" "yes")))
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-store-update-indexed" 5
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-fpstore" 5
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-fpstore-update" 5
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-vecstore" 5
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-larx" 3
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "power8"))
"DU_both_power8,LU_or_LSU_power8")
(define_insn_reservation "power8-stcx" 10
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "power8"))
"DU_both_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-sync" 1
(and (eq_attr "type" "sync,isync")
(eq_attr "cpu" "power8"))
"DU_both_power8,LSU_power8")
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (ior (eq_attr "type" "integer,insert,trap,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
; Extra cycle to LU/LSU
(define_bypass 2 "power8-1cyc"
"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
power8-vecstore,power8-larx,power8-stcx")
; "power8-load,power8-load-update,power8-load-ext,\
; power8-load-ext-update,power8-fpload,power8-fpload-update,\
; power8-store,power8-store-update,power8-store-update-indexed,\
; power8-fpstore,power8-fpstore-update,power8-vecstore,\
; power8-larx,power8-stcx")
(define_insn_reservation "power8-2cyc" 2
(and (eq_attr "type" "cntlz,popcnt")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
(define_insn_reservation "power8-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power8"))
"DU_any_power8+DU_any_power8,FXU_power8,FXU_power8")
(define_insn_reservation "power8-three" 3
(and (eq_attr "type" "three")
(eq_attr "cpu" "power8"))
"DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8")
; cmp - Normal compare insns
(define_insn_reservation "power8-cmp" 2
(and (eq_attr "type" "cmp")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
; add/logical with dot : add./and./nor./etc
(define_insn_reservation "power8-fast-compare" 2
(and (eq_attr "type" "add,logical")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
; exts/shift with dot : rldicl./exts./rlwinm./slwi./rlwnm./slw./etc
(define_insn_reservation "power8-compare" 2
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8,FXU_power8")
; Extra cycle to LU/LSU
(define_bypass 3 "power8-fast-compare,power8-compare"
"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
power8-vecstore,power8-larx,power8-stcx")
; 5 cycle CR latency
(define_bypass 5 "power8-fast-compare,power8-compare"
"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
(define_insn_reservation "power8-mul" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
(define_insn_reservation "power8-mul-compare" 4
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8")
; Extra cycle to LU/LSU
(define_bypass 5 "power8-mul,power8-mul-compare"
"power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\
power8-vecstore,power8-larx,power8-stcx")
; 7 cycle CR latency
(define_bypass 7 "power8-mul,power8-mul-compare"
"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
; FXU divides are not pipelined
(define_insn_reservation "power8-idiv" 37
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power8"))
"DU_any_power8,fxu0_power8*37|fxu1_power8*37")
(define_insn_reservation "power8-ldiv" 68
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power8"))
"DU_any_power8,fxu0_power8*68|fxu1_power8*68")
(define_insn_reservation "power8-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "power8"))
"DU_first_power8,FXU_power8")
; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode
(define_insn_reservation "power8-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power8"))
"DU_both_power8,FXU_power8")
; CR Unit
(define_insn_reservation "power8-mfjmpr" 5
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "power8"))
"DU_first_power8,cru_power8+FXU_power8")
(define_insn_reservation "power8-crlogical" 3
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "power8"))
"DU_first_power8,cru_power8")
(define_insn_reservation "power8-mfcr" 5
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power8"))
"DU_both_power8,cru_power8")
(define_insn_reservation "power8-mfcrf" 3
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power8"))
"DU_first_power8,cru_power8")
; BR Unit
; Branches take dispatch slot 7, but reserve any remaining prior slots to
; prevent other insns from grabbing them once this is assigned.
(define_insn_reservation "power8-branch" 3
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power8"))
"(du6_power8\
|du5_power8+du6_power8\
|du4_power8+du5_power8+du6_power8\
|du3_power8+du4_power8+du5_power8+du6_power8\
|du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
|du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\
|du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\
du6_power8),bpu_power8")
; Branch updating LR/CTR feeding mf[lr|ctr]
(define_bypass 4 "power8-branch" "power8-mfjmpr")
; VS Unit (includes FP/VSX/VMX/DFP/Crypto)
(define_insn_reservation "power8-fp" 6
(and (eq_attr "type" "fp,fpsimple,dmul,dfp")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
; Additional 3 cycles for any CR result
(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch")
(define_insn_reservation "power8-fpcompare" 8
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-sdiv" 27
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-sqrt" 32
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-dsqrt" 44
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecsimple" 2
(and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp,
veccmpfx")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecnormal" 6
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_bypass 7 "power8-vecnormal"
"power8-vecsimple,power8-veccomplex,power8-fpstore*,\
power8-vecstore")
(define_insn_reservation "power8-veccomplex" 7
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecfdiv" 25
(and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-vecdiv" 31
(and (eq_attr "type" "vecdiv")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-mffgpr" 5
(and (eq_attr "type" "mffgpr")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-mftgpr" 6
(and (eq_attr "type" "mftgpr")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")
(define_insn_reservation "power8-crypto" 7
(and (eq_attr "type" "crypto")
(eq_attr "cpu" "power8"))
"DU_any_power8,VSU_power8")

489
gcc/config/powerpcspe/power9.md
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@ -1,489 +0,0 @@
;; Scheduling description for IBM POWER9 processor.
;; Copyright (C) 2016-2018 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "power9dsp,power9lsu,power9vsu,power9misc")
(define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu")
(define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu")
; Two vector permute units, part of vsu
(define_cpu_unit "prm0_power9,prm1_power9" "power9vsu")
; Two fixed point divide units, not pipelined
(define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc")
(define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc")
(define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9,
x2_power9,x3_power9,xb0_power9,xb1_power9,
br0_power9,br1_power9" "power9dsp")
; Dispatch port reservations
;
; Power9 can dispatch a maximum of 6 iops per cycle with the following
; general restrictions (other restrictions also apply):
; 1) At most 2 iops per execution slice
; 2) At most 2 iops to the branch unit
; Note that insn position in a dispatch group of 6 insns does not infer which
; execution slice the insn is routed to. The units are used to infer the
; conflicts that exist (i.e. an 'even' requirement will preclude dispatch
; with 2 insns with 'superslice' requirement).
; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but
; are listed as separate units to allow those insns that preclude its use to
; still be scheduled two to a superslice while reserving the 3rd slot. The
; same applies for xb0/xb1.
(define_reservation "DU_xa_power9" "xa0_power9+xa1_power9")
(define_reservation "DU_xb_power9" "xb0_power9+xb1_power9")
; Any execution slice dispatch
(define_reservation "DU_any_power9"
"x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9|
DU_xb_power9")
; Even slice, actually takes even/odd slots
(define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9")
; Slice plus 3rd slot
(define_reservation "DU_slice_3_power9"
"x0_power9+xa0_power9|x1_power9+xa1_power9|
x2_power9+xb0_power9|x3_power9+xb1_power9")
; Superslice
(define_reservation "DU_super_power9"
"x0_power9+x1_power9|x2_power9+x3_power9")
; 2-way cracked
(define_reservation "DU_C2_power9" "x0_power9+x1_power9|
x1_power9+DU_xa_power9|
x1_power9+x2_power9|
DU_xa_power9+x2_power9|
x2_power9+x3_power9|
x3_power9+DU_xb_power9")
; 2-way cracked plus 3rd slot
(define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9|
x1_power9+x2_power9+xa0_power9|
x1_power9+x2_power9+xb0_power9|
x2_power9+x3_power9+xb0_power9")
; 3-way cracked (consumes whole decode/dispatch cycle)
(define_reservation "DU_C3_power9"
"x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+
x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9")
; Branch ports
(define_reservation "DU_branch_power9" "br0_power9|br1_power9")
; Execution unit reservations
(define_reservation "LSU_power9"
"lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9")
(define_reservation "LSU_pair_power9"
"lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9|
lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9")
(define_reservation "VSU_power9"
"vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9")
(define_reservation "VSU_super_power9"
"vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9")
(define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9")
; LS Unit
(define_insn_reservation "power9-load" 4
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "no")
(eq_attr "cpu" "power9"))
"DU_any_power9,LSU_power9")
(define_insn_reservation "power9-load-update" 4
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "no")
(eq_attr "update" "yes")
(eq_attr "cpu" "power9"))
"DU_C2_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-load-ext" 6
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "no")
(eq_attr "cpu" "power9"))
"DU_C2_power9,LSU_power9")
(define_insn_reservation "power9-load-ext-update" 6
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")
(eq_attr "update" "yes")
(eq_attr "cpu" "power9"))
"DU_C3_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-fpload-double" 4
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,LSU_power9")
(define_insn_reservation "power9-fpload-update-double" 4
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9+VSU_power9")
; SFmode loads are cracked and have additional 2 cycles over DFmode
(define_insn_reservation "power9-fpload-single" 6
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9")
(define_insn_reservation "power9-fpload-update-single" 6
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
(eq_attr "cpu" "power9"))
"DU_C3_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-vecload" 5
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "power9"))
"DU_any_power9,LSU_pair_power9")
; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store
(define_insn_reservation "power9-store" 0
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,LSU_power9")
(define_insn_reservation "power9-store-indexed" 0
(and (eq_attr "type" "store")
(eq_attr "update" "no")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,LSU_power9")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power9-store-update" 2
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "no")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9+VSU_power9")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power9-store-update-indexed" 2
(and (eq_attr "type" "store")
(eq_attr "update" "yes")
(eq_attr "indexed" "yes")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-fpstore" 0
(and (eq_attr "type" "fpstore")
(eq_attr "update" "no")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,LSU_power9")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power9-fpstore-update" 2
(and (eq_attr "type" "fpstore")
(eq_attr "update" "yes")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-vecstore" 0
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power9"))
"DU_super_power9,LSU_pair_power9")
(define_insn_reservation "power9-larx" 4
(and (eq_attr "type" "load_l")
(eq_attr "cpu" "power9"))
"DU_any_power9,LSU_power9")
(define_insn_reservation "power9-stcx" 2
(and (eq_attr "type" "store_c")
(eq_attr "cpu" "power9"))
"DU_C2_3_power9,LSU_power9+VSU_power9")
(define_insn_reservation "power9-sync" 4
(and (eq_attr "type" "sync,isync")
(eq_attr "cpu" "power9"))
"DU_any_power9,LSU_power9")
; VSU Execution Unit
; Fixed point ops
; Most ALU insns are simple 2 cycle, including record form
(define_insn_reservation "power9-alu" 2
(and (ior (eq_attr "type" "add,exts,integer,logical,isel")
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; 5 cycle CR latency
(define_bypass 5 "power9-alu"
"power9-crlogical,power9-mfcr,power9-mfcrf")
; Record form rotate/shift are cracked
(define_insn_reservation "power9-cracked-alu" 2
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power9"))
"DU_C2_power9,VSU_power9")
; 7 cycle CR latency
(define_bypass 7 "power9-cracked-alu"
"power9-crlogical,power9-mfcr,power9-mfcrf")
(define_insn_reservation "power9-alu2" 3
(and (eq_attr "type" "cntlz,popcnt,trap")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; 6 cycle CR latency
(define_bypass 6 "power9-alu2"
"power9-crlogical,power9-mfcr,power9-mfcrf")
(define_insn_reservation "power9-cmp" 2
(and (eq_attr "type" "cmp")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; Treat 'two' and 'three' types as 2 or 3 way cracked
(define_insn_reservation "power9-two" 4
(and (eq_attr "type" "two")
(eq_attr "cpu" "power9"))
"DU_C2_power9,VSU_power9")
(define_insn_reservation "power9-three" 6
(and (eq_attr "type" "three")
(eq_attr "cpu" "power9"))
"DU_C3_power9,VSU_power9")
(define_insn_reservation "power9-mul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
(define_insn_reservation "power9-mul-compare" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
(eq_attr "cpu" "power9"))
"DU_C2_power9,VSU_power9")
; 10 cycle CR latency
(define_bypass 10 "power9-mul-compare"
"power9-crlogical,power9-mfcr,power9-mfcrf")
; Fixed point divides reserve the divide units for a minimum of 8 cycles
(define_insn_reservation "power9-idiv" 16
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "power9"))
"DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
(define_insn_reservation "power9-ldiv" 24
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "power9"))
"DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
(define_insn_reservation "power9-crlogical" 2
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
(define_insn_reservation "power9-mfcrf" 2
(and (eq_attr "type" "mfcrf")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
(define_insn_reservation "power9-mfcr" 6
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "power9"))
"DU_C3_power9,VSU_power9")
; Should differentiate between 1 cr field and > 1 since target of > 1 cr
; is cracked
(define_insn_reservation "power9-mtcr" 2
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; Move to LR/CTR are executed in VSU
(define_insn_reservation "power9-mtjmpr" 5
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; Floating point/Vector ops
(define_insn_reservation "power9-fpsimple" 2
(and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-fp" 7
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-fpcompare" 3
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other
; divide insns, but for the most part do not block pipelined ops.
(define_insn_reservation "power9-sdiv" 22
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-ddiv" 33
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-sqrt" 26
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-dsqrt" 36
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-vec-2cyc" 2
(and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-veccmp" 3
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-vecsimple" 3
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-vecnormal" 7
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "!128")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
; Quad-precision FP ops, execute in DFU
(define_insn_reservation "power9-qp" 12
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "128")
(eq_attr "cpu" "power9"))
"DU_super_power9,dfu_power9")
(define_insn_reservation "power9-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_PRM_power9")
(define_insn_reservation "power9-veccomplex" 7
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-vecfdiv" 28
(and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-vecdiv" 32
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "!128")
(eq_attr "cpu" "power9"))
"DU_super_power9,VSU_super_power9")
(define_insn_reservation "power9-qpdiv" 56
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "128")
(eq_attr "cpu" "power9"))
"DU_super_power9,dfu_power9")
(define_insn_reservation "power9-mffgpr" 2
(and (eq_attr "type" "mffgpr")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
(define_insn_reservation "power9-mftgpr" 2
(and (eq_attr "type" "mftgpr")
(eq_attr "cpu" "power9"))
"DU_slice_3_power9,VSU_power9")
; Branch Unit
; Move from LR/CTR are executed in BRU but consume a writeback port from an
; execution slice.
(define_insn_reservation "power9-mfjmpr" 6
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "power9"))
"DU_branch_power9,bru_power9+VSU_power9")
; Branch is 2 cycles
(define_insn_reservation "power9-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power9"))
"DU_branch_power9,bru_power9")
; Crypto Unit
(define_insn_reservation "power9-crypto" 6
(and (eq_attr "type" "crypto")
(eq_attr "cpu" "power9"))
"DU_super_power9,cryptu_power9")
; HTM Unit
(define_insn_reservation "power9-htm" 4
(and (eq_attr "type" "htm")
(eq_attr "cpu" "power9"))
"DU_C2_power9,LSU_power9")
(define_insn_reservation "power9-htm-simple" 2
(and (eq_attr "type" "htmsimple")
(eq_attr "cpu" "power9"))
"DU_any_power9,VSU_power9")
; DFP Unit
(define_insn_reservation "power9-dfp" 12
(and (eq_attr "type" "dfp")
(eq_attr "cpu" "power9"))
"DU_even_power9,dfu_power9")

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gcc/config/powerpcspe/powerpcspe-builtin.def
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gcc/config/powerpcspe/powerpcspe-c.c
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gcc/config/powerpcspe/powerpcspe-cpus.def
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/* IBM RS/6000 CPU names..
Copyright (C) 1991-2018 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* ISA masks. */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS OPTION_MASK_MFCRF
#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
/* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
fre, fsqrt, etc. were no longer documented as optional. Group masks by
server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
| OPTION_MASK_CMPB \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT)
#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
/* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
PR 58587 is fixed. */
#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX \
| OPTION_MASK_UPPER_REGS_DI \
| OPTION_MASK_UPPER_REGS_DF)
/* For now, don't provide an embedded version of ISA 2.07. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR)
/* Support for the IEEE 128-bit floating point hardware requires a lot of the
VSX instructions that are part of ISA 3.0. */
#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_UPPER_REGS_DI \
| OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_MINMAX)
/* Flags that need to be turned off if -mno-power8-vector. */
#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_UPPER_REGS_SF) \
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_UPPER_REGS_DI \
| OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
/* Deal with ports that do not have -mstrict-align. */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_FPRND \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LRA \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MFPGPR \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_POPCNTB \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_POWERPC64 \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
| OPTION_MASK_UPPER_REGS_DI \
| OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#endif
/* This table occasionally claims that a processor does not support a
particular feature even though it does, but the feature is slower than the
alternative. Thus, it shouldn't be relied on as a complete description of
the processor's support.
Please keep this list in order, and don't forget to update the documentation
in invoke.texi when adding a new processor or flag.
Before including this file, define a macro:
RS6000_CPU (NAME, CPU, FLAGS)
where the arguments are the fields of struct rs6000_ptt. */
RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
| MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
| MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
| MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
| MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
| OPTION_MASK_UPPER_REGS_DI)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)

45
gcc/config/powerpcspe/powerpcspe-d.c
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@ -1,45 +0,0 @@
/* Subroutines for the D front end on the PowerPC architecture.
Copyright (C) 2017-2018 Free Software Foundation, Inc.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "d/d-target.h"
#include "d/d-target-def.h"
/* Implement TARGET_D_CPU_VERSIONS for PowerPC targets. */
void
rs6000_d_target_versions (void)
{
if (TARGET_64BIT)
d_add_builtin_version ("PPC64");
else
d_add_builtin_version ("PPC");
if (TARGET_HARD_FLOAT)
{
d_add_builtin_version ("PPC_HardFloat");
d_add_builtin_version ("D_HardFloat");
}
else if (TARGET_SOFT_FLOAT)
{
d_add_builtin_version ("PPC_SoftFloat");
d_add_builtin_version ("D_SoftFloat");
}
}

38
gcc/config/powerpcspe/powerpcspe-linux.c
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@ -1,38 +0,0 @@
/* Functions for Linux on PowerPC.
Copyright (C) 2013-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
/* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
bool
rs6000_linux_float_exceptions_rounding_supported_p (void)
{
/* glibc has support for exceptions and rounding modes for software
floating point. */
if (OPTION_GLIBC)
return true;
else
return TARGET_DF_INSN;
}

56
gcc/config/powerpcspe/powerpcspe-modes.def
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@ -1,56 +0,0 @@
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* IBM 128-bit floating point. IFmode and KFmode use the fractional float
support in order to declare 3 128-bit floating point types. */
FRACTIONAL_FLOAT_MODE (IF, 106, 16, ibm_extended_format);
/* Explicit IEEE 128-bit floating point. */
FRACTIONAL_FLOAT_MODE (KF, 113, 16, ieee_quad_format);
/* 128-bit floating point. ABI_V4 uses IEEE quad, AIX/Darwin
adjust this in rs6000_option_override_internal. */
FLOAT_MODE (TF, 16, ieee_quad_format);
/* Add any extra modes needed to represent the condition code.
For the RS/6000, we need separate modes when unsigned (logical) comparisons
are being done and we need a separate mode for floating-point. We also
use a mode for the case when we are comparing the results of two
comparisons, as then only the EQ bit is valid in the register. */
CC_MODE (CCUNS);
CC_MODE (CCFP);
CC_MODE (CCEQ);
/* Vector modes. */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
VECTOR_MODE (INT, DI, 1);
VECTOR_MODE (INT, TI, 1);
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
/* Replacement for TImode that only is allowed in GPRs. We also use PTImode
for quad memory atomic operations to force getting an even/odd register
combination. */
PARTIAL_INT_MODE (TI, 128, PTI);

168
gcc/config/powerpcspe/powerpcspe-opts.h
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@ -1,168 +0,0 @@
/* Definitions of target machine needed for option handling for GNU compiler,
for IBM RS/6000.
Copyright (C) 2010-2018 Free Software Foundation, Inc.
Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef RS6000_OPTS_H
#define RS6000_OPTS_H
/* Processor type. Order must match cpu attribute in MD file. */
enum processor_type
{
PROCESSOR_PPC601,
PROCESSOR_PPC603,
PROCESSOR_PPC604,
PROCESSOR_PPC604e,
PROCESSOR_PPC620,
PROCESSOR_PPC630,
PROCESSOR_PPC750,
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC403,
PROCESSOR_PPC405,
PROCESSOR_PPC440,
PROCESSOR_PPC476,
PROCESSOR_PPC8540,
PROCESSOR_PPC8548,
PROCESSOR_PPCE300C2,
PROCESSOR_PPCE300C3,
PROCESSOR_PPCE500MC,
PROCESSOR_PPCE500MC64,
PROCESSOR_PPCE5500,
PROCESSOR_PPCE6500,
PROCESSOR_POWER4,
PROCESSOR_POWER5,
PROCESSOR_POWER6,
PROCESSOR_POWER7,
PROCESSOR_POWER8,
PROCESSOR_POWER9,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
PROCESSOR_PPCA2,
PROCESSOR_TITAN
};
/* FP processor type. */
enum fpu_type_t
{
FPU_NONE, /* No FPU */
FPU_SF_LITE, /* Limited Single Precision FPU */
FPU_DF_LITE, /* Limited Double Precision FPU */
FPU_SF_FULL, /* Full Single Precision FPU */
FPU_DF_FULL /* Full Double Single Precision FPU */
};
/* Types of costly dependences. */
enum rs6000_dependence_cost
{
max_dep_latency = 1000,
no_dep_costly,
all_deps_costly,
true_store_to_load_dep_costly,
store_to_load_dep_costly
};
/* Types of nop insertion schemes in sched target hook sched_finish. */
enum rs6000_nop_insertion
{
sched_finish_regroup_exact = 1000,
sched_finish_pad_groups,
sched_finish_none
};
/* Dispatch group termination caused by an insn. */
enum group_termination
{
current_group,
previous_group
};
/* Enumeration to give which calling sequence to use. */
enum rs6000_abi {
ABI_NONE,
ABI_AIX, /* IBM's AIX, or Linux ELFv1 */
ABI_ELFv2, /* Linux ELFv2 ABI */
ABI_V4, /* System V.4/eabi */
ABI_DARWIN /* Apple's Darwin (OS X kernel) */
};
/* Small data support types. */
enum rs6000_sdata_type {
SDATA_NONE, /* No small data support. */
SDATA_DATA, /* Just put data in .sbss/.sdata, don't use relocs. */
SDATA_SYSV, /* Use r13 to point to .sdata/.sbss. */
SDATA_EABI /* Use r13 like above, r2 points to .sdata2/.sbss2. */
};
/* Type of traceback to use. */
enum rs6000_traceback_type {
traceback_default = 0,
traceback_none,
traceback_part,
traceback_full
};
/* Code model for 64-bit linux.
small: 16-bit toc offsets.
medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
large: 32-bit toc offsets, no limit on static data and code. */
enum rs6000_cmodel {
CMODEL_SMALL,
CMODEL_MEDIUM,
CMODEL_LARGE
};
/* Describe which vector unit to use for a given machine mode. The
VECTOR_MEM_* and VECTOR_UNIT_* macros assume that Altivec, VSX, and
P8_VECTOR are contiguous. */
enum rs6000_vector {
VECTOR_NONE, /* Type is not a vector or not supported */
VECTOR_ALTIVEC, /* Use altivec for vector processing */
VECTOR_VSX, /* Use VSX for vector processing */
VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */
VECTOR_PAIRED, /* Use paired floating point for vectors */
VECTOR_SPE, /* Use SPE for vector processing */
VECTOR_OTHER /* Some other vector unit */
};
/* Where to get the canary for the stack protector. */
enum stack_protector_guard {
SSP_TLS, /* per-thread canary in TLS block */
SSP_GLOBAL /* global canary */
};
/* No enumeration is defined to index the -mcpu= values (entries in
processor_target_table), with the type int being used instead, but
we need to distinguish the special "native" value. */
#define RS6000_CPU_OPTION_NATIVE -1
#endif

27
gcc/config/powerpcspe/powerpcspe-passes.def
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@ -1,27 +0,0 @@
/* Description of target passes for rs6000
Copyright (C) 2016-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/*
Macros that can be used in this file:
INSERT_PASS_AFTER (PASS, INSTANCE, TGT_PASS)
INSERT_PASS_BEFORE (PASS, INSTANCE, TGT_PASS)
REPLACE_PASS (PASS, INSTANCE, TGT_PASS)
*/
INSERT_PASS_BEFORE (pass_cse, 1, pass_analyze_swaps);

258
gcc/config/powerpcspe/powerpcspe-protos.h
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@ -1,258 +0,0 @@
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
Copyright (C) 2000-2018 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_RS6000_PROTOS_H
#define GCC_RS6000_PROTOS_H
/* Declare functions in rs6000.c */
#ifdef RTX_CODE
#ifdef TREE_CODE
extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
tree, machine_mode);
#endif /* TREE_CODE */
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
extern int num_insns_constant (rtx, machine_mode);
extern int num_insns_constant_wide (HOST_WIDE_INT);
extern int small_data_operand (rtx, machine_mode);
extern bool mem_operand_gpr (rtx, machine_mode);
extern bool mem_operand_ds_form (rtx, machine_mode);
extern bool toc_relative_expr_p (const_rtx, bool);
extern bool invalid_e500_subreg (rtx, machine_mode);
extern void validate_condition_mode (enum rtx_code, machine_mode);
extern bool legitimate_constant_pool_address_p (const_rtx, machine_mode,
bool);
extern bool legitimate_indirect_address_p (rtx, int);
extern bool legitimate_indexed_address_p (rtx, int);
extern bool avoiding_indexed_address_p (machine_mode);
extern rtx rs6000_got_register (rtx);
extern rtx find_addr_reg (rtx);
extern rtx gen_easy_altivec_constant (rtx);
extern const char *output_vec_const_move (rtx *);
extern const char *rs6000_output_move_128bit (rtx *);
extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void rs6000_expand_vector_init (rtx, rtx);
extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int);
extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
extern void rs6000_split_v4si_init (rtx []);
extern void altivec_expand_vec_perm_le (rtx op[4]);
extern void altivec_expand_lvx_be (rtx, rtx, machine_mode, unsigned);
extern void altivec_expand_stvx_be (rtx, rtx, machine_mode, unsigned);
extern void altivec_expand_stvex_be (rtx, rtx, machine_mode, unsigned);
extern void rs6000_expand_extract_even (rtx, rtx, rtx);
extern void rs6000_expand_interleave (rtx, rtx, rtx, bool);
extern void rs6000_scale_v2df (rtx, rtx, int);
extern int expand_block_clear (rtx[]);
extern int expand_block_move (rtx[]);
extern bool expand_block_compare (rtx[]);
extern bool expand_strn_compare (rtx[], int);
extern const char * rs6000_output_load_multiple (rtx[]);
extern bool rs6000_is_valid_mask (rtx, int *, int *, machine_mode);
extern bool rs6000_is_valid_and_mask (rtx, machine_mode);
extern bool rs6000_is_valid_shift_mask (rtx, rtx, machine_mode);
extern bool rs6000_is_valid_insert_mask (rtx, rtx, machine_mode);
extern const char *rs6000_insn_for_and_mask (machine_mode, rtx *, bool);
extern const char *rs6000_insn_for_shift_mask (machine_mode, rtx *, bool);
extern const char *rs6000_insn_for_insert_mask (machine_mode, rtx *, bool);
extern bool rs6000_is_valid_2insn_and (rtx, machine_mode);
extern void rs6000_emit_2insn_and (machine_mode, rtx *, bool, int);
extern int registers_ok_for_quad_peep (rtx, rtx);
extern int mems_ok_for_quad_peep (rtx, rtx);
extern bool gpr_or_gpr_p (rtx, rtx);
extern bool direct_move_p (rtx, rtx);
extern bool quad_address_p (rtx, machine_mode, bool);
extern bool quad_load_store_p (rtx, rtx);
extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx);
extern void expand_fusion_gpr_load (rtx *);
extern void emit_fusion_addis (rtx, rtx, const char *, const char *);
extern void emit_fusion_load_store (rtx, rtx, rtx, const char *);
extern const char *emit_fusion_gpr_load (rtx, rtx);
extern bool fusion_p9_p (rtx, rtx, rtx, rtx);
extern void expand_fusion_p9_load (rtx *);
extern void expand_fusion_p9_store (rtx *);
extern const char *emit_fusion_p9_load (rtx, rtx, rtx);
extern const char *emit_fusion_p9_store (rtx, rtx, rtx);
extern rtx fusion_wrap_memory_address (rtx);
extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class);
extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
machine_mode,
rtx);
extern void rs6000_secondary_reload_inner (rtx, rtx, rtx, bool);
extern void rs6000_secondary_reload_gpr (rtx, rtx, rtx, bool);
extern int paired_emit_vector_cond_expr (rtx, rtx, rtx,
rtx, rtx, rtx);
extern void paired_expand_vector_move (rtx operands[]);
extern int ccr_bit (rtx, int);
extern void rs6000_output_function_entry (FILE *, const char *);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern enum rtx_code rs6000_reverse_condition (machine_mode,
enum rtx_code);
extern rtx rs6000_emit_eqne (machine_mode, rtx, rtx, rtx);
extern void rs6000_emit_sISEL (machine_mode, rtx[]);
extern void rs6000_emit_sCOND (machine_mode, rtx[]);
extern void rs6000_emit_cbranch (machine_mode, rtx[]);
extern char * output_cbranch (rtx, const char *, int, rtx_insn *);
extern char * output_e500_flip_gt_bit (rtx, rtx);
extern const char * output_probe_stack_range (rtx, rtx);
extern bool rs6000_emit_set_const (rtx, rtx);
extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
extern void rs6000_split_signbit (rtx, rtx);
extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
extern void rs6000_expand_atomic_exchange (rtx op[]);
extern void rs6000_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
extern void rs6000_emit_swdiv (rtx, rtx, rtx, bool);
extern void rs6000_emit_swsqrt (rtx, rtx, bool);
extern void output_toc (FILE *, rtx, int, machine_mode);
extern rtx rs6000_longcall_ref (rtx);
extern void rs6000_fatal_bad_address (rtx);
extern rtx create_TOC_reference (rtx, rtx);
extern void rs6000_split_multireg_move (rtx, rtx);
extern void rs6000_emit_le_vsx_move (rtx, rtx, machine_mode);
extern bool valid_sf_si_move (rtx, rtx, machine_mode);
extern void rs6000_emit_move (rtx, rtx, machine_mode);
extern rtx rs6000_secondary_memory_needed_rtx (machine_mode);
extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode,
int, int, int, int *);
extern bool rs6000_legitimate_offset_address_p (machine_mode, rtx,
bool, bool);
extern rtx rs6000_find_base_term (rtx);
extern rtx rs6000_return_addr (int, rtx);
extern void rs6000_output_symbol_ref (FILE*, rtx);
extern HOST_WIDE_INT rs6000_initial_elimination_offset (int, int);
extern void rs6000_emit_popcount (rtx, rtx);
extern void rs6000_emit_parity (rtx, rtx);
extern rtx rs6000_machopic_legitimize_pic_address (rtx, machine_mode,
rtx);
extern rtx rs6000_address_for_fpconvert (rtx);
extern rtx rs6000_address_for_altivec (rtx);
extern rtx rs6000_allocate_stack_temp (machine_mode, bool, bool);
extern align_flags rs6000_loop_align (rtx);
extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool);
#endif /* RTX_CODE */
#ifdef TREE_CODE
extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align);
extern bool rs6000_special_adjust_field_align_p (tree, unsigned int);
extern unsigned int rs6000_special_round_type_align (tree, unsigned int,
unsigned int);
extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int,
unsigned int);
extern tree altivec_resolve_overloaded_builtin (location_t, tree, void *);
extern rtx rs6000_libcall_value (machine_mode);
extern rtx rs6000_va_arg (tree, tree);
extern int function_ok_for_sibcall (tree);
extern int rs6000_reg_parm_stack_space (tree, bool);
extern void rs6000_asm_weaken_decl (FILE *, tree, const char *, const char *);
extern void rs6000_xcoff_declare_function_name (FILE *, const char *, tree);
extern void rs6000_xcoff_declare_object_name (FILE *, const char *, tree);
extern void rs6000_xcoff_asm_output_aligned_decl_common (FILE *, tree,
const char *,
unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT);
extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);
extern bool rs6000_elf_in_small_data_p (const_tree);
#endif /* TREE_CODE */
extern int direct_return (void);
extern int first_reg_to_save (void);
extern int first_fp_reg_to_save (void);
extern void output_ascii (FILE *, const char *, int);
extern void rs6000_gen_section_name (char **, const char *, const char *);
extern void output_function_profiler (FILE *, int);
extern void output_profile_hook (int);
extern int rs6000_trampoline_size (void);
extern alias_set_type get_TOC_alias_set (void);
extern void rs6000_emit_prologue (void);
extern void rs6000_emit_load_toc_table (int);
extern unsigned int rs6000_dbx_register_number (unsigned int, unsigned int);
extern void rs6000_emit_epilogue (int);
extern void rs6000_expand_split_stack_prologue (void);
extern void rs6000_split_stack_space_check (rtx, rtx);
extern void rs6000_emit_eh_reg_restore (rtx, rtx);
extern const char * output_isel (rtx *);
extern void rs6000_call_aix (rtx, rtx, rtx, rtx);
extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx);
extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
extern void get_ppc476_thunk_name (char name[32]);
extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);
extern const char *rs6000_overloaded_builtin_name (enum rs6000_builtins);
extern int rs6000_store_data_bypass_p (rtx_insn *, rtx_insn *);
extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void);
extern void rs6000_asm_output_dwarf_pcrel (FILE *file, int size,
const char *label);
extern void rs6000_asm_output_dwarf_datarel (FILE *file, int size,
const char *label);
/* Declare functions in rs6000-c.c */
extern void rs6000_pragma_longcall (struct cpp_reader *);
extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
#ifdef TREE_CODE
extern bool rs6000_pragma_target_parse (tree, tree);
#endif
extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
HOST_WIDE_INT);
/* Declare functions in powerpcspe-d.c */
extern void rs6000_d_target_versions (void);
#if TARGET_MACHO
char *output_call (rtx_insn *, rtx *, int, int);
#endif
#ifdef NO_DOLLAR_IN_LABEL
const char * rs6000_xcoff_strip_dollar (const char *);
#endif
void rs6000_final_prescan_insn (rtx_insn *, rtx *operand, int num_operands);
extern unsigned char rs6000_class_max_nregs[][LIM_REG_CLASSES];
extern unsigned char rs6000_hard_regno_nregs[][FIRST_PSEUDO_REGISTER];
extern bool rs6000_linux_float_exceptions_rounding_supported_p (void);
/* Pass management. */
namespace gcc { class context; }
class rtl_opt_pass;
extern rtl_opt_pass *make_pass_analyze_swaps (gcc::context *);
#endif /* rs6000-protos.h */

32
gcc/config/powerpcspe/powerpcspe-tables.opt
View file

@ -1,32 +0,0 @@
; Generated automatically by genopt.sh from powerpcspe-cpus.def.
; Copyright (C) 2011-2018 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Enum
Name(rs6000_cpu_opt_value) Type(int)
Known CPUs (for use with the -mcpu= and -mtune= options):
EnumValue
Enum(rs6000_cpu_opt_value) String(native) Value(RS6000_CPU_OPTION_NATIVE) DriverOnly
EnumValue
Enum(rs6000_cpu_opt_value) String(8540) Value(26)
EnumValue
Enum(rs6000_cpu_opt_value) String(8548) Value(27)

43711
gcc/config/powerpcspe/powerpcspe.c
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File diff suppressed because it is too large Load diff

2705
gcc/config/powerpcspe/powerpcspe.h
View file

File diff suppressed because it is too large Load diff

14770
gcc/config/powerpcspe/powerpcspe.md
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File diff suppressed because it is too large Load diff

702
gcc/config/powerpcspe/powerpcspe.opt
View file

@ -1,702 +0,0 @@
; Options for the rs6000 port of the compiler
;
; Copyright (C) 2005-2018 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
HeaderInclude
config/powerpcspe/powerpcspe-opts.h
;; ISA flag bits (on/off)
Variable
HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
TargetSave
HOST_WIDE_INT x_rs6000_isa_flags
;; Miscellaneous flag bits that were set explicitly by the user
Variable
HOST_WIDE_INT rs6000_isa_flags_explicit
TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit
;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC8540
;; Always emit branch hint bits.
TargetVariable
unsigned char rs6000_always_hint
;; Schedule instructions for group formation.
TargetVariable
unsigned char rs6000_sched_groups
;; Align branch targets.
TargetVariable
unsigned char rs6000_align_branch_targets
;; Support for -msched-costly-dep option.
TargetVariable
enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
;; Support for -minsert-sched-nops option.
TargetVariable
enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
;; Non-zero to allow overriding loop alignment.
TargetVariable
unsigned char can_override_loop_align
;; Which small data model to use (for System V targets only)
TargetVariable
enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
;; Bit size of immediate TLS offsets and string from which it is decoded.
TargetVariable
int rs6000_tls_size = 32
;; ABI enumeration available for subtarget to use.
TargetVariable
enum rs6000_abi rs6000_current_abi = ABI_NONE
;; Type of traceback to use.
TargetVariable
enum rs6000_traceback_type rs6000_traceback = traceback_default
;; Control alignment for fields within structures.
TargetVariable
unsigned char rs6000_alignment_flags
;; Code model for 64-bit linux.
TargetVariable
enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
;; What type of reciprocal estimation instructions to generate
TargetVariable
unsigned int rs6000_recip_control
;; Mask of what builtin functions are allowed
TargetVariable
HOST_WIDE_INT rs6000_builtin_mask
;; Debug flags
TargetVariable
unsigned int rs6000_debug
;; This option existed in the past, but now is always on.
mpowerpc
Target RejectNegative Undocumented Ignore
mpowerpc64
Target Undocumented Report Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set.
mpowerpc-gpopt
Target Undocumented Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions.
mpowerpc-gfxopt
Target Undocumented Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions.
mmfcrf
Target Report Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction.
mpopcntb
Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction.
mfprnd
Target Undocumented Report Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions.
mcmpb
Target Undocumented Report Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction.
mmfpgpr
Target Undocumented Report Mask(MFPGPR) Var(rs6000_isa_flags)
Use extended PowerPC V2.05 move floating point to/from GPR instructions.
maltivec
Target Undocumented Report Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions.
maltivec=le
Target Undocumented Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
Generate AltiVec instructions using little-endian element order.
maltivec=be
Target Undocumented Report RejectNegative Var(rs6000_altivec_element_order, 2)
Generate AltiVec instructions using big-endian element order.
mhard-dfp
Target Undocumented Report Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions.
mmulhw
Target Undocumented Report Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions.
mdlmzb
Target Undocumented Report Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction.
mmultiple
Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions.
mstring
Target Undocumented Report Mask(STRING) Var(rs6000_isa_flags)
Generate string instructions for block moves.
msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point.
mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point.
mpopcntd
Target Undocumented Report Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction.
mfriz
Target Undocumented Report Var(TARGET_FRIZ) Init(-1) Save
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
mveclibabi=
Target RejectNegative Joined Var(rs6000_veclibabi_name)
Vector library ABI to use.
mvsx
Target Undocumented Report Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions.
mvsx-scalar-float
Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)
mvsx-scalar-double
Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
mvsx-scalar-memory
Target Undocumented Report Alias(mupper-regs-df)
mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64
mallow-movmisalign
Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow the movmisalign in DF/DI vectors
mefficient-unaligned-vsx
Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX vector and fp accesses to be efficient
mallow-df-permute
Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
; Allow permutation of DF/DI vectors
msched-groups
Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set rs6000_sched_groups
malways-hint
Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set rs6000_always_hint
malign-branch-targets
Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set rs6000_align_branch_targets
mvectorize-builtins
Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
; Explicitly control whether we vectorize the builtins or not.
mno-update
Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions.
mupdate
Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions.
msingle-pic-base
Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
Do not load the PIC register in function prologues.
mavoid-indexed-addresses
Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
Avoid generation of indexed load/store instructions when possible.
mtls-markers
Target Report Var(tls_markers) Init(1) Save
Mark __tls_get_addr calls with argument info.
msched-epilog
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
msched-prolog
Target Report Var(TARGET_SCHED_PROLOG) Save
Schedule the start and end of the procedure.
maix-struct-return
Target Report RejectNegative Var(aix_struct_return) Save
Return all structures in memory (AIX default).
msvr4-struct-return
Target Report RejectNegative Var(aix_struct_return,0) Save
Return small structures in registers (SVR4 default).
mxl-compat
Target Report Var(TARGET_XL_COMPAT) Save
Conform more closely to IBM XLC semantics.
mrecip
Target Report
Generate software reciprocal divide and square root for better throughput.
mrecip=
Target Report RejectNegative Joined Var(rs6000_recip_name)
Generate software reciprocal divide and square root for better throughput.
mrecip-precision
Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy.
mno-fp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
Do not place floating point constants in TOC.
mfp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
Place floating point constants in TOC.
mno-sum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
Do not place symbol+offset constants in TOC.
msum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
Place symbol+offset constants in TOC.
; Output only one TOC entry per module. Normally linking fails if
; there are more than 16K unique variables/constants in an executable. With
; this option, linking fails only if there are more than 16K modules, or
; if there are more than 16K unique variables/constant in a single module.
;
; This is at the cost of having 2 extra loads and one extra store per
; function, and one less allocable register.
mminimal-toc
Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure.
mfull-toc
Target Report
Put everything in the regular TOC.
mvrsave
Target Undocumented Report Var(TARGET_ALTIVEC_VRSAVE) Save
Generate VRSAVE instructions when generating AltiVec code.
mvrsave=no
Target Undocumented RejectNegative Alias(mvrsave) NegativeAlias
Deprecated option. Use -mno-vrsave instead.
mvrsave=yes
Target Undocumented RejectNegative Alias(mvrsave)
Deprecated option. Use -mvrsave instead.
mblock-move-inline-limit=
Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
Specify how many bytes should be moved inline before calling out to memcpy/memmove.
mblock-compare-inline-limit=
Target Report Var(rs6000_block_compare_inline_limit) Init(5) RejectNegative Joined UInteger Save
Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to memcmp will be generated instead.
mstring-compare-inline-limit=
Target Report Var(rs6000_string_compare_inline_limit) Init(8) RejectNegative Joined UInteger Save
Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to strncmp will be generated instead.
misel
Target Report Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions.
misel=no
Target RejectNegative Alias(misel) NegativeAlias
Deprecated option. Use -mno-isel instead.
misel=yes
Target RejectNegative Alias(misel)
Deprecated option. Use -misel instead.
mspe
Target Var(rs6000_spe) Save
Generate SPE SIMD instructions on E500.
mpaired
Target Undocumented Var(rs6000_paired_float) Save
Generate PPC750CL paired-single instructions.
mspe=no
Target RejectNegative Alias(mspe) NegativeAlias
Deprecated option. Use -mno-spe instead.
mspe=yes
Target RejectNegative Alias(mspe)
Deprecated option. Use -mspe instead.
mdebug=
Target RejectNegative Joined
-mdebug= Enable debug output.
mabi=altivec
Target Undocumented RejectNegative Var(rs6000_altivec_abi) Save
Use the AltiVec ABI extensions.
mabi=no-altivec
Target Undocumented RejectNegative Var(rs6000_altivec_abi, 0)
Do not use the AltiVec ABI extensions.
mabi=spe
Target RejectNegative Var(rs6000_spe_abi) Save
Use the SPE ABI extensions.
mabi=no-spe
Target RejectNegative Var(rs6000_spe_abi, 0)
Do not use the SPE ABI extensions.
mabi=elfv1
Target RejectNegative Var(rs6000_elf_abi, 1) Save
Use the ELFv1 ABI.
mabi=elfv2
Target RejectNegative Var(rs6000_elf_abi, 2)
Use the ELFv2 ABI.
; These are here for testing during development only, do not document
; in the manual please.
; If we want Darwin's struct-by-value-in-regs ABI.
mabi=d64
Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
mabi=d32
Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
mabi=ieeelongdouble
Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save
mabi=ibmlongdouble
Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)
mcpu=
Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mcpu= Use features of and schedule code for given CPU.
mtune=
Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mtune= Schedule code for given CPU.
mtraceback=
Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
-mtraceback= Select full, part, or no traceback table.
Enum
Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
EnumValue
Enum(rs6000_traceback_type) String(full) Value(traceback_full)
EnumValue
Enum(rs6000_traceback_type) String(part) Value(traceback_part)
EnumValue
Enum(rs6000_traceback_type) String(no) Value(traceback_none)
mlongcall
Target Report Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions.
mgen-cell-microcode
Target Undocumented Report Var(rs6000_gen_cell_microcode) Init(-1) Save
Generate Cell microcode.
mwarn-cell-microcode
Target Undocumented Var(rs6000_warn_cell_microcode) Init(0) Warning Save
Warn when a Cell microcoded instruction is emitted.
mwarn-altivec-long
Target Undocumented Var(rs6000_warn_altivec_long) Init(1) Save
Warn about deprecated 'vector long ...' AltiVec type usage.
mfloat-gprs=
Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
-mfloat-gprs= Select GPR floating point method.
Enum
Name(rs6000_float_gprs) Type(unsigned char)
Valid arguments to -mfloat-gprs=:
EnumValue
Enum(rs6000_float_gprs) String(yes) Value(1)
EnumValue
Enum(rs6000_float_gprs) String(single) Value(1)
EnumValue
Enum(rs6000_float_gprs) String(double) Value(2)
EnumValue
Enum(rs6000_float_gprs) String(no) Value(0)
mlong-double-
Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
-mlong-double-<n> Specify size of long double (64 or 128 bits).
mlra
Target Report Mask(LRA) Var(rs6000_isa_flags)
Enable Local Register Allocation.
msched-costly-dep=
Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
Determine which dependences between insns are considered costly.
minsert-sched-nops=
Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
Specify which post scheduling nop insertion scheme to apply.
malign-
Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
Specify alignment of structure fields default/natural.
Enum
Name(rs6000_alignment_flags) Type(unsigned char)
Valid arguments to -malign-:
EnumValue
Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
EnumValue
Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
mprioritize-restricted-insns=
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
Specify scheduling priority for dispatch slot restricted insns.
msingle-float
Target RejectNegative Var(rs6000_single_float) Save
Single-precision floating point unit.
mdouble-float
Target RejectNegative Var(rs6000_double_float) Save
Double-precision floating point unit.
msimple-fpu
Target Undocumented RejectNegative Var(rs6000_simple_fpu) Save
Floating point unit does not support divide & sqrt.
mfpu=
Target Undocumented RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
Enum
Name(fpu_type_t) Type(enum fpu_type_t)
EnumValue
Enum(fpu_type_t) String(none) Value(FPU_NONE)
EnumValue
Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
EnumValue
Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
EnumValue
Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
EnumValue
Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
mxilinx-fpu
Target Undocumented Var(rs6000_xilinx_fpu) Save
Specify Xilinx FPU.
mpointers-to-nested-functions
Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers.
msave-toc-indirect
Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Save the TOC in the prologue for indirect calls rather than inline.
mvsx-timode
Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
Allow 128-bit integers in VSX registers.
mpower8-fusion
Target Undocumented Report Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign
Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
Allow sign extension in fusion operations.
mpower8-vector
Target Undocumented Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use vector and scalar instructions added in ISA 2.07.
mcrypto
Target Undocumented Report Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
mdirect-move
Target Undocumented Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
Use ISA 2.07 direct move between GPR & VSX register instructions.
mhtm
Target Undocumented Report Mask(HTM) Var(rs6000_isa_flags)
Use ISA 2.07 transactional memory (HTM) instructions.
mquad-memory
Target Undocumented Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
Generate the quad word memory instructions (lq/stq).
mquad-memory-atomic
Target Undocumented Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
Generate the quad word memory atomic instructions (lqarx/stqcx).
mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.
mupper-regs-df
Target Undocumented Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
Allow double variables in upper registers with -mcpu=power7 or -mvsx.
mupper-regs-sf
Target Undocumented Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
mupper-regs
Target Undocumented Report Var(TARGET_UPPER_REGS) Init(-1) Save
Allow float/double variables in upper registers if cpu allows it.
mupper-regs-di
Target Undocumented Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.
mpower9-fusion
Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
Fuse certain operations together for better performance on power9.
mpower9-misc
Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
Use certain scalar instructions added in ISA 3.0.
mpower9-vector
Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use vector instructions added in ISA 3.0.
mpower9-dform-scalar
Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
Use scalar register+offset memory instructions added in ISA 3.0.
mpower9-dform-vector
Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
Use vector register+offset memory instructions added in ISA 3.0.
mpower9-dform
Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
Use register+offset memory instructions added in ISA 3.0.
mpower9-minmax
Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
Use the new min/max instructions defined in ISA 3.0.
mtoc-fusion
Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
Fuse medium/large code model toc references with the memory instruction.
mmodulo
Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions.
; We want to enable the internal support for the IEEE 128-bit floating point
; type without necessarily enabling the __float128 keyword. This is to allow
; Boost and other libraries that know about __float128 to work until the
; official library support is finished.
mfloat128-type
Target Undocumented Mask(FLOAT128_TYPE) Var(rs6000_isa_flags)
Allow the IEEE 128-bit types without requiring the __float128 keyword.
mfloat128
Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
Enable IEEE 128-bit floating point via the __float128 keyword.
mfloat128-hardware
Target Undocumented Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
Enable using IEEE 128-bit floating point instructions.
mfloat128-convert
Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
Enable default conversions between __float128 & long double.
mvsx-small-integer
Target Undocumented Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
Enable small integers to be in VSX registers.
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.
Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
Valid arguments to -mstack-protector-guard=:
EnumValue
Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
mstack-protector-guard-reg=
Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
Use the given base register for addressing the stack-protector guard.
TargetVariable
int rs6000_stack_protector_guard_reg = 0
mstack-protector-guard-offset=
Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
Use the given offset for addressing the stack-protector guard.
TargetVariable
long rs6000_stack_protector_guard_offset = 0

381
gcc/config/powerpcspe/ppc-asm.h
View file

@ -1,381 +0,0 @@
/* PowerPC asm definitions for GNU C.
Copyright (C) 2002-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Under winnt, 1) gas supports the following as names and 2) in particular
defining "toc" breaks the FUNC_START macro as ".toc" becomes ".2" */
#define r0 0
#define sp 1
#define toc 2
#define r3 3
#define r4 4
#define r5 5
#define r6 6
#define r7 7
#define r8 8
#define r9 9
#define r10 10
#define r11 11
#define r12 12
#define r13 13
#define r14 14
#define r15 15
#define r16 16
#define r17 17
#define r18 18
#define r19 19
#define r20 20
#define r21 21
#define r22 22
#define r23 23
#define r24 24
#define r25 25
#define r26 26
#define r27 27
#define r28 28
#define r29 29
#define r30 30
#define r31 31
#define cr0 0
#define cr1 1
#define cr2 2
#define cr3 3
#define cr4 4
#define cr5 5
#define cr6 6
#define cr7 7
#define f0 0
#define f1 1
#define f2 2
#define f3 3
#define f4 4
#define f5 5
#define f6 6
#define f7 7
#define f8 8
#define f9 9
#define f10 10
#define f11 11
#define f12 12
#define f13 13
#define f14 14
#define f15 15
#define f16 16
#define f17 17
#define f18 18
#define f19 19
#define f20 20
#define f21 21
#define f22 22
#define f23 23
#define f24 24
#define f25 25
#define f26 26
#define f27 27
#define f28 28
#define f29 29
#define f30 30
#define f31 31
#ifdef __VSX__
#define f32 32
#define f33 33
#define f34 34
#define f35 35
#define f36 36
#define f37 37
#define f38 38
#define f39 39
#define f40 40
#define f41 41
#define f42 42
#define f43 43
#define f44 44
#define f45 45
#define f46 46
#define f47 47
#define f48 48
#define f49 49
#define f50 30
#define f51 51
#define f52 52
#define f53 53
#define f54 54
#define f55 55
#define f56 56
#define f57 57
#define f58 58
#define f59 59
#define f60 60
#define f61 61
#define f62 62
#define f63 63
#endif
#ifdef __ALTIVEC__
#define v0 0
#define v1 1
#define v2 2
#define v3 3
#define v4 4
#define v5 5
#define v6 6
#define v7 7
#define v8 8
#define v9 9
#define v10 10
#define v11 11
#define v12 12
#define v13 13
#define v14 14
#define v15 15
#define v16 16
#define v17 17
#define v18 18
#define v19 19
#define v20 20
#define v21 21
#define v22 22
#define v23 23
#define v24 24
#define v25 25
#define v26 26
#define v27 27
#define v28 28
#define v29 29
#define v30 30
#define v31 31
#endif
#ifdef __VSX__
#define vs0 0
#define vs1 1
#define vs2 2
#define vs3 3
#define vs4 4
#define vs5 5
#define vs6 6
#define vs7 7
#define vs8 8
#define vs9 9
#define vs10 10
#define vs11 11
#define vs12 12
#define vs13 13
#define vs14 14
#define vs15 15
#define vs16 16
#define vs17 17
#define vs18 18
#define vs19 19
#define vs20 20
#define vs21 21
#define vs22 22
#define vs23 23
#define vs24 24
#define vs25 25
#define vs26 26
#define vs27 27
#define vs28 28
#define vs29 29
#define vs30 30
#define vs31 31
#define vs32 32
#define vs33 33
#define vs34 34
#define vs35 35
#define vs36 36
#define vs37 37
#define vs38 38
#define vs39 39
#define vs40 40
#define vs41 41
#define vs42 42
#define vs43 43
#define vs44 44
#define vs45 45
#define vs46 46
#define vs47 47
#define vs48 48
#define vs49 49
#define vs50 30
#define vs51 51
#define vs52 52
#define vs53 53
#define vs54 54
#define vs55 55
#define vs56 56
#define vs57 57
#define vs58 58
#define vs59 59
#define vs60 60
#define vs61 61
#define vs62 62
#define vs63 63
#endif
/*
* Macros to glue together two tokens.
*/
#ifdef __STDC__
#define XGLUE(a,b) a##b
#else
#define XGLUE(a,b) a/**/b
#endif
#define GLUE(a,b) XGLUE(a,b)
/*
* Macros to begin and end a function written in assembler. If -mcall-aixdesc
* or -mcall-nt, create a function descriptor with the given name, and create
* the real function with one or two leading periods respectively.
*/
#if defined(__powerpc64__) && _CALL_ELF == 2
/* Defining "toc" above breaks @toc in assembler code. */
#undef toc
#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name)
#define JUMP_TARGET(name) FUNC_NAME(name)
#define FUNC_START(name) \
.type FUNC_NAME(name),@function; \
.globl FUNC_NAME(name); \
FUNC_NAME(name): \
0: addis 2,12,(.TOC.-0b)@ha; \
addi 2,2,(.TOC.-0b)@l; \
.localentry FUNC_NAME(name),.-FUNC_NAME(name)
#define HIDDEN_FUNC(name) \
FUNC_START(name) \
.hidden FUNC_NAME(name);
#define FUNC_END(name) \
.size FUNC_NAME(name),.-FUNC_NAME(name)
#elif defined (__powerpc64__)
#define FUNC_NAME(name) GLUE(.,name)
#define JUMP_TARGET(name) FUNC_NAME(name)
#define FUNC_START(name) \
.section ".opd","aw"; \
name: \
.quad GLUE(.,name); \
.quad .TOC.@tocbase; \
.quad 0; \
.previous; \
.type GLUE(.,name),@function; \
.globl name; \
.globl GLUE(.,name); \
GLUE(.,name):
#define HIDDEN_FUNC(name) \
FUNC_START(name) \
.hidden name; \
.hidden GLUE(.,name);
#define FUNC_END(name) \
GLUE(.L,name): \
.size GLUE(.,name),GLUE(.L,name)-GLUE(.,name)
#elif defined(_CALL_AIXDESC)
#ifdef _RELOCATABLE
#define DESC_SECTION ".got2"
#else
#define DESC_SECTION ".got1"
#endif
#define FUNC_NAME(name) GLUE(.,name)
#define JUMP_TARGET(name) FUNC_NAME(name)
#define FUNC_START(name) \
.section DESC_SECTION,"aw"; \
name: \
.long GLUE(.,name); \
.long _GLOBAL_OFFSET_TABLE_; \
.long 0; \
.previous; \
.type GLUE(.,name),@function; \
.globl name; \
.globl GLUE(.,name); \
GLUE(.,name):
#define HIDDEN_FUNC(name) \
FUNC_START(name) \
.hidden name; \
.hidden GLUE(.,name);
#define FUNC_END(name) \
GLUE(.L,name): \
.size GLUE(.,name),GLUE(.L,name)-GLUE(.,name)
#else
#define FUNC_NAME(name) GLUE(__USER_LABEL_PREFIX__,name)
#if defined __PIC__ || defined __pic__
#define JUMP_TARGET(name) FUNC_NAME(name@plt)
#else
#define JUMP_TARGET(name) FUNC_NAME(name)
#endif
#define FUNC_START(name) \
.type FUNC_NAME(name),@function; \
.globl FUNC_NAME(name); \
FUNC_NAME(name):
#define HIDDEN_FUNC(name) \
FUNC_START(name) \
.hidden FUNC_NAME(name);
#define FUNC_END(name) \
GLUE(.L,name): \
.size FUNC_NAME(name),GLUE(.L,name)-FUNC_NAME(name)
#endif
#ifdef IN_GCC
/* For HAVE_GAS_CFI_DIRECTIVE. */
#include "auto-host.h"
#ifdef HAVE_GAS_CFI_DIRECTIVE
# define CFI_STARTPROC .cfi_startproc
# define CFI_ENDPROC .cfi_endproc
# define CFI_OFFSET(reg, off) .cfi_offset reg, off
# define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
# define CFI_RESTORE(reg) .cfi_restore reg
#else
# define CFI_STARTPROC
# define CFI_ENDPROC
# define CFI_OFFSET(reg, off)
# define CFI_DEF_CFA_REGISTER(reg)
# define CFI_RESTORE(reg)
#endif
#endif
#if defined __linux__ && !defined __powerpc64__
.section .note.GNU-stack
.previous
#endif

105
gcc/config/powerpcspe/ppc-auxv.h
View file

@ -1,105 +0,0 @@
/* PowerPC support for accessing the AUXV AT_PLATFORM, AT_HWCAP and AT_HWCAP2
values from the Thread Control Block (TCB).
Copyright (C) 2016-2018 Free Software Foundation, Inc.
Contributed by Peter Bergner <bergner@vnet.ibm.com>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _PPC_AUXV_H
#define _PPC_AUXV_H
/* The PLATFORM value stored in the TCB is offset by _DL_FIRST_PLATFORM. */
#define _DL_FIRST_PLATFORM 32
/* AT_PLATFORM bits. These must match the values defined in GLIBC. */
#define PPC_PLATFORM_POWER4 0
#define PPC_PLATFORM_PPC970 1
#define PPC_PLATFORM_POWER5 2
#define PPC_PLATFORM_POWER5_PLUS 3
#define PPC_PLATFORM_POWER6 4
#define PPC_PLATFORM_CELL_BE 5
#define PPC_PLATFORM_POWER6X 6
#define PPC_PLATFORM_POWER7 7
#define PPC_PLATFORM_PPCA2 8
#define PPC_PLATFORM_PPC405 9
#define PPC_PLATFORM_PPC440 10
#define PPC_PLATFORM_PPC464 11
#define PPC_PLATFORM_PPC476 12
#define PPC_PLATFORM_POWER8 13
#define PPC_PLATFORM_POWER9 14
/* AT_HWCAP bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
#define PPC_FEATURE_HAS_FPU 0x08000000
#define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#define PPC_FEATURE_NO_TB 0x00100000
#define PPC_FEATURE_POWER4 0x00080000
#define PPC_FEATURE_POWER5 0x00040000
#define PPC_FEATURE_POWER5_PLUS 0x00020000
#define PPC_FEATURE_CELL_BE 0x00010000
#define PPC_FEATURE_BOOKE 0x00008000
#define PPC_FEATURE_SMT 0x00004000
#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
#define PPC_FEATURE_ARCH_2_05 0x00001000
#define PPC_FEATURE_PA6T 0x00000800
#define PPC_FEATURE_HAS_DFP 0x00000400
#define PPC_FEATURE_POWER6_EXT 0x00000200
#define PPC_FEATURE_ARCH_2_06 0x00000100
#define PPC_FEATURE_HAS_VSX 0x00000080
#define PPC_FEATURE_PERFMON_COMPAT 0x00000040
#define PPC_FEATURE_TRUE_LE 0x00000002
#define PPC_FEATURE_PPC_LE 0x00000001
/* AT_HWCAP2 bits. These must match the values defined in the Linux kernel. */
#define PPC_FEATURE2_ARCH_2_07 0x80000000
#define PPC_FEATURE2_HAS_HTM 0x40000000
#define PPC_FEATURE2_HAS_DSCR 0x20000000
#define PPC_FEATURE2_HAS_EBB 0x10000000
#define PPC_FEATURE2_HAS_ISEL 0x08000000
#define PPC_FEATURE2_HAS_TAR 0x04000000
#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000
#define PPC_FEATURE2_HTM_NOSC 0x01000000
#define PPC_FEATURE2_ARCH_3_00 0x00800000
#define PPC_FEATURE2_HAS_IEEE128 0x00400000
/* Thread Control Block (TCB) offsets of the AT_PLATFORM, AT_HWCAP and
AT_HWCAP2 values. These must match the values defined in GLIBC. */
#define TCB_PLATFORM_OFFSET ((TARGET_64BIT) ? -28764 : -28724)
#define TCB_HWCAP_BASE_OFFSET ((TARGET_64BIT) ? -28776 : -28736)
#define TCB_HWCAP1_OFFSET \
((BYTES_BIG_ENDIAN) ? TCB_HWCAP_BASE_OFFSET : TCB_HWCAP_BASE_OFFSET+4)
#define TCB_HWCAP2_OFFSET \
((BYTES_BIG_ENDIAN) ? TCB_HWCAP_BASE_OFFSET+4 : TCB_HWCAP_BASE_OFFSET)
#define TCB_HWCAP_OFFSET(ID) \
(((ID) == 0) ? TCB_HWCAP1_OFFSET : TCB_HWCAP2_OFFSET)
#endif /* _PPC_AUXV_H */

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gcc/config/powerpcspe/ppu_intrinsics.h
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@ -1,727 +0,0 @@
/* PPU intrinsics as defined by the C/C++ Language extension for Cell BEA.
Copyright (C) 2007-2018 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* TODO:
misc ops (traps)
supervisor/hypervisor mode ops. */
#ifndef _PPU_INTRINSICS_H
#define _PPU_INTRINSICS_H
#if !defined(__PPU__) && !defined(__ppc__) && !defined(__ppc64__) \
&& !defined(__GNUC__)
#error ppu_intrinsics.h included on wrong platform/compiler
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*
* unsigned int __cntlzw(unsigned int)
* unsigned int __cntlzd(unsigned long long)
* int __mulhw(int, int)
* unsigned int __mulhwu(unsigned int, unsigned int)
* long long __mulhd(long long, long long)
* unsigned long long __mulhdu(unsigned long long, unsigned long long)
*
* void __sync(void)
* void __isync(void)
* void __lwsync(void)
* void __eieio(void)
*
* void __nop(void)
* void __cctpl(void)
* void __cctpm(void)
* void __cctph(void)
* void __db8cyc(void)
* void __db10cyc(void)
* void __db12cyc(void)
* void __db16cyc(void)
*
* void __mtspr(unsigned int spr, unsigned long long value)
* unsigned long long __mfspr(unsigned int spr)
* unsigned long long __mftb(void)
*
* void __icbi(void *base)
* void __dcbi(void *base)
*
* void __dcbf(void *base)
* void __dcbz(void *base)
* void __dcbst(void *base)
* void __dcbtst(void *base)
* void __dcbt(void *base)
* void __dcbt_TH1000(void *EATRUNC, bool D, bool UG, int ID)
* void __dcbt_TH1010(bool GO, int S, int UNITCNT, bool T, bool U, int ID)
*
* unsigned __lwarx(void *base)
* unsigned long long __ldarx(void *base)
* bool __stwcx(void *base, unsigned value)
* bool __stdcx(void *base, unsigned long long value)
*
* unsigned short __lhbrx(void *base)
* unsigned int __lwbrx(void *base)
* unsigned long long __ldbrx(void *base)
* void __sthbrx(void *base, unsigned short value)
* void __stwbrx(void *base, unsigned int value)
* void __stdbrx(void *base, unsigned long long value)
*
* double __fabs(double x)
* float __fabsf(float x)
* double __fnabs(double x)
* float __fnabsf(float x)
* double __fmadd(double x, double y, double z)
* double __fmsub(double x, double y, double z)
* double __fnmadd(double x, double y, double z)
* double __fnmsub(double x, double y, double z)
* float __fmadds(float x, float y, float z)
* float __fmsubs(float x, float y, float z)
* float __fnmadds(float x, float y, float z)
* float __fnmsubs(float x, float y, float z)
* double __fsel(double x, double y, double z)
* float __fsels(float x, float y, float z)
* double __frsqrte(double x)
* float __fres(float x)
* double __fsqrt(double x)
* float __fsqrts(float x)
* long long __fctid(double x)
* long long __fctiw(double x)
* double __fcfid(long long x)
* double __mffs(void)
* void __mtfsf(int mask, double value)
* void __mtfsfi(int bits, int field)
* void __mtfsb0(int)
* void __mtfsb1(int)
* double __setflm(double)
*
* dcbt intrinsics
* void __protected_unlimited_stream_set (unsigned int direction, const void *add, unsigned int ID)
* void __protected_stream_set (unsigned int direction, const void *add, unsigned int ID)
* void __protected_stream_stop_all (void)
* void __protected_stream_stop (unsigned int ID)
* void __protected_stream_count (unsigned int unit_cnt, unsigned int ID)
* void __protected_stream_go (void)
*/
typedef int __V4SI __attribute__((vector_size(16)));
#define __cntlzw(v) __builtin_clz(v)
#define __cntlzd(v) __builtin_clzll(v)
#define __mulhw(a,b) __extension__ \
({int result; \
__asm__ ("mulhw %0,%1,%2" \
: "=r" (result) \
: "r" ((int) (a)), \
"r" ((int) (b))); \
result; })
#define __mulhwu(a,b) __extension__ \
({unsigned int result; \
__asm__ ("mulhwu %0,%1,%2" \
: "=r" (result) \
: "r" ((unsigned int) (a)), \
"r" ((unsigned int) (b))); \
result; })
#ifdef __powerpc64__
#define __mulhd(a,b) __extension__ \
({ long long result; \
__asm__ ("mulhd %0,%1,%2" \
: "=r" (result) \
: "r" ((long long) (a)), \
"r" ((long long) (b))); \
result; })
#define __mulhdu(a,b) __extension__ \
({unsigned long long result; \
__asm__ ("mulhdu %0,%1,%2" \
: "=r" (result) \
: "r" ((unsigned long long) (a)), \
"r" ((unsigned long long) (b))); \
result; })
#endif /* __powerpc64__ */
#define __sync() __asm__ volatile ("sync" : : : "memory")
#define __isync() __asm__ volatile ("isync" : : : "memory")
#define __lwsync() __asm__ volatile ("lwsync" : : : "memory")
#define __eieio() __asm__ volatile ("eieio" : : : "memory")
#define __nop() __asm__ volatile ("ori 0,0,0" : : : "memory")
#define __cctpl() __asm__ volatile ("or 1,1,1" : : : "memory")
#define __cctpm() __asm__ volatile ("or 2,2,2" : : : "memory")
#define __cctph() __asm__ volatile ("or 3,3,3" : : : "memory")
#define __db8cyc() __asm__ volatile ("or 28,28,28" : : : "memory")
#define __db10cyc() __asm__ volatile ("or 29,29,29" : : : "memory")
#define __db12cyc() __asm__ volatile ("or 30,30,30" : : : "memory")
#define __db16cyc() __asm__ volatile ("or 31,31,31" : : : "memory")
#ifdef __powerpc64__
#define __mtspr(spr, value) \
__asm__ volatile ("mtspr %0,%1" : : "n" (spr), "r" (value))
#define __mfspr(spr) __extension__ \
({ unsigned long long result; \
__asm__ volatile ("mfspr %0,%1" : "=r" (result) : "n" (spr)); \
result; })
#endif /* __powerpc64__ */
#ifdef __powerpc64__
/* Work around the hardware bug in the current Cell implementation. */
#define __mftb() __extension__ \
({ unsigned long long result; \
__asm__ volatile ("1: mftb %[current_tb]\n" \
"\tcmpwi 7, %[current_tb], 0\n" \
"\tbeq- 7, 1b" \
: [current_tb] "=r" (result): \
:"cr7"); \
result; })
#else
#define __mftb() __extension__ \
({ unsigned long long result; \
unsigned long t; \
__asm__ volatile ("1:\n" \
"\tmftbu %0\n" \
"\tmftb %L0\n" \
"\tmftbu %1\n" \
"\tcmpw %0,%1\n" \
"\tbne 1b" \
: "=r" (result), "=r" (t)); \
result; })
#endif /* __powerpc64__ */
#define __dcbf(base) \
__asm__ volatile ("dcbf %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __dcbz(base) \
__asm__ volatile ("dcbz %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __dcbst(base) \
__asm__ volatile ("dcbst %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __dcbtst(base) \
__asm__ volatile ("dcbtst %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __dcbt(base) \
__asm__ volatile ("dcbt %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __icbi(base) \
__asm__ volatile ("icbi %y0" : "=Z" (*(__V4SI*) (base)) : : "memory")
#define __dcbt_TH1000(EATRUNC, D, UG, ID) \
__asm__ volatile ("dcbt %y0,8" \
: "=Z" (*(__V4SI*) (__SIZE_TYPE__)((((__SIZE_TYPE__) (EATRUNC)) & ~0x7F) \
| ((((D) & 1) << 6) \
| (((UG) & 1) << 5) \
| ((ID) & 0xF)))) : : "memory")
#define __dcbt_TH1010(GO, S, UNITCNT, T, U, ID) \
__asm__ volatile ("dcbt %y0,10" \
: "=Z" (*(__V4SI*) (__SIZE_TYPE__)((((__SIZE_TYPE__) (GO) & 1) << 31) \
| (((S) & 0x3) << 29) \
| (((UNITCNT) & 0x3FF) << 7) \
| (((T) & 1) << 6) \
| (((U) & 1) << 5) \
| ((ID) & 0xF))) : : "memory")
#define __protected_unlimited_stream_set(DIRECTION, ADDR, ID) \
__dcbt_TH1000 ((ADDR), (DIRECTION)>>1, 1, (ID))
#define __protected_stream_set(DIRECTION, ADDR, ID) \
__dcbt_TH1000 ((ADDR), (DIRECTION)>>1, 0, (ID))
#define __protected_stream_stop_all() \
__dcbt_TH1010 (0, 3, 0, 0, 0, 0)
#define __protected_stream_stop(ID) \
__dcbt_TH1010 (0, 2, 0, 0, 0, (ID))
#define __protected_stream_count(COUNT, ID) \
__dcbt_TH1010 (0, 0, (COUNT), 0, 0, (ID))
#define __protected_stream_go() \
__dcbt_TH1010 (1, 0, 0, 0, 0, 0)
#define __lhbrx(base) __extension__ \
({unsigned short result; \
typedef struct {char a[2];} halfwordsize; \
halfwordsize *ptrp = (halfwordsize*)(void*)(base); \
__asm__ ("lhbrx %0,%y1" \
: "=r" (result) \
: "Z" (*ptrp)); \
result; })
#define __lwbrx(base) __extension__ \
({unsigned int result; \
typedef struct {char a[4];} wordsize; \
wordsize *ptrp = (wordsize*)(void*)(base); \
__asm__ ("lwbrx %0,%y1" \
: "=r" (result) \
: "Z" (*ptrp)); \
result; })
#ifdef __powerpc64__
#define __ldbrx(base) __extension__ \
({unsigned long long result; \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ ("ldbrx %0,%y1" \
: "=r" (result) \
: "Z" (*ptrp)); \
result; })
#else
#define __ldbrx(base) __extension__ \
({unsigned long long result; \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ ("lwbrx %L0,%y1\n" \
"\tlwbrx %0,%y2" \
: "=&r" (result) \
: "Z" (*ptrp), "Z" (*((char *) ptrp + 4))); \
result; })
#endif /* __powerpc64__ */
#define __sthbrx(base, value) do { \
typedef struct {char a[2];} halfwordsize; \
halfwordsize *ptrp = (halfwordsize*)(void*)(base); \
__asm__ ("sthbrx %1,%y0" \
: "=Z" (*ptrp) \
: "r" (value)); \
} while (0)
#define __stwbrx(base, value) do { \
typedef struct {char a[4];} wordsize; \
wordsize *ptrp = (wordsize*)(void*)(base); \
__asm__ ("stwbrx %1,%y0" \
: "=Z" (*ptrp) \
: "r" (value)); \
} while (0)
#ifdef __powerpc64__
#define __stdbrx(base, value) do { \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ ("stdbrx %1,%y0" \
: "=Z" (*ptrp) \
: "r" (value)); \
} while (0)
#else
#define __stdbrx(base, value) do { \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ ("stwbrx %L2,%y0\n" \
"\tstwbrx %2,%y1" \
: "=Z" (*ptrp), "=Z" (*((char *) ptrp + 4)) \
: "r" (value)); \
} while (0)
#endif /* __powerpc64__ */
#define __lwarx(base) __extension__ \
({unsigned int result; \
typedef struct {char a[4];} wordsize; \
wordsize *ptrp = (wordsize*)(void*)(base); \
__asm__ volatile ("lwarx %0,%y1" \
: "=r" (result) \
: "Z" (*ptrp)); \
result; })
#ifdef __powerpc64__
#define __ldarx(base) __extension__ \
({unsigned long long result; \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ volatile ("ldarx %0,%y1" \
: "=r" (result) \
: "Z" (*ptrp)); \
result; })
#endif /* __powerpc64__ */
#define __stwcx(base, value) __extension__ \
({unsigned int result; \
typedef struct {char a[4];} wordsize; \
wordsize *ptrp = (wordsize*)(void*)(base); \
__asm__ volatile ("stwcx. %2,%y1\n" \
"\tmfocrf %0,0x80" \
: "=r" (result), \
"=Z" (*ptrp) \
: "r" (value) : "cr0"); \
((result & 0x20000000) >> 29); })
#ifdef __powerpc64__
#define __stdcx(base, value) __extension__ \
({unsigned long long result; \
typedef struct {char a[8];} doublewordsize; \
doublewordsize *ptrp = (doublewordsize*)(void*)(base); \
__asm__ volatile ("stdcx. %2,%y1\n" \
"\tmfocrf %0,0x80" \
: "=r" (result), \
"=Z" (*ptrp) \
: "r" (value) : "cr0"); \
((result & 0x20000000) >> 29); })
#endif /* __powerpc64__ */
#define __mffs() __extension__ \
({double result; \
__asm__ volatile ("mffs %0" : "=d" (result)); \
result; })
#define __mtfsf(mask,value) \
__asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "d" ((double) (value)))
#define __mtfsfi(bits,field) \
__asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field))
#define __mtfsb0(bit) __asm__ volatile ("mtfsb0 %0" : : "n" (bit))
#define __mtfsb1(bit) __asm__ volatile ("mtfsb1 %0" : : "n" (bit))
#define __setflm(v) __extension__ \
({double result; \
__asm__ volatile ("mffs %0\n\tmtfsf 255,%1" \
: "=&d" (result) \
: "d" ((double) (v))); \
result; })
/* __builtin_fabs may perform unnecessary rounding. */
/* Rename __fabs and __fabsf to work around internal prototypes defined
in bits/mathcalls.h with some glibc versions. */
#define __fabs __ppu_fabs
#define __fabsf __ppu_fabsf
static __inline__ double __fabs(double x) __attribute__((always_inline));
static __inline__ double
__fabs(double x)
{
double r;
__asm__("fabs %0,%1" : "=d"(r) : "d"(x));
return r;
}
static __inline__ float __fabsf(float x) __attribute__((always_inline));
static __inline__ float
__fabsf(float x)
{
float r;
__asm__("fabs %0,%1" : "=f"(r) : "f"(x));
return r;
}
static __inline__ double __fnabs(double x) __attribute__((always_inline));
static __inline__ double
__fnabs(double x)
{
double r;
__asm__("fnabs %0,%1" : "=d"(r) : "d"(x));
return r;
}
static __inline__ float __fnabsf(float x) __attribute__((always_inline));
static __inline__ float
__fnabsf(float x)
{
float r;
__asm__("fnabs %0,%1" : "=f"(r) : "f"(x));
return r;
}
static __inline__ double __fmadd(double x, double y, double z)
__attribute__((always_inline));
static __inline__ double
__fmadd(double x, double y, double z)
{
double r;
__asm__("fmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r;
}
static __inline__ double __fmsub(double x, double y, double z)
__attribute__((always_inline));
static __inline__ double
__fmsub(double x, double y, double z)
{
double r;
__asm__("fmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r;
}
static __inline__ double __fnmadd(double x, double y, double z)
__attribute__((always_inline));
static __inline__ double
__fnmadd(double x, double y, double z)
{
double r;
__asm__("fnmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r;
}
static __inline__ double __fnmsub(double x, double y, double z)
__attribute__((always_inline));
static __inline__ double
__fnmsub(double x, double y, double z)
{
double r;
__asm__("fnmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r;
}
static __inline__ float __fmadds(float x, float y, float z)
__attribute__((always_inline));
static __inline__ float
__fmadds(float x, float y, float z)
{
float r;
__asm__("fmadds %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
return r;
}
static __inline__ float __fmsubs(float x, float y, float z)
__attribute__((always_inline));
static __inline__ float
__fmsubs(float x, float y, float z)
{
float r;
__asm__("fmsubs %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
return r;
}
static __inline__ float __fnmadds(float x, float y, float z)
__attribute__((always_inline));
static __inline__ float
__fnmadds(float x, float y, float z)
{
float r;
__asm__("fnmadds %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
return r;
}
static __inline__ float __fnmsubs(float x, float y, float z)
__attribute__((always_inline));
static __inline__ float
__fnmsubs(float x, float y, float z)
{
float r;
__asm__("fnmsubs %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
return r;
}
static __inline__ double __fsel(double x, double y, double z)
__attribute__((always_inline));
static __inline__ double
__fsel(double x, double y, double z)
{
double r;
__asm__("fsel %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
return r;
}
static __inline__ float __fsels(float x, float y, float z)
__attribute__((always_inline));
static __inline__ float
__fsels(float x, float y, float z)
{
float r;
__asm__("fsel %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
return r;
}
static __inline__ double __frsqrte(double x) __attribute__((always_inline));
static __inline__ double
__frsqrte(double x)
{
double r;
__asm__("frsqrte %0,%1" : "=d" (r) : "d" (x));
return r;
}
static __inline__ float __fres(float x) __attribute__((always_inline));
static __inline__ float
__fres(float x)
{
float r;
__asm__("fres %0,%1" : "=f"(r) : "f"(x));
return r;
}
static __inline__ double __fsqrt(double x) __attribute__((always_inline));
static __inline__ double
__fsqrt(double x)
{
double r;
__asm__("fsqrt %0,%1" : "=d"(r) : "d"(x));
return r;
}
static __inline__ float __fsqrts(float x) __attribute__((always_inline));
static __inline__ float
__fsqrts(float x)
{
float r;
__asm__("fsqrts %0,%1" : "=f"(r) : "f"(x));
return r;
}
static __inline__ double __fmul (double a, double b) __attribute__ ((always_inline));
static __inline__ double
__fmul(double a, double b)
{
double d;
__asm__ ("fmul %0,%1,%2" : "=d" (d) : "d" (a), "d" (b));
return d;
}
static __inline__ float __fmuls (float a, float b) __attribute__ ((always_inline));
static __inline__ float
__fmuls (float a, float b)
{
float d;
__asm__ ("fmuls %0,%1,%2" : "=d" (d) : "f" (a), "f" (b));
return d;
}
static __inline__ float __frsp (float a) __attribute__ ((always_inline));
static __inline__ float
__frsp (float a)
{
float d;
__asm__ ("frsp %0,%1" : "=d" (d) : "f" (a));
return d;
}
static __inline__ double __fcfid (long long a) __attribute__((always_inline));
static __inline__ double
__fcfid (long long a)
{
double d;
__asm__ ("fcfid %0,%1" : "=d" (d) : "d" (a));
return d;
}
static __inline__ long long __fctid (double a) __attribute__ ((always_inline));
static __inline__ long long
__fctid (double a)
{
long long d;
__asm__ ("fctid %0,%1" : "=d" (d) : "d" (a));
return d;
}
static __inline__ long long __fctidz (double a) __attribute__ ((always_inline));
static __inline__ long long
__fctidz (double a)
{
long long d;
__asm__ ("fctidz %0,%1" : "=d" (d) : "d" (a));
return d;
}
static __inline__ int __fctiw (double a) __attribute__ ((always_inline));
static __inline__ int
__fctiw (double a)
{
unsigned long long d;
__asm__ ("fctiw %0,%1" : "=d" (d) : "d" (a));
return (int) d;
}
static __inline__ int __fctiwz (double a) __attribute__ ((always_inline));
static __inline__ int
__fctiwz (double a)
{
long long d;
__asm__ ("fctiwz %0,%1" : "=d" (d) : "d" (a));
return (int) d;
}
#ifdef __powerpc64__
#define __rldcl(a,b,mb) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldcl %0,%1,%2,%3" : "=r" (d) : "r" (a), "r" (b), "i" (mb)); \
d; \
})
#define __rldcr(a,b,me) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldcr %0,%1,%2,%3" : "=r" (d) : "r" (a), "r" (b), "i" (me)); \
d; \
})
#define __rldic(a,sh,mb) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldic %0,%1,%2,%3" : "=r" (d) : "r" (a), "i" (sh), "i" (mb)); \
d; \
})
#define __rldicl(a,sh,mb) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldicl %0,%1,%2,%3" : "=r" (d) : "r" (a), "i" (sh), "i" (mb)); \
d; \
})
#define __rldicr(a,sh,me) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldicr %0,%1,%2,%3" : "=r" (d) : "r" (a), "i" (sh), "i" (me)); \
d; \
})
#define __rldimi(a,b,sh,mb) __extension__ \
({ \
unsigned long long d; \
__asm__ ("rldimi %0,%1,%2,%3" : "=r" (d) : "r" (b), "i" (sh), "i" (mb), "0" (a)); \
d; \
})
#endif /* __powerpc64__ */
#define __rlwimi(a,b,sh,mb,me) __extension__ \
({ \
unsigned int d; \
__asm__ ("rlwimi %0,%1,%2,%3,%4" : "=r" (d) : "r" (b), "i" (sh), "i" (mb), "i" (me), "0" (a)); \
d; \
})
#define __rlwinm(a,sh,mb,me) __extension__ \
({ \
unsigned int d; \
__asm__ ("rlwinm %0,%1,%2,%3,%4" : "=r" (d) : "r" (a), "i" (sh), "i" (mb), "i" (me)); \
d; \
})
#define __rlwnm(a,b,mb,me) __extension__ \
({ \
unsigned int d; \
__asm__ ("rlwnm %0,%1,%2,%3,%4" : "=r" (d) : "r" (a), "r" (b), "i" (mb), "i" (me)); \
d; \
})
#ifdef __cplusplus
}
#endif
#endif /* _PPU_INTRINSICS_H */

2124
gcc/config/powerpcspe/predicates.md
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162
gcc/config/powerpcspe/rs64.md
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@ -1,162 +0,0 @@
;; Scheduling description for IBM RS64 processors.
;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "rs64,rs64fp")
(define_cpu_unit "iu_rs64" "rs64")
(define_cpu_unit "mciu_rs64" "rs64")
(define_cpu_unit "fpu_rs64" "rs64fp")
(define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
;; RS64a 64-bit IU, LSU, FPU, BPU
(define_insn_reservation "rs64a-load" 2
(and (eq_attr "type" "load")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-store" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-fpload" 3
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-llsc" 2
(and (eq_attr "type" "load_l,store_c")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
(define_insn_reservation "rs64a-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "rs64a"))
"iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "rs64a"))
"iu_rs64,iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-imul" 20
(and (eq_attr "type" "mul")
(eq_attr "size" "32")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*13")
(define_insn_reservation "rs64a-imul2" 12
(and (eq_attr "type" "mul")
(eq_attr "size" "16")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*5")
(define_insn_reservation "rs64a-imul3" 8
(and (eq_attr "type" "mul")
(eq_attr "size" "8")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*2")
(define_insn_reservation "rs64a-lmul" 34
(and (eq_attr "type" "mul")
(eq_attr "size" "64")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*34")
(define_insn_reservation "rs64a-idiv" 66
(and (eq_attr "type" "div")
(eq_attr "size" "32")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*66")
(define_insn_reservation "rs64a-ldiv" 66
(and (eq_attr "type" "div")
(eq_attr "size" "64")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
(and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
(define_insn_reservation "rs64a-fpcompare" 5
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64,bpu_rs64")
(define_insn_reservation "rs64a-fp" 4
(and (eq_attr "type" "fp,fpsimple,dmul")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64")
(define_insn_reservation "rs64a-sdiv" 31
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64*31")
(define_insn_reservation "rs64a-sqrt" 49
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "rs64a"))
"mciu_rs64,fpu_rs64*49")
(define_insn_reservation "rs64a-mfcr" 2
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-mtcr" 3
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
(define_insn_reservation "rs64a-jmpreg" 1
(and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
(eq_attr "cpu" "rs64a"))
"bpu_rs64")
(define_insn_reservation "rs64a-isync" 6
(and (eq_attr "type" "isync")
(eq_attr "cpu" "rs64a"))
"bpu_rs64")
(define_insn_reservation "rs64a-sync" 1
(and (eq_attr "type" "sync")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")

65
gcc/config/powerpcspe/rtems.h
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@ -1,65 +0,0 @@
/* Definitions for rtems targeting a PowerPC using elf.
Copyright (C) 1996-2018 Free Software Foundation, Inc.
Contributed by Joel Sherrill (joel@OARcorp.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Specify predefined symbols in preprocessor. */
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("PPC"); \
builtin_define ("__rtems__"); \
builtin_define ("__USE_INIT_FINI__"); \
builtin_assert ("system=rtems"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
while (0)
#undef TARGET_LIBGCC_SDATA_SECTION
#define TARGET_LIBGCC_SDATA_SECTION ".sdata"
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_rtems)"
#define CPP_OS_RTEMS_SPEC "\
%{!mcpu*: %{!Dppc*: %{!Dmpc*: -Dmpc750} } }\
%{mcpu=403: %{!Dppc*: %{!Dmpc*: -Dppc403} } } \
%{mcpu=505: %{!Dppc*: %{!Dmpc*: -Dmpc505} } } \
%{mcpu=601: %{!Dppc*: %{!Dmpc*: -Dppc601} } } \
%{mcpu=602: %{!Dppc*: %{!Dmpc*: -Dppc602} } } \
%{mcpu=603: %{!Dppc*: %{!Dmpc*: -Dppc603} } } \
%{mcpu=603e: %{!Dppc*: %{!Dmpc*: -Dppc603e} } } \
%{mcpu=604: %{!Dppc*: %{!Dmpc*: -Dmpc604} } } \
%{mcpu=750: %{!Dppc*: %{!Dmpc*: -Dmpc750} } } \
%{mcpu=821: %{!Dppc*: %{!Dmpc*: -Dmpc821} } } \
%{mcpu=860: %{!Dppc*: %{!Dmpc*: -Dmpc860} } } \
%{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540} } } \
%{mcpu=e6500: -D__PPC_CPU_E6500__}"
#undef SUBSUBTARGET_EXTRA_SPECS
#define SUBSUBTARGET_EXTRA_SPECS \
{ "cpp_os_rtems", CPP_OS_RTEMS_SPEC }

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