RISC-V: Enable full coverage vect tests
I have analyzed all existing FAILs.
Except these following FAILs need to be addressed:
FAIL: gcc.dg/vect/slp-reduc-7.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/slp-reduc-7.c execution test
FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_(LEN_)?SUB"
FAIL: gcc.dg/vect/vect-cond-arith-2.c scan-tree-dump optimized " = \\.COND_(LEN_)?SUB"
All other FAILs are dumple fail can be ignored (Confirm ARM SVE also has such FAILs and didn't fix them on either tests or implementation).
Now, It's time to enable full coverage vect tests including vec_unpack, vec_pack, vec_interleave, ... etc.
To see what we are still missing:
Before this patch:
=== gcc Summary ===
# of expected passes 182839
# of unexpected failures 79
# of unexpected successes 11
# of expected failures 1275
# of unresolved testcases 4
# of unsupported tests 4223
After this patch:
=== gcc Summary ===
# of expected passes 183411
# of unexpected failures 93
# of unexpected successes 7
# of expected failures 1285
# of unresolved testcases 4
# of unsupported tests 4157
There is an important issue increased that I have noticed after this patch:
FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-3.c -flto -ffat-lto-objects scan-tree-dump vect "Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-3.c scan-tree-dump vect "Loop contains only SLP stmts"
It has a related PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111721
I am gonna fix this first in the middle-end after commit this patch.
Ok for trunk ?
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add RVV.
This commit is contained in:
Juzhe-Zhong
Lehua Ding
parent
4efe9085d0
commit
23aabded1f
1 changed files with 33 additions and 12 deletions
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@ -7876,7 +7876,9 @@ proc check_effective_target_vect_sdot_qi { } {
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|| [istarget aarch64*-*-*]
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|| [istarget arm*-*-*]
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|| ([istarget mips*-*-*]
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&& [et-is-effective-target mips_msa]) }}]
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&& [et-is-effective-target mips_msa])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports a vector
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@ -7891,7 +7893,9 @@ proc check_effective_target_vect_udot_qi { } {
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|| [istarget arm*-*-*]
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|| [istarget ia64-*-*]
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|| ([istarget mips*-*-*]
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&& [et-is-effective-target mips_msa]) }}]
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&& [et-is-effective-target mips_msa])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports a vector
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@ -7918,7 +7922,9 @@ proc check_effective_target_vect_sdot_hi { } {
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|| [istarget ia64-*-*]
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|| [istarget i?86-*-*] || [istarget x86_64-*-*]
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|| ([istarget mips*-*-*]
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&& [et-is-effective-target mips_msa]) }}]
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&& [et-is-effective-target mips_msa])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports a vector
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@ -7930,7 +7936,9 @@ proc check_effective_target_vect_udot_hi { } {
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return [check_cached_effective_target_indexed vect_udot_hi {
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expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
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|| ([istarget mips*-*-*]
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&& [et-is-effective-target mips_msa]) }}]
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&& [et-is-effective-target mips_msa])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports a vector
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@ -7945,7 +7953,9 @@ proc check_effective_target_vect_usad_char { } {
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|| ([istarget aarch64*-*-*]
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&& ![check_effective_target_aarch64_sve])
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|| ([istarget powerpc*-*-*]
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&& [check_p9vector_hw_available])}}]
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&& [check_p9vector_hw_available])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports both signed
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@ -7971,8 +7981,10 @@ proc check_effective_target_vect_mulhrs_hi {} {
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# by power-of-2 operations on vectors of 4-byte integers.
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proc check_effective_target_vect_sdiv_pow2_si {} {
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return [expr { [istarget aarch64*-*-*]
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&& [check_effective_target_aarch64_sve] }]
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return [expr { ([istarget aarch64*-*-*]
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&& [check_effective_target_aarch64_sve])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }]
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}
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# Return 1 if the target plus current options supports a vector
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@ -7992,7 +8004,9 @@ proc check_effective_target_vect_pack_trunc { } {
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&& [et-is-effective-target mips_msa])
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|| ([istarget s390*-*-*]
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&& [check_effective_target_s390_vx])
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|| [istarget amdgcn*-*-*] }}]
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|| [istarget amdgcn*-*-*]
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options supports a vector
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@ -8012,7 +8026,9 @@ proc check_effective_target_vect_unpack { } {
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&& [check_effective_target_arm_little_endian])
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|| ([istarget s390*-*-*]
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&& [check_effective_target_s390_vx])
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|| [istarget amdgcn*-*-*] }}]
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|| [istarget amdgcn*-*-*]
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target plus current options does not guarantee
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@ -8662,7 +8678,8 @@ proc check_effective_target_vect_masked_store { } {
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# Return 1 if the target supports vector gather loads via internal functions.
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proc check_effective_target_vect_gather_load_ifn { } {
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return [expr { [check_effective_target_aarch64_sve] }]
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return [expr { [check_effective_target_aarch64_sve]
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|| [check_effective_target_riscv_v] }]
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}
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# Return 1 if the target supports vector scatter stores.
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@ -8816,7 +8833,9 @@ proc check_effective_target_vect_extract_even_odd { } {
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&& ([et-is-effective-target mips_msa]
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|| [et-is-effective-target mpaired_single]))
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|| ([istarget s390*-*-*]
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&& [check_effective_target_s390_vx]) }}]
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&& [check_effective_target_s390_vx])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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# Return 1 if the target supports vector interleaving, 0 otherwise.
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@ -8832,7 +8851,9 @@ proc check_effective_target_vect_interleave { } {
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&& ([et-is-effective-target mpaired_single]
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|| [et-is-effective-target mips_msa]))
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|| ([istarget s390*-*-*]
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&& [check_effective_target_s390_vx]) }}]
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&& [check_effective_target_s390_vx])
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|| ([istarget riscv*-*-*]
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&& [check_effective_target_riscv_v]) }}]
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}
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foreach N {2 3 4 5 6 7 8} {
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