i386: Add ISA check for newly introduced prefetch builtins.
Hi all, As Hongtao said, the fail on pentiumpro is caused by missing ISA check since we are using emit_insn () through new builtins and it won't check if the TARGET matches. Previously, the builtin in middle-end will check that. On pentiumpro, we won't have anything that supports any prefetch so that it dropped into the pattern and then failed. I have added the restrictions just like what middle-end builtin_prefetch does. Also I added missing checks for PREFETCHI. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_PREFETCHI for prefetchi builtin. * config/i386/i386-expand.cc (ix86_expand_builtin): Add ISA check before emit_insn. * config/i386/prfchiintrin.h: Add target for intrin. gcc/testsuite/ChangeLog: * gcc.target/i386/prefetchi-5.c: New test.
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4 changed files with 27 additions and 4 deletions
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@ -498,7 +498,7 @@ BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide1
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BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide256kl_u8", IX86_BUILTIN_AESENCWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID)
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/* PREFETCHI */
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BDESC (0, 0, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT)
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BDESC (0, OPTION_MASK_ISA2_PREFETCHI, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT)
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BDESC (0, 0, CODE_FOR_nothing, "__builtin_ia32_prefetch", IX86_BUILTIN_PREFETCH, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT_INT_INT)
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BDESC_END (SPECIAL_ARGS, PURE_ARGS)
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@ -13133,7 +13133,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
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if (INTVAL (op3) == 1)
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{
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if (TARGET_64BIT
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if (TARGET_64BIT && TARGET_PREFETCHI
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&& local_func_symbolic_operand (op0, GET_MODE (op0)))
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emit_insn (gen_prefetchi (op0, op2));
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else
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@ -13152,7 +13152,14 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
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op0 = convert_memory_address (Pmode, op0);
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op0 = copy_addr_to_reg (op0);
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}
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emit_insn (gen_prefetch (op0, op1, op2));
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if (TARGET_3DNOW || TARGET_PREFETCH_SSE
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|| TARGET_PRFCHW || TARGET_PREFETCHWT1)
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emit_insn (gen_prefetch (op0, op1, op2));
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else if (!MEM_P (op0) && side_effects_p (op0))
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/* Don't do anything with direct references to volatile memory,
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but generate code to handle other side effects. */
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emit_insn (op0);
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}
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return 0;
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@ -30,6 +30,13 @@
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#ifdef __x86_64__
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#ifndef __PREFETCHI__
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#pragma GCC push_options
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#pragma GCC target("prefetchi")
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#define __DISABLE_PREFETCHI__
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#endif /* __PREFETCHI__ */
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extern __inline void
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_m_prefetchit0 (void* __P)
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@ -44,6 +51,11 @@ _m_prefetchit1 (void* __P)
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__builtin_ia32_prefetchi (__P, 2);
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}
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#endif
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#ifdef __DISABLE_PREFETCHI__
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#undef __DISABLE_PREFETCHI__
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#pragma GCC pop_options
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#endif /* __DISABLE_PREFETCHI__ */
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#endif /* __x86_64__ */
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#endif /* _PRFCHIINTRIN_H_INCLUDED */
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4
gcc/testsuite/gcc.target/i386/prefetchi-5.c
Normal file
4
gcc/testsuite/gcc.target/i386/prefetchi-5.c
Normal file
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@ -0,0 +1,4 @@
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/* { dg-do compile { target { ia32 } } } */
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/* { dg-options "-O0 -march=pentiumpro" } */
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#include "prefetchi-4.c"
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