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aarch64: Add ASHIFTRT handling for shrn pattern

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The first patch in the series has some fallout in the testsuite,
particularly gcc.target/aarch64/shrn-combine-2.c.
Our previous patterns for SHRN matched both
(truncate (ashiftrt (x) (N))) and (truncate (lshiftrt (x) (N))
as these are equivalent for the shift amounts involved.
In our refactoring, however, we mapped shrn to truncate+lshiftrt.

The fix here is to iterate over ashiftrt,lshiftrt in the pattern for it.
However, we don't want to allow ashiftrt for us_truncate or lshiftrt for
ss_truncate from the ALL_TRUNC iterator.

This patch addds a AARCH64_VALID_SHRN_OP helper to gate the valid
combinations of truncations and shifts.

Bootstrapped and tested on aarch64-none-linux-gnu and
aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64.h (AARCH64_VALID_SHRN_OP): Define.
	* config/aarch64/aarch64-simd.md
	(*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): Rename to...
	(*aarch64_<shrn_op><shrn_s>shrn_n<mode>_insn<vczle><vczbe>): ... This.
	Use SHIFTRT iterator and add AARCH64_VALID_SHRN_OP to condition.
	* config/aarch64/iterators.md (shrn_s): New code attribute.
This commit is contained in:
Kyrylo Tkachov 2023-06-06 23:42:48 +01:00
parent d20b2ad845
commit 207db5d92f
3 changed files with 10 additions and 3 deletions
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6
gcc/config/aarch64/aarch64-simd.md
View file

@ -6665,13 +6665,13 @@
[(set_attr "type" "neon_shift_imm_narrow_q")]
)
(define_insn "*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>"
(define_insn "*aarch64_<shrn_op><shrn_s>shrn_n<mode>_insn<vczle><vczbe>"
[(set (match_operand:<VNARROWQ> 0 "register_operand" "=w")
(ALL_TRUNC:<VNARROWQ>
(<TRUNC_SHIFT>:VQN
(SHIFTRT:VQN
(match_operand:VQN 1 "register_operand" "w")
(match_operand:VQN 2 "aarch64_simd_shift_imm_vec_<vn_mode>"))))]
"TARGET_SIMD"
"TARGET_SIMD && AARCH64_VALID_SHRN_OP (<ALL_TRUNC:CODE>, <SHIFTRT:CODE>)"
"<shrn_op>shrn\t%<vn2>0<Vmntype>, %<v>1<Vmtype>, %2"
[(set_attr "type" "neon_shift_imm_narrow_q")]
)

5
gcc/config/aarch64/aarch64.h
View file

@ -1297,4 +1297,9 @@ extern poly_uint16 aarch64_sve_vg;
#define REG_ALLOC_ORDER {}
#define ADJUST_REG_ALLOC_ORDER aarch64_adjust_reg_alloc_order ()
#define AARCH64_VALID_SHRN_OP(T,S) \
((T) == TRUNCATE \
|| ((T) == US_TRUNCATE && (S) == LSHIFTRT) \
|| ((T) == SS_TRUNCATE && (S) == ASHIFTRT))
#endif /* GCC_AARCH64_H */

2
gcc/config/aarch64/iterators.md
View file

@ -2398,6 +2398,8 @@
;; op prefix for shift right and narrow.
(define_code_attr srn_op [(ashiftrt "r") (lshiftrt "")])
(define_code_attr shrn_s [(ashiftrt "s") (lshiftrt "")])
;; Map shift operators onto underlying bit-field instructions
(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
(lshiftrt "ubfx") (rotatert "extr")])