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Fix _mm512_cvt_roundps_ph to generate sae instruction.

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zmm-version vcvtps2ph is special, it encodes {sae} in evex, but put
round control in the imm. For intrinsic _mm512_cvt_roundps_ph (a,
imm), imm contains both {sae} and round control, we need to separate
it in the assembly output since vcvtps2ph will ignore imm[3:7].

gcc/ChangeLog:

	* config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512):
	Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae.
	* config/i386/sse.md (<mask_codefor>avx512f_vcvtps2ph512<mask_name>): Extend to ..
	(<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>): .. this.
	(avx512f_vcvtps2ph512_mask_sae): New expander

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512f-vcvtps2ph-sae.c: New test.
This commit is contained in:
liuhongt 2022-08-30 17:32:47 +08:00
parent 47d2dcd139
commit 20288a0c89
3 changed files with 47 additions and 3 deletions
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2
gcc/config/i386/i386-builtin.def
View file

@ -1351,7 +1351,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask_sae, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT)
BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI)

30
gcc/config/i386/sse.md
View file

@ -26903,14 +26903,40 @@
(set_attr "btver2_decode" "vector")
(set_attr "mode" "V8SF")])
(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name>"
;; vcvtps2ph is special, it encodes {sae} in evex, but round control in the imm
;; For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae}
;; and round control, we need to separate it in the assembly output.
;; op2 in avx512f_vcvtps2ph512_mask_sae contains both sae and round control.
(define_expand "avx512f_vcvtps2ph512_mask_sae"
[(set (match_operand:V16HI 0 "register_operand" "=v")
(vec_merge:V16HI
(unspec:V16HI
[(match_operand:V16SF 1 "register_operand" "v")
(match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_VCVTPS2PH)
(match_operand:V16HI 3 "nonimm_or_0_operand")
(match_operand:HI 4 "register_operand")))]
"TARGET_AVX512F"
{
int round = INTVAL (operands[2]);
/* Separate {sae} from rounding control imm,
imm[3:7] will be ignored by the instruction. */
if (round & 8)
{
emit_insn (gen_avx512f_vcvtps2ph512_mask_round (operands[0], operands[1],
operands[2], operands[3], operands[4], GEN_INT (8)));
DONE;
}
})
(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>"
[(set (match_operand:V16HI 0 "register_operand" "=v")
(unspec:V16HI
[(match_operand:V16SF 1 "register_operand" "v")
(match_operand:SI 2 "const_0_to_255_operand")]
UNSPEC_VCVTPS2PH))]
"TARGET_AVX512F"
"vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
"vcvtps2ph\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "V16SF")])

18
gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c Normal file
View file

@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m512 x;
volatile __m256i y;
void extern
avx512f_test (void)
{
y = _mm512_cvtps_ph (x, 8);
y = _mm512_maskz_cvtps_ph (4, x, 9);
y = _mm512_mask_cvtps_ph (y, 2, x, 10);
}