avr.md (*reload_insi): Change predicate #1 to const_int_operand.
* config/avr/avr.md (*reload_insi): Change predicate #1 to const_int_operand. Ditto for peep2 producing this insn. Add argument to output_reload_insisf call. (*movsi,*movsf): Add argument to output_movsisf call. (*reload_insf): New insn and new peep2 to produce it. * config/avr/avr-protos.h (output_movsisf): Change prototype. (output_reload_insisf): Change prototype. * config/avr/avr.c (avr_asm_len): New function. (output_reload_insisf): Rewrite. (output_movsisf): Change prototype. output_reload_insisf for all CONST_INT and CONST_DOUBLE. ALlow moving 0.0f to memory. (adjust_insn_length): Add argument to output_movsisf and output_reload_insisf call. From-SVN: r175956
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
ffca9d534c
commit
1e6a67d1bd
4 changed files with 274 additions and 113 deletions
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@ -1,3 +1,19 @@
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2011-07-07 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.md (*reload_insi): Change predicate #1 to
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const_int_operand. Ditto for peep2 producing this insn.
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Add argument to output_reload_insisf call.
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(*movsi,*movsf): Add argument to output_movsisf call.
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(*reload_insf): New insn and new peep2 to produce it.
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* config/avr/avr-protos.h (output_movsisf): Change prototype.
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(output_reload_insisf): Change prototype.
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* config/avr/avr.c (avr_asm_len): New function.
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(output_reload_insisf): Rewrite.
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(output_movsisf): Change prototype. output_reload_insisf for
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all CONST_INT and CONST_DOUBLE. ALlow moving 0.0f to memory.
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(adjust_insn_length): Add argument to output_movsisf and
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output_reload_insisf call.
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2011-07-07 Bernd Schmidt <bernds@codesourcery.com>
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* emit-rtl.c (paradoxical_subreg_p): New function.
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@ -56,7 +56,7 @@ extern const char *out_movhi_r_mr (rtx insn, rtx op[], int *l);
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extern const char *out_movhi_mr_r (rtx insn, rtx op[], int *l);
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extern const char *out_movsi_r_mr (rtx insn, rtx op[], int *l);
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extern const char *out_movsi_mr_r (rtx insn, rtx op[], int *l);
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extern const char *output_movsisf (rtx insn, rtx operands[], int *l);
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extern const char *output_movsisf (rtx insn, rtx operands[], rtx clobber, int *l);
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extern const char *out_tstsi (rtx insn, rtx src, int *l);
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extern const char *out_tsthi (rtx insn, rtx src, int *l);
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extern const char *ret_cond_branch (rtx x, int len, int reverse);
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@ -85,7 +85,7 @@ extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]);
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extern int extra_constraint_Q (rtx x);
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extern int adjust_insn_length (rtx insn, int len);
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extern const char *output_reload_inhi (rtx insn, rtx *operands, int *len);
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extern const char *output_reload_insisf (rtx insn, rtx *operands, int *len);
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extern const char *output_reload_insisf (rtx insn, rtx *operands, rtx clobber, int *len);
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extern enum reg_class secondary_input_reload_class (enum reg_class,
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enum machine_mode,
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rtx);
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@ -1184,6 +1184,32 @@ avr_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
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}
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/* Helper function to print assembler resp. track instruction
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sequence lengths.
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If PLEN == NULL:
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Output assembler code from template TPL with operands supplied
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by OPERANDS. This is just forwarding to output_asm_insn.
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If PLEN != NULL:
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Add N_WORDS to *PLEN.
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Don't output anything.
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*/
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static void
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avr_asm_len (const char* tpl, rtx* operands, int* plen, int n_words)
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{
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if (NULL == plen)
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{
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output_asm_insn (tpl, operands);
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}
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else
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{
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*plen += n_words;
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}
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}
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/* Return a pointer register name as a string. */
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static const char *
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@ -2600,7 +2626,7 @@ out_movsi_mr_r (rtx insn, rtx op[], int *l)
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}
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const char *
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output_movsisf(rtx insn, rtx operands[], int *l)
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output_movsisf (rtx insn, rtx operands[], rtx clobber_reg, int *l)
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{
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int dummy;
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rtx dest = operands[0];
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@ -2643,6 +2669,11 @@ output_movsisf(rtx insn, rtx operands[], int *l)
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AS2 (mov,%D0,%D1));
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}
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}
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else if (CONST_INT_P (src)
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|| CONST_DOUBLE_P (src))
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{
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return output_reload_insisf (insn, operands, clobber_reg, real_l);
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}
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else if (CONSTANT_P (src))
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{
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if (test_hard_reg_class (LD_REGS, dest)) /* ldi d,i */
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@ -2653,68 +2684,6 @@ output_movsisf(rtx insn, rtx operands[], int *l)
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AS2 (ldi,%C0,hlo8(%1)) CR_TAB
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AS2 (ldi,%D0,hhi8(%1)));
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}
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if (GET_CODE (src) == CONST_INT)
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{
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const char *const clr_op0 =
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AVR_HAVE_MOVW ? (AS1 (clr,%A0) CR_TAB
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AS1 (clr,%B0) CR_TAB
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AS2 (movw,%C0,%A0))
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: (AS1 (clr,%A0) CR_TAB
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AS1 (clr,%B0) CR_TAB
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AS1 (clr,%C0) CR_TAB
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AS1 (clr,%D0));
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if (src == const0_rtx) /* mov r,L */
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{
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*l = AVR_HAVE_MOVW ? 3 : 4;
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return clr_op0;
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}
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else if (src == const1_rtx)
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{
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if (!real_l)
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output_asm_insn (clr_op0, operands);
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*l = AVR_HAVE_MOVW ? 4 : 5;
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return AS1 (inc,%A0);
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}
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else if (src == constm1_rtx)
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{
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/* Immediate constants -1 to any register */
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if (AVR_HAVE_MOVW)
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{
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*l = 4;
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return (AS1 (clr,%A0) CR_TAB
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AS1 (dec,%A0) CR_TAB
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AS2 (mov,%B0,%A0) CR_TAB
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AS2 (movw,%C0,%A0));
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}
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*l = 5;
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return (AS1 (clr,%A0) CR_TAB
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AS1 (dec,%A0) CR_TAB
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AS2 (mov,%B0,%A0) CR_TAB
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AS2 (mov,%C0,%A0) CR_TAB
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AS2 (mov,%D0,%A0));
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}
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else
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{
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int bit_nr = exact_log2 (INTVAL (src));
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if (bit_nr >= 0)
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{
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*l = AVR_HAVE_MOVW ? 5 : 6;
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if (!real_l)
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{
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output_asm_insn (clr_op0, operands);
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output_asm_insn ("set", operands);
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}
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if (!real_l)
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avr_output_bld (operands, bit_nr);
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return "";
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}
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}
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}
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/* Last resort, better than loading from memory. */
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*l = 10;
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return (AS2 (mov,__tmp_reg__,r31) CR_TAB
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@ -2735,7 +2704,7 @@ output_movsisf(rtx insn, rtx operands[], int *l)
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{
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const char *templ;
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if (src == const0_rtx)
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if (src == CONST0_RTX (GET_MODE (dest)))
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operands[1] = zero_reg_rtx;
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templ = out_movsi_mr_r (insn, operands, real_l);
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@ -4612,7 +4581,7 @@ adjust_insn_length (rtx insn, int len)
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break;
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case SImode:
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case SFmode:
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output_movsisf (insn, op, &len);
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output_movsisf (insn, op, NULL_RTX, &len);
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break;
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default:
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break;
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@ -4683,7 +4652,7 @@ adjust_insn_length (rtx insn, int len)
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break;
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case SImode:
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case SFmode:
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output_reload_insisf (insn, op, &len);
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output_reload_insisf (insn, op, XEXP (op[2], 0), &len);
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break;
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default:
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break;
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@ -6212,53 +6181,199 @@ output_reload_inhi (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
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}
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/* Reload a SI or SF compile time constant (OP[1]) into a GPR (OP[0]).
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CLOBBER_REG is a QI clobber reg needed to move vast majority of consts
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into a NO_LD_REGS. If CLOBBER_REG is NULL_RTX we either don't need a
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clobber reg or have to cook one up.
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LEN == NULL: Output instructions.
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LEN != NULL: Output nothing. Increment *LEN by number of words occupied
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by the insns printed.
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Return "". */
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const char *
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output_reload_insisf (rtx insn ATTRIBUTE_UNUSED, rtx *operands, int *len)
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output_reload_insisf (rtx insn ATTRIBUTE_UNUSED,
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rtx *op, rtx clobber_reg, int *len)
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{
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rtx src = operands[1];
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int cnst = (GET_CODE (src) == CONST_INT);
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rtx src = op[1];
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rtx dest = op[0];
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rtx xval, xdest[4];
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int ival[4];
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int clobber_val = 1234;
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bool cooked_clobber_p = false;
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bool set_p = false;
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unsigned int n;
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enum machine_mode mode = GET_MODE (dest);
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gcc_assert (REG_P (dest));
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if (len)
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*len = 0;
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/* (REG:SI 14) is special: It's neither in LD_REGS nor in NO_LD_REGS
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but has some subregs that are in LD_REGS. Use the MSB (REG:QI 17). */
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if (14 == REGNO (dest))
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{
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if (cnst)
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*len = 4 + ((INTVAL (src) & 0xff) != 0)
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+ ((INTVAL (src) & 0xff00) != 0)
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+ ((INTVAL (src) & 0xff0000) != 0)
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+ ((INTVAL (src) & 0xff000000) != 0);
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else
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*len = 8;
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return "";
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clobber_reg = gen_rtx_REG (QImode, 17);
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}
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if (cnst && ((INTVAL (src) & 0xff) == 0))
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output_asm_insn (AS2 (mov, %A0, __zero_reg__), operands);
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else
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/* We might need a clobber reg but don't have one. Look at the value
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to be loaded more closely. A clobber is only needed if it contains
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a byte that is neither 0, -1 or a power of 2. */
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if (NULL_RTX == clobber_reg
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&& !test_hard_reg_class (LD_REGS, dest))
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{
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output_asm_insn (AS2 (ldi, %2, lo8(%1)), operands);
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output_asm_insn (AS2 (mov, %A0, %2), operands);
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for (n = 0; n < GET_MODE_SIZE (mode); n++)
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{
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xval = simplify_gen_subreg (QImode, src, mode, n);
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if (!(const0_rtx == xval
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|| constm1_rtx == xval
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|| single_one_operand (xval, QImode)))
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{
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/* We have no clobber reg but need one. Cook one up.
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That's cheaper than loading from constant pool. */
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cooked_clobber_p = true;
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clobber_reg = gen_rtx_REG (QImode, 31);
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avr_asm_len ("mov __tmp_reg__,%0", &clobber_reg, len, 1);
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break;
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}
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}
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}
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if (cnst && ((INTVAL (src) & 0xff00) == 0))
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output_asm_insn (AS2 (mov, %B0, __zero_reg__), operands);
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else
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/* Now start filling DEST from LSB to MSB. */
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for (n = 0; n < GET_MODE_SIZE (mode); n++)
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{
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output_asm_insn (AS2 (ldi, %2, hi8(%1)), operands);
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output_asm_insn (AS2 (mov, %B0, %2), operands);
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bool done_byte = false;
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unsigned int j;
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rtx xop[3];
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/* Crop the n-th sub-byte. */
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xval = simplify_gen_subreg (QImode, src, mode, n);
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xdest[n] = simplify_gen_subreg (QImode, dest, mode, n);
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ival[n] = INTVAL (xval);
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/* Look if we can reuse the low word by means of MOVW. */
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if (n == 2
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&& AVR_HAVE_MOVW)
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{
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rtx lo16 = simplify_gen_subreg (HImode, src, mode, 0);
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rtx hi16 = simplify_gen_subreg (HImode, src, mode, 2);
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if (INTVAL (lo16) == INTVAL (hi16))
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{
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avr_asm_len ("movw %C0,%A0", &op[0], len, 1);
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break;
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}
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}
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/* Use CLR to zero a value so that cc0 is set as expected
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for zero. */
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if (ival[n] == 0)
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{
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avr_asm_len ("clr %0", &xdest[n], len, 1);
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continue;
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}
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if (clobber_val == ival[n]
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&& REGNO (clobber_reg) == REGNO (xdest[n]))
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{
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continue;
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}
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/* LD_REGS can use LDI to move a constant value */
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if (test_hard_reg_class (LD_REGS, xdest[n]))
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{
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xop[0] = xdest[n];
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xop[1] = xval;
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avr_asm_len ("ldi %0,lo8(%1)", xop, len, 1);
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continue;
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}
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/* Try to reuse value already loaded in some lower byte. */
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for (j = 0; j < n; j++)
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if (ival[j] == ival[n])
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{
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xop[0] = xdest[n];
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xop[1] = xdest[j];
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avr_asm_len ("mov %0,%1", xop, len, 1);
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done_byte = true;
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break;
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}
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if (done_byte)
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continue;
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/* Need no clobber reg for -1: Use CLR/DEC */
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if (-1 == ival[n])
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{
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avr_asm_len ("clr %0" CR_TAB
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"dec %0", &xdest[n], len, 2);
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continue;
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}
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/* Use T flag or INC to manage powers of 2 if we have
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no clobber reg. */
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if (NULL_RTX == clobber_reg
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&& single_one_operand (xval, QImode))
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{
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if (1 == ival[n])
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{
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avr_asm_len ("clr %0" CR_TAB
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"inc %0", &xdest[n], len, 2);
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continue;
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}
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xop[0] = xdest[n];
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xop[1] = GEN_INT (exact_log2 (ival[n] & GET_MODE_MASK (QImode)));
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gcc_assert (constm1_rtx != xop[1]);
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if (!set_p)
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{
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set_p = true;
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avr_asm_len ("set", xop, len, 1);
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}
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avr_asm_len ("clr %0" CR_TAB
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"bld %0,%1", xop, len, 2);
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continue;
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}
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/* We actually need the LD_REGS clobber reg. */
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gcc_assert (NULL_RTX != clobber_reg);
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xop[0] = xdest[n];
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xop[1] = xval;
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xop[2] = clobber_reg;
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clobber_val = ival[n];
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avr_asm_len ("ldi %2,lo8(%1)" CR_TAB
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"mov %0,%2", xop, len, 2);
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}
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if (cnst && ((INTVAL (src) & 0xff0000) == 0))
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output_asm_insn (AS2 (mov, %C0, __zero_reg__), operands);
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else
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/* If we cooked up a clobber reg above, restore it. */
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if (cooked_clobber_p)
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{
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output_asm_insn (AS2 (ldi, %2, hlo8(%1)), operands);
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output_asm_insn (AS2 (mov, %C0, %2), operands);
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}
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if (cnst && ((INTVAL (src) & 0xff000000) == 0))
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output_asm_insn (AS2 (mov, %D0, __zero_reg__), operands);
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else
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{
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output_asm_insn (AS2 (ldi, %2, hhi8(%1)), operands);
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output_asm_insn (AS2 (mov, %D0, %2), operands);
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avr_asm_len ("mov %0,__tmp_reg__", &clobber_reg, len, 1);
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}
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return "";
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}
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|
|
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@ -402,10 +402,10 @@
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||||
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||||
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(define_peephole2 ; movsi_lreg_const
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||||
(define_peephole2 ; *reload_insi
|
||||
[(match_scratch:QI 2 "d")
|
||||
(set (match_operand:SI 0 "l_register_operand" "")
|
||||
(match_operand:SI 1 "immediate_operand" ""))
|
||||
(match_operand:SI 1 "const_int_operand" ""))
|
||||
(match_dup 2)]
|
||||
"(operands[1] != const0_rtx
|
||||
&& operands[1] != constm1_rtx)"
|
||||
|
|
@ -416,12 +416,14 @@
|
|||
;; '*' because it is not used in rtl generation.
|
||||
(define_insn "*reload_insi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(match_operand:SI 1 "immediate_operand" "i"))
|
||||
(match_operand:SI 1 "const_int_operand" "n"))
|
||||
(clobber (match_operand:QI 2 "register_operand" "=&d"))]
|
||||
"reload_completed"
|
||||
"* return output_reload_insisf (insn, operands, NULL);"
|
||||
{
|
||||
return output_reload_insisf (insn, operands, operands[2], NULL);
|
||||
}
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cc" "none")])
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
|
||||
(define_insn "*movsi"
|
||||
|
|
@ -429,9 +431,11 @@
|
|||
(match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
|
||||
"(register_operand (operands[0],SImode)
|
||||
|| register_operand (operands[1],SImode) || const0_rtx == operands[1])"
|
||||
"* return output_movsisf (insn, operands, NULL);"
|
||||
{
|
||||
return output_movsisf (insn, operands, NULL_RTX, NULL);
|
||||
}
|
||||
[(set_attr "length" "4,4,8,9,4,10")
|
||||
(set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
|
||||
(set_attr "cc" "none,set_zn,clobber,clobber,clobber,clobber")])
|
||||
|
||||
;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
|
||||
;; move floating point numbers (32 bit)
|
||||
|
|
@ -452,12 +456,38 @@
|
|||
|
||||
(define_insn "*movsf"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
|
||||
(match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
|
||||
(match_operand:SF 1 "general_operand" "r,G,Qm,rG,F,F"))]
|
||||
"register_operand (operands[0], SFmode)
|
||||
|| register_operand (operands[1], SFmode)"
|
||||
"* return output_movsisf (insn, operands, NULL);"
|
||||
|| register_operand (operands[1], SFmode)
|
||||
|| operands[1] == CONST0_RTX (SFmode)"
|
||||
{
|
||||
return output_movsisf (insn, operands, NULL_RTX, NULL);
|
||||
}
|
||||
[(set_attr "length" "4,4,8,9,4,10")
|
||||
(set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
|
||||
(set_attr "cc" "none,set_zn,clobber,clobber,clobber,clobber")])
|
||||
|
||||
(define_peephole2 ; *reload_insf
|
||||
[(match_scratch:QI 2 "d")
|
||||
(set (match_operand:SF 0 "l_register_operand" "")
|
||||
(match_operand:SF 1 "const_double_operand" ""))
|
||||
(match_dup 2)]
|
||||
"operands[1] != CONST0_RTX (SFmode)"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(match_dup 1))
|
||||
(clobber (match_dup 2))])]
|
||||
"")
|
||||
|
||||
;; '*' because it is not used in rtl generation.
|
||||
(define_insn "*reload_insf"
|
||||
[(set (match_operand:SF 0 "register_operand" "=r")
|
||||
(match_operand:SF 1 "const_double_operand" "F"))
|
||||
(clobber (match_operand:QI 2 "register_operand" "=&d"))]
|
||||
"reload_completed"
|
||||
{
|
||||
return output_reload_insisf (insn, operands, operands[2], NULL);
|
||||
}
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
;;=========================================================================
|
||||
;; move string (like memcpy)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue