iris6.h (DWARF_FRAME_RETURN_COLUMN): Redefine to match what the system unwinder expects.

* config/mips/iris6.h (DWARF_FRAME_RETURN_COLUMN): Redefine to
	match what the system unwinder expects.
	* config/mips/mips.c (mips_frame_set): If we're saving the return
	address register and the dwarf return address column number differs
	from the hard register number, adjust the note reg to refer to the
	former.

From-SVN: r97617
This commit is contained in:
Olivier Hainque 2005-04-05 09:36:06 +00:00 committed by Olivier Hainque
parent df7cc9b576
commit 1de2bc2a00
3 changed files with 25 additions and 1 deletions

View file

@ -1,3 +1,12 @@
2005-04-05 Olivier Hainque <hainque@adacore.com>
* config/mips/iris6.h (DWARF_FRAME_RETURN_COLUMN): Redefine to
match what the system unwinder expects.
* config/mips/mips.c (mips_frame_set): If we're saving the return
address register and the dwarf return address column number differs
from the hard register number, adjust the note reg to refer to the
former.
2004-04-05 Richard Sandiford <rsandifo@redhat.com>
* config/mn10300/mn10300-protos.h (mn10300_override_options): Declare.

View file

@ -38,6 +38,11 @@ Boston, MA 02111-1307, USA. */
compiling -g. This guarantees that we can unwind the stack. */
#define DWARF2_FRAME_INFO 1
/* The system unwinder in libexc requires a specific dwarf return address
column to work. */
#undef DWARF_FRAME_RETURN_COLUMN
#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
#undef MACHINE_TYPE
#define MACHINE_TYPE "SGI running IRIX 6.x"

View file

@ -6276,8 +6276,18 @@ mips_set_frame_expr (rtx frame_pattern)
static rtx
mips_frame_set (rtx mem, rtx reg)
{
rtx set = gen_rtx_SET (VOIDmode, mem, reg);
rtx set;
/* If we're saving the return address register and the dwarf return
address column differs from the hard register number, adjust the
note reg to refer to the former. */
if (REGNO (reg) == GP_REG_FIRST + 31
&& DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
set = gen_rtx_SET (VOIDmode, mem, reg);
RTX_FRAME_RELATED_P (set) = 1;
return set;
}