[Patch ARM] Add initial tuning for Cortex-A55 and Cortex-A75
Much like my AArch64 patch a few weeks ago, this patch adds support for the ARM Cortex-A75 and Cortex-A55 processors through the -mcpu/-mtune values cortex-a55 and cortex-a75, and an ARM DynamIQ big.LITTLE configuration of these two processors through the -mcpu/-mtune value cortex-a75.cortex-a55 Both Cortex-A55 and Cortex-A75 support ARMv8-A with the ARM8.1-A and ARMv8.2-A extensions. This is reflected in the patch, -mcpu=cortex-a75 is treated as equivalent to passing -mtune=cortex-a75 -march=armv8.2-a+fp16 gcc/ 2017-07-04 James Greenhalgh <james.greenhalgh@arm.com> * config/arm/arm-cpus.in (cortex-a55): New. (cortex-a75): Likewise. (cortex-a75.cortex-a55): Likewise. * config/arm/driver-arm.c (arm_cpu_table): Add cortex-a55 and cortex-a75. * doc/invoke.texi (-mcpu): Document cortex-a55 and cortex-a75. * config/arm/arm-cpu-cdata.h: Regenerate. * config/arm/arm-cpu-data.h: Regenerate. * config/arm/arm-cpu.h: Regenerate. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. From-SVN: r249970
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
cea768b0ca
commit
1d79dcb813
9 changed files with 154 additions and 8 deletions
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@ -1,3 +1,17 @@
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2017-07-04 James Greenhalgh <james.greenhalgh@arm.com>
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* config/arm/arm-cpus.in (cortex-a55): New.
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(cortex-a75): Likewise.
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(cortex-a75.cortex-a55): Likewise.
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* config/arm/driver-arm.c (arm_cpu_table): Add cortex-a55 and
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cortex-a75.
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* doc/invoke.texi (-mcpu): Document cortex-a55 and cortex-a75.
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* config/arm/arm-cpu-cdata.h: Regenerate.
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* config/arm/arm-cpu-data.h: Regenerate.
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* config/arm/arm-cpu.h: Regenerate.
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm-tune.md: Regenerate.
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2017-07-04 Jan Hubicka <hubicka@ucw.cz>
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* haifa-sched.c (sched_create_recovery_edges): Update profile.
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@ -388,6 +388,34 @@ static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
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{ NULL, false, false, {isa_nobit}}
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};
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static const cpu_arch_extension cpu_opttab_cortexa55[] = {
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{
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"crypto", false, false,
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{ ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
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},
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{
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"nofp", true, false,
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{ ISA_ALL_FP, isa_nobit }
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},
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{ NULL, false, false, {isa_nobit}}
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};
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static const cpu_arch_extension cpu_opttab_cortexa75[] = {
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{
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"crypto", false, false,
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{ ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
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},
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{ NULL, false, false, {isa_nobit}}
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};
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static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = {
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{
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"crypto", false, false,
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{ ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit }
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},
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{ NULL, false, false, {isa_nobit}}
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};
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static const cpu_arch_extension cpu_opttab_cortexm33[] = {
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{
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"nofp", true, false,
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@ -1622,6 +1650,45 @@ const cpu_option all_cores[] =
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},
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TARGET_ARCH_armv8_a
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},
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{
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{
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"cortex-a55",
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cpu_opttab_cortexa55,
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{
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ISA_ARMv8_2a,
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isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
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ISA_FP_ARMv8,ISA_NEON,
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isa_nobit
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}
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},
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TARGET_ARCH_armv8_2_a
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},
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{
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{
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"cortex-a75",
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cpu_opttab_cortexa75,
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{
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ISA_ARMv8_2a,
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isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
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ISA_FP_ARMv8,ISA_NEON,
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isa_nobit
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}
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},
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TARGET_ARCH_armv8_2_a
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},
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{
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{
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"cortex-a75.cortex-a55",
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cpu_opttab_cortexa75cortexa55,
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{
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ISA_ARMv8_2a,
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isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,
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ISA_FP_ARMv8,ISA_NEON,
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isa_nobit
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}
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},
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TARGET_ARCH_armv8_2_a
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},
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{
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{
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"cortex-m23",
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@ -552,6 +552,21 @@ static const cpu_tune all_tunes[] =
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(TF_LDSCHED),
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&arm_cortex_a73_tune
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},
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{ /* cortex-a55. */
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TARGET_CPU_cortexa53,
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(TF_LDSCHED),
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&arm_cortex_a53_tune
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},
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{ /* cortex-a75. */
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TARGET_CPU_cortexa57,
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(TF_LDSCHED),
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&arm_cortex_a73_tune
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},
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{ /* cortex-a75.cortex-a55. */
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TARGET_CPU_cortexa53,
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(TF_LDSCHED),
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&arm_cortex_a73_tune
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},
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{ /* cortex-m23. */
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TARGET_CPU_cortexm23,
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(TF_LDSCHED),
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@ -128,6 +128,9 @@ enum processor_type
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TARGET_CPU_cortexa72cortexa53,
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TARGET_CPU_cortexa73cortexa35,
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TARGET_CPU_cortexa73cortexa53,
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TARGET_CPU_cortexa55,
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TARGET_CPU_cortexa75,
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TARGET_CPU_cortexa75cortexa55,
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TARGET_CPU_cortexm23,
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TARGET_CPU_cortexm33,
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TARGET_CPU_arm_none
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@ -1206,7 +1206,6 @@ begin cpu xgene1
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costs xgene1
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end cpu xgene1
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# V8 A-profile big.LITTLE implementations
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begin cpu cortex-a57.cortex-a53
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cname cortexa57cortexa53
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@ -1249,6 +1248,40 @@ begin cpu cortex-a73.cortex-a53
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end cpu cortex-a73.cortex-a53
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# ARMv8.2 A-profile Architecture Processors
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begin cpu cortex-a55
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cname cortexa55
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8.2-a+fp16
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fpu neon-fp-armv8
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option crypto add FP_ARMv8 CRYPTO
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option nofp remove ALL_FP
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costs cortex_a53
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end cpu cortex-a55
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begin cpu cortex-a75
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cname cortexa75
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8.2-a+fp16
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fpu neon-fp-armv8
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a73
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end cpu cortex-a75
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# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
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begin cpu cortex-a75.cortex-a55
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cname cortexa75cortexa55
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tune for cortex-a53
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tune flags LDSCHED
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architecture armv8.2-a+fp16
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fpu neon-fp-armv8
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a73
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end cpu cortex-a75.cortex-a55
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# V8 M-profile implementations.
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begin cpu cortex-m23
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cname cortexm23
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@ -342,6 +342,15 @@ Enum(processor_type) String(cortex-a73.cortex-a35) Value( TARGET_CPU_cortexa73co
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EnumValue
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Enum(processor_type) String(cortex-a73.cortex-a53) Value( TARGET_CPU_cortexa73cortexa53)
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EnumValue
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Enum(processor_type) String(cortex-a55) Value( TARGET_CPU_cortexa55)
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EnumValue
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Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
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EnumValue
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Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)
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EnumValue
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Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
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@ -56,5 +56,6 @@
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cortexa53,cortexa57,cortexa72,
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cortexa73,exynosm1,xgene1,
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cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
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cortexa73cortexa53,cortexm23,cortexm33"
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cortexa73cortexa53,cortexa55,cortexa75,
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cortexa75cortexa55,cortexm23,cortexm33"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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@ -52,6 +52,8 @@ static struct vendor_cpu arm_cpu_table[] = {
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{"0xd07", "armv8-a+crc", "cortex-a57"},
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{"0xd08", "armv8-a+crc", "cortex-a72"},
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{"0xd09", "armv8-a+crc", "cortex-a73"},
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{"0xd05", "armv8.2-a+fp16", "cortex-a55"},
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{"0xd0a", "armv8.2-a+fp16", "cortex-a75"},
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{"0xc14", "armv7-r", "cortex-r4"},
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{"0xc15", "armv7-r", "cortex-r5"},
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{"0xc20", "armv6-m", "cortex-m0"},
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@ -15519,9 +15519,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
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@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
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@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
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@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
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@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
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@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-r4},
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@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
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@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
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@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
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@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},
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@samp{cortex-r8},
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@samp{cortex-m33},
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@samp{cortex-m23},
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@samp{cortex-m7},
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@ -15544,7 +15545,8 @@ Additionally, this option can specify that GCC should tune the performance
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of the code for a big.LITTLE system. Permissible names are:
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@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
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@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
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@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53}.
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@samp{cortex-a72.cortex-a35}, @samp{cortex-a73.cortex-a53},
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@samp{cortex-a75.cortex-a55}.
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@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
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performance for a blend of processors within architecture @var{arch}.
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@ -15605,8 +15607,8 @@ Disables the floating-point and SIMD instructions on
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@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
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@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
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@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7},
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@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35}
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and @samp{cortex-a53}.
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@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35},
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@samp{cortex-a53} and @samp{cortex-a55}.
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@item +nofp.dp
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Disables the double-precision component of the floating-point instructions
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