AArch64: Add better costing for vector constants and operations
This patch adds extended costing to cost the creation of constants and the manipulation of constants. The default values provided are based on architectural expectations and each cost models can be individually tweaked as needed. The changes in this patch covers: * Construction of PARALLEL or CONST_VECTOR: Adds better costing for vector of constants which is based on the constant being created and the instruction that can be used to create it. i.e. a movi is cheaper than a literal load etc. * Construction of a vector through a vec_dup. gcc/ChangeLog: * config/arm/aarch-common-protos.h (struct vector_cost_table): Add movi, dup and extract costing fields. * config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs, thunderx_extra_costs, thunderx2t99_extra_costs, thunderx3t110_extra_costs, tsv110_extra_costs, a64fx_extra_costs): Use them. * config/arm/aarch-cost-tables.h (generic_extra_costs, cortexa53_extra_costs, cortexa57_extra_costs, cortexa76_extra_costs, exynosm1_extra_costs, xgene1_extra_costs): Likewise * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>): Add r->w dup. * config/aarch64/aarch64.c (aarch64_rtx_costs): Add extra costs. gcc/testsuite/ChangeLog: * gcc.target/aarch64/vect-cse-codegen.c: New test.
This commit is contained in:
Tamar Christina
parent
68b48f3f4c
commit
1d5c43db79
6 changed files with 188 additions and 20 deletions
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@ -124,7 +124,10 @@ const struct cpu_cost_table qdf24xx_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -229,7 +232,10 @@ const struct cpu_cost_table thunderx_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* Alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -333,7 +339,10 @@ const struct cpu_cost_table thunderx2t99_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* Alu. */
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COSTS_N_INSNS (4) /* Mult. */
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COSTS_N_INSNS (4), /* Mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -437,7 +446,10 @@ const struct cpu_cost_table thunderx3t110_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* Alu. */
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COSTS_N_INSNS (4) /* Mult. */
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COSTS_N_INSNS (4), /* Mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -542,7 +554,10 @@ const struct cpu_cost_table tsv110_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -646,7 +661,10 @@ const struct cpu_cost_table a64fx_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -74,12 +74,14 @@
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)
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(define_insn "aarch64_simd_dup<mode>"
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[(set (match_operand:VDQF_F16 0 "register_operand" "=w")
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[(set (match_operand:VDQF_F16 0 "register_operand" "=w,w")
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(vec_duplicate:VDQF_F16
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(match_operand:<VEL> 1 "register_operand" "w")))]
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(match_operand:<VEL> 1 "register_operand" "w,r")))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %1.<Vetype>[0]"
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[(set_attr "type" "neon_dup<q>")]
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"@
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dup\\t%0.<Vtype>, %1.<Vetype>[0]
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dup\\t%0.<Vtype>, %<vw>1"
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[(set_attr "type" "neon_dup<q>, neon_from_gp<q>")]
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)
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(define_insn "aarch64_dup_lane<mode>"
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@ -12701,7 +12701,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
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rtx op0, op1, op2;
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const struct cpu_cost_table *extra_cost
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= aarch64_tune_params.insn_extra_cost;
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int code = GET_CODE (x);
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rtx_code code = GET_CODE (x);
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scalar_int_mode int_mode;
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/* By default, assume that everything has equivalent cost to the
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@ -13462,8 +13462,7 @@ cost_plus:
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we must cost the explicit register move. */
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if (mode == DImode
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&& GET_MODE (op0) == SImode
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&& outer == SET)
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&& GET_MODE (op0) == SImode)
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{
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int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
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@ -14002,8 +14001,39 @@ cost_plus:
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mode, MULT, 1, speed);
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return true;
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}
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break;
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case CONST_VECTOR:
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{
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/* Load using MOVI/MVNI. */
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if (aarch64_simd_valid_immediate (x, NULL))
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*cost = extra_cost->vect.movi;
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else /* Load using constant pool. */
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*cost = extra_cost->ldst.load;
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break;
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}
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case VEC_CONCAT:
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/* depending on the operation, either DUP or INS.
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For now, keep default costing. */
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break;
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case VEC_DUPLICATE:
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/* Load using a DUP. */
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*cost = extra_cost->vect.dup;
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return false;
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case VEC_SELECT:
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{
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rtx op0 = XEXP (x, 0);
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*cost = rtx_cost (op0, GET_MODE (op0), VEC_SELECT, 0, speed);
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/* Fall through. */
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/* cost subreg of 0 as free, otherwise as DUP */
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rtx op1 = XEXP (x, 1);
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if (vec_series_lowpart_p (mode, GET_MODE (op1), op1))
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;
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else if (vec_series_highpart_p (mode, GET_MODE (op1), op1))
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*cost = extra_cost->vect.dup;
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else
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*cost = extra_cost->vect.extract;
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return true;
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}
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default:
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break;
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}
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@ -133,6 +133,9 @@ struct vector_cost_table
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{
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const int alu;
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const int mult;
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const int movi;
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const int dup;
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const int extract;
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};
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struct cpu_cost_table
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@ -122,7 +122,10 @@ const struct cpu_cost_table generic_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -226,7 +229,10 @@ const struct cpu_cost_table cortexa53_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -330,7 +336,10 @@ const struct cpu_cost_table cortexa57_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -434,7 +443,10 @@ const struct cpu_cost_table cortexa76_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (1), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -538,7 +550,10 @@ const struct cpu_cost_table exynosm1_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (0), /* alu. */
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COSTS_N_INSNS (4) /* mult. */
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COSTS_N_INSNS (4), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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@ -642,7 +657,10 @@ const struct cpu_cost_table xgene1_extra_costs =
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/* Vector */
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{
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COSTS_N_INSNS (2), /* alu. */
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COSTS_N_INSNS (8) /* mult. */
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COSTS_N_INSNS (8), /* mult. */
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COSTS_N_INSNS (1), /* movi. */
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COSTS_N_INSNS (2), /* dup. */
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COSTS_N_INSNS (2) /* extract. */
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}
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};
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97
gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c
Normal file
97
gcc/testsuite/gcc.target/aarch64/vect-cse-codegen.c
Normal file
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@ -0,0 +1,97 @@
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/* { dg-do compile { target { lp64 } } } */
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/* { dg-additional-options "-O3 -march=armv8.2-a+crypto -fno-schedule-insns -fno-schedule-insns2 -mcmodel=small" } */
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/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */
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#include <arm_neon.h>
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/*
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**test1:
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** adrp x[0-9]+, .LC[0-9]+
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** ldr q[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\]
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** add v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d
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** str q[0-9]+, \[x[0-9]+\]
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** fmov x[0-9]+, d[0-9]+
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** orr x[0-9]+, x[0-9]+, x[0-9]+
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** ret
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*/
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uint64_t
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test1 (uint64_t a, uint64x2_t b, uint64x2_t* rt)
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{
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uint64_t arr[2] = { 0x0942430810234076UL, 0x0942430810234076UL};
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uint64_t res = a | arr[0];
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uint64x2_t val = vld1q_u64 (arr);
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*rt = vaddq_u64 (val, b);
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return res;
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}
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/*
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**test2:
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** adrp x[0-9]+, .LC[0-1]+
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** ldr q[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\]
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** add v[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d
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** str q[0-9]+, \[x[0-9]+\]
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** fmov x[0-9]+, d[0-9]+
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** orr x[0-9]+, x[0-9]+, x[0-9]+
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** ret
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*/
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uint64_t
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test2 (uint64_t a, uint64x2_t b, uint64x2_t* rt)
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{
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uint64x2_t val = vdupq_n_u64 (0x0424303242234076UL);
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uint64_t arr = vgetq_lane_u64 (val, 0);
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uint64_t res = a | arr;
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*rt = vaddq_u64 (val, b);
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return res;
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}
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/*
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**test3:
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** adrp x[0-9]+, .LC[0-9]+
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** ldr q[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\]
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** add v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s
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** str q[0-9]+, \[x1\]
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** fmov w[0-9]+, s[0-9]+
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** orr w[0-9]+, w[0-9]+, w[0-9]+
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** ret
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*/
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uint32_t
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test3 (uint32_t a, uint32x4_t b, uint32x4_t* rt)
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{
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uint32_t arr[4] = { 0x094243, 0x094243, 0x094243, 0x094243 };
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uint32_t res = a | arr[0];
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uint32x4_t val = vld1q_u32 (arr);
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*rt = vaddq_u32 (val, b);
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return res;
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}
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/*
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**test4:
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** ushr v[0-9]+.16b, v[0-9]+.16b, 7
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** mov x[0-9]+, 16512
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** movk x[0-9]+, 0x1020, lsl 16
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** movk x[0-9]+, 0x408, lsl 32
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** movk x[0-9]+, 0x102, lsl 48
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** fmov d[0-9]+, x[0-9]+
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** pmull v[0-9]+.1q, v[0-9]+.1d, v[0-9]+.1d
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** dup v[0-9]+.2d, v[0-9]+.d\[0\]
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** pmull2 v[0-9]+.1q, v[0-9]+.2d, v[0-9]+.2d
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** trn2 v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b
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** umov w[0-9]+, v[0-9]+.h\[3\]
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** ret
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*/
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uint64_t
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test4 (uint8x16_t input)
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{
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uint8x16_t bool_input = vshrq_n_u8(input, 7);
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poly64x2_t mask = vdupq_n_p64(0x0102040810204080UL);
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poly64_t prodL = vmull_p64((poly64_t)vgetq_lane_p64((poly64x2_t)bool_input, 0),
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vgetq_lane_p64(mask, 0));
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poly64_t prodH = vmull_high_p64((poly64x2_t)bool_input, mask);
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uint8x8_t res = vtrn2_u8((uint8x8_t)prodL, (uint8x8_t)prodH);
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return vget_lane_u16((uint16x4_t)res, 3);
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}
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