diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 753422f2c47..1fd3468f650 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2008-08-28  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa/xtensa.md (<u>mulsidi3): Use a temporary register.
+
 2008-08-28  Adam Nemet  <anemet@caviumnetworks.com>
 
 	* config/mips/mips.h (ISA_HAS_BBIT): New macro.
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 7d85956bfe4..cffbcd12f94 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -222,10 +222,11 @@
 		 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
   "TARGET_MUL32_HIGH"
 {
-  emit_insn (gen_mulsi3 (gen_lowpart (SImode, operands[0]),
-			 operands[1], operands[2]));
+  rtx temp = gen_reg_rtx (SImode);
+  emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
   emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
 				     operands[1], operands[2]));
+  emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp));
   DONE;
 })