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[AArch64] Remove constraint strings from define_expand constructs

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A number of AArch64 define_expand patterns have specified constraints
for their operands. But the constraint strings are ignored at expand
time and are therefore redundant/useless. We now avoid specifying
constraints in new define_expands, but we should clean up the existing
define_expand definitions.

For example, the constraint "=w" is removed in the following case:
(define_expand "sqrt<mode>2"
    [(set (match_operand:GPF_F16 0 "register_operand" "=w")
The "" marks with an empty constraint in define_expand are removed as well.

2019-07-03  Dennis Zhang  <dennis.zhang@arm.com>

gcc/
	* config/aarch64/aarch64.md: Remove redundant constraints from
	define_expand but keep some patterns untouched if they are
	specially selected by TARGET_SECONDARY_RELOAD hook.
	* config/aarch64/aarch64-sve.md: Likewise.
	* config/aarch64/atomics.md: Remove redundant constraints from
	define_expand.
	* config/aarch64/aarch64-simd.md: Likewise.

From-SVN: r273021
This commit is contained in:
Dennis Zhang 2019-07-03 19:52:04 +00:00 • committed by Richard Sandiford
parent 03eddfb3b5
commit 1bbffb87a9
5 changed files with 382 additions and 370 deletions
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10
gcc/ChangeLog
View file

@ -1,3 +1,13 @@
2019-07-03 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64.md: Remove redundant constraints from
define_expand but keep some patterns untouched if they are
specially selected by TARGET_SECONDARY_RELOAD hook.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/atomics.md: Remove redundant constraints from
define_expand.
* config/aarch64/aarch64-simd.md: Likewise.
2019-07-03 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.h (DRIVER_SELF_SPECS): Remove the linker cases.

506
gcc/config/aarch64/aarch64-simd.md
View file

File diff suppressed because it is too large Load diff

3
gcc/config/aarch64/aarch64-sve.md
View file

@ -144,6 +144,7 @@
;; Handle big-endian memory reloads. We use byte PTRUE for all modes
;; to try to encourage reuse.
;; This pattern needs constraints due to TARGET_SECONDARY_RELOAD hook.
(define_expand "aarch64_sve_reload_be"
[(parallel
[(set (match_operand 0)
@ -3120,7 +3121,7 @@
;; Standard pattern name vec_init<mode><Vel>.
(define_expand "vec_init<mode><Vel>"
[(match_operand:SVE_ALL 0 "register_operand" "")
[(match_operand:SVE_ALL 0 "register_operand")
(match_operand 1 "" "")]
"TARGET_SVE"
{

197
gcc/config/aarch64/aarch64.md
View file

@ -388,8 +388,8 @@
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "aarch64_plus_operand" "")])
[(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_plus_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
@ -402,8 +402,8 @@
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPF 1 "register_operand" "")
(match_operand:GPF 2 "aarch64_fp_compare_operand" "")])
[(match_operand:GPF 1 "register_operand")
(match_operand:GPF 2 "aarch64_fp_compare_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
@ -417,7 +417,7 @@
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "aarch64_comparison_operator"
[(match_operand 1 "cc_register" "")
[(match_operand 1 "cc_register")
(match_operand 2 "const0_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
@ -480,9 +480,9 @@
;; csneg x0, x0, x1, mi
(define_expand "mod<mode>3"
[(match_operand:GPI 0 "register_operand" "")
(match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "const_int_operand" "")]
[(match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "const_int_operand")]
""
{
HOST_WIDE_INT val = INTVAL (operands[2]);
@ -593,9 +593,9 @@
)
(define_expand "casesi"
[(match_operand:SI 0 "register_operand" "") ; Index
(match_operand:SI 1 "const_int_operand" "") ; Lower bound
(match_operand:SI 2 "const_int_operand" "") ; Total range
[(match_operand:SI 0 "register_operand") ; Index
(match_operand:SI 1 "const_int_operand") ; Lower bound
(match_operand:SI 2 "const_int_operand") ; Total range
(match_operand:DI 3 "" "") ; Table label
(match_operand:DI 4 "" "")] ; Out of range label
""
@ -881,8 +881,8 @@
;; -------------------------------------------------------------------
(define_expand "call"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
[(parallel [(call (match_operand 0 "memory_operand")
(match_operand 1 "general_operand"))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
@ -906,8 +906,8 @@
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(call (match_operand 1 "memory_operand")
(match_operand 2 "general_operand")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
@ -931,8 +931,8 @@
)
(define_expand "sibcall"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
[(parallel [(call (match_operand 0 "memory_operand")
(match_operand 1 "general_operand"))
(return)
(use (match_operand 2 "" ""))])]
""
@ -944,8 +944,8 @@
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(call (match_operand 1 "memory_operand")
(match_operand 2 "general_operand")))
(return)
(use (match_operand 3 "" ""))])]
""
@ -1011,8 +1011,8 @@
;; -------------------------------------------------------------------
(define_expand "mov<mode>"
[(set (match_operand:SHORT 0 "nonimmediate_operand" "")
(match_operand:SHORT 1 "general_operand" ""))]
[(set (match_operand:SHORT 0 "nonimmediate_operand")
(match_operand:SHORT 1 "general_operand"))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
@ -1068,8 +1068,8 @@
)
(define_expand "mov<mode>"
[(set (match_operand:GPI 0 "nonimmediate_operand" "")
(match_operand:GPI 1 "general_operand" ""))]
[(set (match_operand:GPI 0 "nonimmediate_operand")
(match_operand:GPI 1 "general_operand"))]
""
"
if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
@ -1175,8 +1175,8 @@
)
(define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
[(set (match_operand:TI 0 "nonimmediate_operand")
(match_operand:TI 1 "general_operand"))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
@ -1230,8 +1230,8 @@
})
(define_expand "mov<mode>"
[(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "")
(match_operand:GPF_TF_F16 1 "general_operand" ""))]
[(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand")
(match_operand:GPF_TF_F16 1 "general_operand"))]
""
{
if (!TARGET_FLOAT)
@ -1715,9 +1715,9 @@
(define_expand "add<mode>3"
[(set
(match_operand:GPI 0 "register_operand" "")
(plus:GPI (match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "")))]
(match_operand:GPI 0 "register_operand")
(plus:GPI (match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_pluslong_or_poly_operand")))]
""
{
/* If operands[1] is a subreg extract the inner RTX. */
@ -1910,9 +1910,9 @@
})
(define_expand "addti3"
[(set (match_operand:TI 0 "register_operand" "")
(plus:TI (match_operand:TI 1 "register_operand" "")
(match_operand:TI 2 "aarch64_reg_or_imm" "")))]
[(set (match_operand:TI 0 "register_operand")
(plus:TI (match_operand:TI 1 "register_operand")
(match_operand:TI 2 "aarch64_reg_or_imm")))]
""
{
rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;
@ -1943,9 +1943,9 @@
})
(define_expand "addvti4"
[(match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "register_operand" "")
(match_operand:TI 2 "aarch64_reg_or_imm" "")
[(match_operand:TI 0 "register_operand")
(match_operand:TI 1 "register_operand")
(match_operand:TI 2 "aarch64_reg_or_imm")
(label_ref (match_operand 3 "" ""))]
""
{
@ -1977,9 +1977,9 @@
})
(define_expand "uaddvti4"
[(match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "register_operand" "")
(match_operand:TI 2 "aarch64_reg_or_imm" "")
[(match_operand:TI 0 "register_operand")
(match_operand:TI 1 "register_operand")
(match_operand:TI 2 "aarch64_reg_or_imm")
(label_ref (match_operand 3 "" ""))]
""
{
@ -2514,9 +2514,9 @@
(plus:<DWI>
(match_dup 4)
(zero_extend:<DWI>
(match_operand:GPI 1 "register_operand" "")))
(match_operand:GPI 1 "register_operand")))
(zero_extend:<DWI>
(match_operand:GPI 2 "register_operand" "")))
(match_operand:GPI 2 "register_operand")))
(match_dup 6)))
(set (match_operand:GPI 0 "register_operand")
(plus:GPI
@ -2577,9 +2577,9 @@
(plus:<DWI>
(match_dup 3)
(sign_extend:<DWI>
(match_operand:GPI 1 "register_operand" "")))
(match_operand:GPI 1 "register_operand")))
(sign_extend:<DWI>
(match_operand:GPI 2 "register_operand" "")))
(match_operand:GPI 2 "register_operand")))
(sign_extend:<DWI>
(plus:GPI
(plus:GPI (match_dup 4) (match_dup 1))
@ -2848,9 +2848,9 @@
})
(define_expand "subti3"
[(set (match_operand:TI 0 "register_operand" "")
(minus:TI (match_operand:TI 1 "aarch64_reg_or_zero" "")
(match_operand:TI 2 "register_operand" "")))]
[(set (match_operand:TI 0 "register_operand")
(minus:TI (match_operand:TI 1 "aarch64_reg_or_zero")
(match_operand:TI 2 "register_operand")))]
""
{
rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;
@ -3298,12 +3298,12 @@
[(set (reg:CC CC_REGNUM)
(compare:CC
(zero_extend:<DWI>
(match_operand:GPI 1 "aarch64_reg_or_zero" ""))
(match_operand:GPI 1 "aarch64_reg_or_zero"))
(plus:<DWI>
(zero_extend:<DWI>
(match_operand:GPI 2 "register_operand" ""))
(match_operand:GPI 2 "register_operand"))
(ltu:<DWI> (reg:CC CC_REGNUM) (const_int 0)))))
(set (match_operand:GPI 0 "register_operand" "")
(set (match_operand:GPI 0 "register_operand")
(minus:GPI
(minus:GPI (match_dup 1) (match_dup 2))
(ltu:GPI (reg:CC CC_REGNUM) (const_int 0))))])]
@ -3366,16 +3366,16 @@
(compare:CC_V
(minus:<DWI>
(sign_extend:<DWI>
(match_operand:GPI 1 "aarch64_reg_or_zero" ""))
(match_operand:GPI 1 "aarch64_reg_or_zero"))
(plus:<DWI>
(sign_extend:<DWI>
(match_operand:GPI 2 "register_operand" ""))
(match_operand:GPI 2 "register_operand"))
(ltu:<DWI> (reg:CC CC_REGNUM) (const_int 0))))
(sign_extend:<DWI>
(minus:GPI (match_dup 1)
(plus:GPI (ltu:GPI (reg:CC CC_REGNUM) (const_int 0))
(match_dup 2))))))
(set (match_operand:GPI 0 "register_operand" "")
(set (match_operand:GPI 0 "register_operand")
(minus:GPI
(minus:GPI (match_dup 1) (match_dup 2))
(ltu:GPI (reg:CC CC_REGNUM) (const_int 0))))])]
@ -3488,8 +3488,8 @@
)
(define_expand "abs<mode>2"
[(match_operand:GPI 0 "register_operand" "")
(match_operand:GPI 1 "register_operand" "")]
[(match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "register_operand")]
""
{
rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
@ -3902,10 +3902,10 @@
;; -------------------------------------------------------------------
(define_expand "cstore<mode>4"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(match_operator:SI 1 "aarch64_comparison_operator"
[(match_operand:GPI 2 "register_operand" "")
(match_operand:GPI 3 "aarch64_plus_operand" "")]))]
[(match_operand:GPI 2 "register_operand")
(match_operand:GPI 3 "aarch64_plus_operand")]))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@ -3927,10 +3927,10 @@
(define_expand "cstore<mode>4"
[(set (match_operand:SI 0 "register_operand" "")
[(set (match_operand:SI 0 "register_operand")
(match_operator:SI 1 "aarch64_comparison_operator_mode"
[(match_operand:GPF 2 "register_operand" "")
(match_operand:GPF 3 "aarch64_fp_compare_operand" "")]))]
[(match_operand:GPF 2 "register_operand")
(match_operand:GPF 3 "aarch64_fp_compare_operand")]))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@ -4015,13 +4015,13 @@
)
(define_expand "cmov<mode>6"
[(set (match_operand:GPI 0 "register_operand" "")
[(set (match_operand:GPI 0 "register_operand")
(if_then_else:GPI
(match_operator 1 "aarch64_comparison_operator"
[(match_operand:GPI 2 "register_operand" "")
(match_operand:GPI 3 "aarch64_plus_operand" "")])
(match_operand:GPI 4 "register_operand" "")
(match_operand:GPI 5 "register_operand" "")))]
[(match_operand:GPI 2 "register_operand")
(match_operand:GPI 3 "aarch64_plus_operand")])
(match_operand:GPI 4 "register_operand")
(match_operand:GPI 5 "register_operand")))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@ -4031,13 +4031,13 @@
)
(define_expand "cmov<mode>6"
[(set (match_operand:GPF 0 "register_operand" "")
[(set (match_operand:GPF 0 "register_operand")
(if_then_else:GPF
(match_operator 1 "aarch64_comparison_operator"
[(match_operand:GPF 2 "register_operand" "")
(match_operand:GPF 3 "aarch64_fp_compare_operand" "")])
(match_operand:GPF 4 "register_operand" "")
(match_operand:GPF 5 "register_operand" "")))]
[(match_operand:GPF 2 "register_operand")
(match_operand:GPF 3 "aarch64_fp_compare_operand")])
(match_operand:GPF 4 "register_operand")
(match_operand:GPF 5 "register_operand")))]
""
"
operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@ -4115,10 +4115,10 @@
)
(define_expand "mov<mode>cc"
[(set (match_operand:ALLI 0 "register_operand" "")
(if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator" "")
(match_operand:ALLI 2 "register_operand" "")
(match_operand:ALLI 3 "register_operand" "")))]
[(set (match_operand:ALLI 0 "register_operand")
(if_then_else:ALLI (match_operand 1 "aarch64_comparison_operator")
(match_operand:ALLI 2 "register_operand")
(match_operand:ALLI 3 "register_operand")))]
""
{
rtx ccreg;
@ -4134,10 +4134,10 @@
)
(define_expand "mov<GPF:mode><GPI:mode>cc"
[(set (match_operand:GPI 0 "register_operand" "")
(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
(match_operand:GPF 2 "register_operand" "")
(match_operand:GPF 3 "register_operand" "")))]
[(set (match_operand:GPI 0 "register_operand")
(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
(match_operand:GPF 2 "register_operand")
(match_operand:GPF 3 "register_operand")))]
""
{
rtx ccreg;
@ -4153,10 +4153,10 @@
)
(define_expand "mov<mode>cc"
[(set (match_operand:GPF 0 "register_operand" "")
(if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
(match_operand:GPF 2 "register_operand" "")
(match_operand:GPF 3 "register_operand" "")))]
[(set (match_operand:GPF 0 "register_operand")
(if_then_else:GPF (match_operand 1 "aarch64_comparison_operator")
(match_operand:GPF 2 "register_operand")
(match_operand:GPF 3 "register_operand")))]
""
{
rtx ccreg;
@ -4172,10 +4172,10 @@
)
(define_expand "<neg_not_op><mode>cc"
[(set (match_operand:GPI 0 "register_operand" "")
(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
(NEG_NOT:GPI (match_operand:GPI 2 "register_operand" ""))
(match_operand:GPI 3 "register_operand" "")))]
[(set (match_operand:GPI 0 "register_operand")
(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator")
(NEG_NOT:GPI (match_operand:GPI 2 "register_operand"))
(match_operand:GPI 3 "register_operand")))]
""
{
rtx ccreg;
@ -5404,7 +5404,7 @@
;; -------------------------------------------------------------------
(define_expand "<optab>"
[(set (match_operand:DI 0 "register_operand" "=r")
[(set (match_operand:DI 0 "register_operand")
(ANY_EXTRACT:DI (match_operand:DI 1 "register_operand")
(match_operand 2
"aarch64_simd_shift_imm_offset_di")
@ -6254,8 +6254,8 @@
)
(define_expand "sqrt<mode>2"
[(set (match_operand:GPF_F16 0 "register_operand" "=w")
(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")))]
[(set (match_operand:GPF_F16 0 "register_operand")
(sqrt:GPF_F16 (match_operand:GPF_F16 1 "register_operand")))]
"TARGET_FLOAT"
{
if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
@ -6414,6 +6414,7 @@
;; -------------------------------------------------------------------
;; Reload Scalar Floating point modes from constant pool.
;; The AArch64 port doesn't have __int128 constant move support.
;; The patterns need constraints due to TARGET_SECONDARY_RELOAD hook.
(define_expand "@aarch64_reload_movcp<GPF_TF:mode><P:mode>"
[(set (match_operand:GPF_TF 0 "register_operand" "=w")
(mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
@ -6514,9 +6515,9 @@
;; rodata section.
(define_expand "add_losym"
[(set (match_operand 0 "register_operand" "=r")
(lo_sum (match_operand 1 "register_operand" "r")
(match_operand 2 "aarch64_valid_symref" "S")))]
[(set (match_operand 0 "register_operand")
(lo_sum (match_operand 1 "register_operand")
(match_operand 2 "aarch64_valid_symref")))]
""
{
machine_mode mode = GET_MODE (operands[0]);
@ -6605,9 +6606,9 @@
;; instructions in the TLS stubs, in order to enable linker relaxation.
;; Therefore we treat the stubs as an atomic sequence.
(define_expand "tlsgd_small_<mode>"
[(parallel [(set (match_operand 0 "register_operand" "")
[(parallel [(set (match_operand 0 "register_operand")
(call (mem:DI (match_dup 2)) (const_int 1)))
(unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
(unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref")] UNSPEC_GOTSMALLTLS)
(clobber (reg:DI LR_REGNUM))])]
""
{
@ -6890,7 +6891,7 @@
;; Named pattern for expanding thread pointer reference.
(define_expand "get_thread_pointerdi"
[(match_operand:DI 0 "register_operand" "=r")]
[(match_operand:DI 0 "register_operand")]
""
{
rtx tmp = aarch64_load_tp (operands[0]);
@ -7147,10 +7148,10 @@
;; tracking enabled. Use the speculation tracker to decide whether to
;; copy operand 1 to the target, or to copy the fail value (operand 2).
(define_expand "@despeculate_copy<ALLI_TI:mode>"
[(set (match_operand:ALLI_TI 0 "register_operand" "=r")
[(set (match_operand:ALLI_TI 0 "register_operand")
(unspec_volatile:ALLI_TI
[(match_operand:ALLI_TI 1 "register_operand" "r")
(match_operand:ALLI_TI 2 "aarch64_reg_or_zero" "rZ")
[(match_operand:ALLI_TI 1 "register_operand")
(match_operand:ALLI_TI 2 "aarch64_reg_or_zero")
(use (reg:DI SPECULATION_TRACKER_REGNUM))
(clobber (reg:CC CC_REGNUM))] UNSPECV_SPECULATION_BARRIER))]
""

36
gcc/config/aarch64/atomics.md
View file

@ -21,11 +21,11 @@
;; Instruction patterns.
(define_expand "@atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand" "") ;; bool out
(match_operand:ALLI 1 "register_operand" "") ;; val out
(match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory
(match_operand:ALLI 3 "nonmemory_operand" "") ;; expected
(match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired
[(match_operand:SI 0 "register_operand") ;; bool out
(match_operand:ALLI 1 "register_operand") ;; val out
(match_operand:ALLI 2 "aarch64_sync_memory_operand") ;; memory
(match_operand:ALLI 3 "nonmemory_operand") ;; expected
(match_operand:ALLI 4 "aarch64_reg_or_zero") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; mod_s
(match_operand:SI 7 "const_int_operand")] ;; mod_f
@ -134,10 +134,10 @@
})
(define_expand "atomic_exchange<mode>"
[(match_operand:ALLI 0 "register_operand" "")
(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
(match_operand:ALLI 2 "aarch64_reg_or_zero" "")
(match_operand:SI 3 "const_int_operand" "")]
[(match_operand:ALLI 0 "register_operand")
(match_operand:ALLI 1 "aarch64_sync_memory_operand")
(match_operand:ALLI 2 "aarch64_reg_or_zero")
(match_operand:SI 3 "const_int_operand")]
""
{
rtx (*gen) (rtx, rtx, rtx, rtx);
@ -198,9 +198,9 @@
)
(define_expand "atomic_<atomic_optab><mode>"
[(match_operand:ALLI 0 "aarch64_sync_memory_operand" "")
[(match_operand:ALLI 0 "aarch64_sync_memory_operand")
(atomic_op:ALLI
(match_operand:ALLI 1 "<atomic_op_operand>" "")
(match_operand:ALLI 1 "<atomic_op_operand>")
(match_operand:SI 2 "const_int_operand"))]
""
{
@ -322,10 +322,10 @@
;; Load-operate-store, returning the original memory data.
(define_expand "atomic_fetch_<atomic_optab><mode>"
[(match_operand:ALLI 0 "register_operand" "")
(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
[(match_operand:ALLI 0 "register_operand")
(match_operand:ALLI 1 "aarch64_sync_memory_operand")
(atomic_op:ALLI
(match_operand:ALLI 2 "<atomic_op_operand>" "")
(match_operand:ALLI 2 "<atomic_op_operand>")
(match_operand:SI 3 "const_int_operand"))]
""
{
@ -439,10 +439,10 @@
;; Load-operate-store, returning the updated memory data.
(define_expand "atomic_<atomic_optab>_fetch<mode>"
[(match_operand:ALLI 0 "register_operand" "")
[(match_operand:ALLI 0 "register_operand")
(atomic_op:ALLI
(match_operand:ALLI 1 "aarch64_sync_memory_operand" "")
(match_operand:ALLI 2 "<atomic_op_operand>" ""))
(match_operand:ALLI 1 "aarch64_sync_memory_operand")
(match_operand:ALLI 2 "<atomic_op_operand>"))
(match_operand:SI 3 "const_int_operand")]
""
{
@ -600,7 +600,7 @@
)
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")]
[(match_operand:SI 0 "const_int_operand")]
""
{
enum memmodel model = memmodel_from_int (INTVAL (operands[0]));