diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b7309ab1068..20a836aa095 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2010-11-24 Mingjie Xing + + * config/mips/loongson.md: Change the description comment of the file + and update the copyright years. + (define_insn "div3): Add loongson3a support. + (define_insn "mod3"): Likewise. + * config/mips/mips.md: Rename mul3_mul3_ls2ef to + mul3_mul3_loongson. + (define_expand "mul3"): Add TARGET_LOONGSON_3A. + (define_insn "mul3_mul3_loongson"): Add loongson3a support. + 2010-11-23 Joseph Myers * common.opt (initial_max_fld_align, flag_debug_asm, diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md index 4f95c285ce5..225f4d16da9 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson.md @@ -1,5 +1,6 @@ -;; Machine description for ST Microelectronics Loongson-2E/2F. -;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. +;; Machine description for Loongson-specific patterns, such as +;; ST Microelectronics Loongson-2E/2F etc. +;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. @@ -497,14 +498,19 @@ "punpckl\t%0,%1,%2" [(set_attr "type" "fdiv")]) -;; Integer division and modulus. +;; Integer division and modulus. For integer multiplication, see mips.md. (define_insn "div3" [(set (match_operand:GPR 0 "register_operand" "=&d") (any_div:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF" - { return mips_output_division ("div.g\t%0,%1,%2", operands); } + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A" + { + if (TARGET_LOONGSON_2EF) + return mips_output_division ("div.g\t%0,%1,%2", operands); + else + return mips_output_division ("gsdiv\t%0,%1,%2", operands); + } [(set_attr "type" "idiv3") (set_attr "mode" "")]) @@ -512,7 +518,12 @@ [(set (match_operand:GPR 0 "register_operand" "=&d") (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF" - { return mips_output_division ("mod.g\t%0,%1,%2", operands); } + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A" + { + if (TARGET_LOONGSON_2EF) + return mips_output_division ("mod.g\t%0,%1,%2", operands); + else + return mips_output_division ("gsmod\t%0,%1,%2", operands); + } [(set_attr "type" "idiv3") (set_attr "mode" "")]) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2379eeb861e..31121f7458d 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1324,9 +1324,9 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (TARGET_LOONGSON_2EF) - emit_insn (gen_mul3_mul3_ls2ef (operands[0], operands[1], - operands[2])); + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) + emit_insn (gen_mul3_mul3_loongson (operands[0], operands[1], + operands[2])); else if (ISA_HAS_MUL3) emit_insn (gen_mul3_mul3 (operands[0], operands[1], operands[2])); else if (TARGET_FIX_R4000) @@ -1337,12 +1337,17 @@ DONE; }) -(define_insn "mul3_mul3_ls2ef" +(define_insn "mul3_mul3_loongson" [(set (match_operand:GPR 0 "register_operand" "=d") (mult:GPR (match_operand:GPR 1 "register_operand" "d") (match_operand:GPR 2 "register_operand" "d")))] - "TARGET_LOONGSON_2EF" - "multu.g\t%0,%1,%2" + "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A" +{ + if (TARGET_LOONGSON_2EF) + return "multu.g\t%0,%1,%2"; + else + return "gsmultu\t%0,%1,%2"; +} [(set_attr "type" "imul3nc") (set_attr "mode" "")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a38ef1082ad..cc9607e8f91 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2010-11-24 Mingjie Xing + + * gcc.target/mips/loongson3a-muldiv-1.c: New test. + * gcc.target/mips/loongson3a-muldiv-2.c: New test. + 2010-11-23 Joseph Myers * gcc.dg/opts-5.c: New test. diff --git a/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c b/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c new file mode 100644 index 00000000000..cc15b83ab93 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c @@ -0,0 +1,16 @@ +/* { dg-options "-O2 -march=loongson3a" } */ + +typedef int st; +typedef unsigned int ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tgsmultu\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tgsdivu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsmodu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsmod\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c b/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c new file mode 100644 index 00000000000..592b492c308 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c @@ -0,0 +1,16 @@ +/* { dg-options "-O2 -march=loongson3a -mgp64" } */ + +typedef long long st; +typedef unsigned long long ut; + +NOMIPS16 st smul (st x, st y) { return x * y; } +NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; } + +NOMIPS16 ut umul (ut x, ut y) { return x * y; } +NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; } + +/* { dg-final { scan-assembler-times "\tgsdmultu\t" 2 } } */ +/* { dg-final { scan-assembler-times "\tgsddivu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdmodu\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsddiv\t" 1 } } */ +/* { dg-final { scan-assembler-times "\tgsdmod\t" 1 } } */