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AArch64: Add FLAG for tbl/tbx intrinsics [PR94442]

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2020-11-10  Zhiheng Xie  <xiezhiheng@huawei.com>
	    Nannan Zheng  <zhengnannan@huawei.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
	for tbl/tbx intrinsics.
This commit is contained in:
zhengnannan 2020-11-10 11:43:36 +00:00 • committed by Richard Sandiford
parent 9e62802422
commit 1900707e56
1 changed files with 12 additions and 12 deletions
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24
gcc/config/aarch64/aarch64-simd-builtins.def
View file

@ -545,28 +545,28 @@
VAR1 (BINOPP, crypto_pmull, 0, NONE, v2di)
/* Implemented by aarch64_tbl3<mode>. */
VAR1 (BINOP, tbl3, 0, ALL, v8qi)
VAR1 (BINOP, tbl3, 0, ALL, v16qi)
VAR1 (BINOP, tbl3, 0, NONE, v8qi)
VAR1 (BINOP, tbl3, 0, NONE, v16qi)
/* Implemented by aarch64_qtbl3<mode>. */
VAR1 (BINOP, qtbl3, 0, ALL, v8qi)
VAR1 (BINOP, qtbl3, 0, ALL, v16qi)
VAR1 (BINOP, qtbl3, 0, NONE, v8qi)
VAR1 (BINOP, qtbl3, 0, NONE, v16qi)
/* Implemented by aarch64_qtbl4<mode>. */
VAR1 (BINOP, qtbl4, 0, ALL, v8qi)
VAR1 (BINOP, qtbl4, 0, ALL, v16qi)
VAR1 (BINOP, qtbl4, 0, NONE, v8qi)
VAR1 (BINOP, qtbl4, 0, NONE, v16qi)
/* Implemented by aarch64_tbx4<mode>. */
VAR1 (TERNOP, tbx4, 0, ALL, v8qi)
VAR1 (TERNOP, tbx4, 0, ALL, v16qi)
VAR1 (TERNOP, tbx4, 0, NONE, v8qi)
VAR1 (TERNOP, tbx4, 0, NONE, v16qi)
/* Implemented by aarch64_qtbx3<mode>. */
VAR1 (TERNOP, qtbx3, 0, ALL, v8qi)
VAR1 (TERNOP, qtbx3, 0, ALL, v16qi)
VAR1 (TERNOP, qtbx3, 0, NONE, v8qi)
VAR1 (TERNOP, qtbx3, 0, NONE, v16qi)
/* Implemented by aarch64_qtbx4<mode>. */
VAR1 (TERNOP, qtbx4, 0, ALL, v8qi)
VAR1 (TERNOP, qtbx4, 0, ALL, v16qi)
VAR1 (TERNOP, qtbx4, 0, NONE, v8qi)
VAR1 (TERNOP, qtbx4, 0, NONE, v16qi)
/* Builtins for ARMv8.1-A Adv.SIMD instructions. */