[AArch64] Use scvtf fbits option where appropriate
gcc/ChangeLog: 2019-08-19 Joel Hutton <Joel.Hutton@arm.com> * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype * config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function * config/aarch64/aarch64.md (*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult): New pattern (*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult): New pattern * config/aarch64/constraints.md (Dt): New constraint * config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate gcc/testsuite/ChangeLog: 2019-08-19 Joel Hutton <Joel.Hutton@arm.com> * gcc.target/aarch64/fmul_scvtf_1.c: New test. From-SVN: r274676
This commit is contained in:
Joel Hutton
Andre Vieira
parent
aac9103b0e
commit
188d00796f
8 changed files with 227 additions and 0 deletions
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@ -1,3 +1,12 @@
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2019-08-19 Joel Hutton <Joel.Hutton@arm.com>
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* config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype
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* config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function
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* config/aarch64/aarch64.md (*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult): New pattern
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(*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult): New pattern
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* config/aarch64/constraints.md (Dt): New constraint
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* config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate
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2019-08-19 Richard Biener <rguenther@suse.de>
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PR tree-optimization/91403
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@ -525,6 +525,7 @@ enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
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enum reg_class aarch64_regno_regclass (unsigned);
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int aarch64_asm_preferred_eh_data_format (int, int);
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int aarch64_fpconst_pow_of_2 (rtx);
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int aarch64_fpconst_pow2_recip (rtx);
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machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
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machine_mode);
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int aarch64_uxt_size (int, HOST_WIDE_INT);
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@ -19750,6 +19750,29 @@ aarch64_fpconst_pow_of_2 (rtx x)
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return exact_log2 (real_to_integer (r));
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}
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/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
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power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
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return n. Otherwise return -1. */
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int
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aarch64_fpconst_pow2_recip (rtx x)
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{
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REAL_VALUE_TYPE r0;
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if (!CONST_DOUBLE_P (x))
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return -1;
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r0 = *CONST_DOUBLE_REAL_VALUE (x);
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if (exact_real_inverse (DFmode, &r0)
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&& !REAL_VALUE_NEGATIVE (r0))
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{
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int ret = exact_log2 (real_to_integer (&r0));
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if (ret >= 1 && ret <= 32)
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return ret;
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}
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return -1;
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}
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/* If X is a vector of equal CONST_DOUBLE values and that value is
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Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
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@ -6051,6 +6051,44 @@
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[(set_attr "type" "f_cvtf2i")]
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)
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;; Equal width integer to fp and multiply combine.
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(define_insn "*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult"
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[(set (match_operand:GPF 0 "register_operand" "=w,w")
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(mult:GPF (FLOATUORS:GPF
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(match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r"))
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(match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt,Dt")))]
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"TARGET_FLOAT"
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{
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operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2]));
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switch (which_alternative)
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{
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case 0:
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return "<su_optab>cvtf\t%<GPF:s>0, %<s>1, #%2";
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case 1:
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return "<su_optab>cvtf\t%<GPF:s>0, %<w1>1, #%2";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")
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(set_attr "arch" "simd,fp")]
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)
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;; Unequal width integer to fp and multiply combine.
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(define_insn "*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult"
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[(set (match_operand:GPF 0 "register_operand" "=w")
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(mult:GPF (FLOATUORS:GPF
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(match_operand:<FCVT_IESIZE> 1 "register_operand" "r"))
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(match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt")))]
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"TARGET_FLOAT"
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{
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operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2]));
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return "<su_optab>cvtf\t%<GPF:s>0, %<w2>1, #%2";
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}
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[(set_attr "type" "f_cvti2f")]
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)
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;; Equal width integer to fp conversion.
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(define_insn "<optab><fcvt_target><GPF:mode>2"
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[(set (match_operand:GPF 0 "register_operand" "=w,w")
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(FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r")))]
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@ -6062,6 +6100,7 @@
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(set_attr "arch" "simd,fp")]
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)
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;; Unequal width integer to fp conversions.
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(define_insn "<optab><fcvt_iesize><GPF:mode>2"
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[(set (match_operand:GPF 0 "register_operand" "=w")
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(FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 "register_operand" "r")))]
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@ -344,6 +344,13 @@
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(match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
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QImode)")))
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(define_constraint "Dt"
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"@internal
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A const_double which is the reciprocal of an exact power of two, can be
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used in an scvtf with fract bits operation"
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(and (match_code "const_double")
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(match_test "aarch64_fpconst_pow2_recip (op) > 0")))
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(define_constraint "Dl"
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"@internal
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A constraint that matches vector of immediates for left shifts."
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@ -104,6 +104,10 @@
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(and (match_code "const_double")
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(match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
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(define_predicate "aarch64_fp_pow2_recip"
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(and (match_code "const_double")
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(match_test "aarch64_fpconst_pow2_recip (op) > 0")))
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(define_predicate "aarch64_fp_vec_pow2"
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(match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
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@ -1,3 +1,7 @@
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2019-08-19 Joel Hutton <Joel.Hutton@arm.com>
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* gcc.target/aarch64/fmul_scvtf_1.c: New test.
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2019-08-19 Marek Polacek <polacek@redhat.com>
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PR c++/91264 - detect modifying const objects in constexpr.
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140
gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c
Normal file
140
gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c
Normal file
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@ -0,0 +1,140 @@
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/* { dg-do run } */
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/* { dg-options "-save-temps -O2 -fno-inline" } */
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#define FUNC_DEFS(__a) \
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float \
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fsfoo##__a (int x) \
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{ \
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return ((float) x)/(1lu << __a); \
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} \
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float \
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fusfoo##__a (unsigned int x) \
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{ \
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return ((float) x)/(1lu << __a); \
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} \
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float \
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fslfoo##__a (long long x) \
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{ \
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return ((float) x)/(1lu << __a); \
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} \
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float \
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fulfoo##__a (unsigned long long x) \
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{ \
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return ((float) x)/(1lu << __a); \
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} \
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#define FUNC_DEFD(__a) \
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double \
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dsfoo##__a (int x) \
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{ \
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return ((double) x)/(1lu << __a); \
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} \
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double \
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dusfoo##__a (unsigned int x) \
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{ \
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return ((double) x)/(1lu << __a); \
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} \
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double \
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dslfoo##__a (long long x) \
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{ \
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return ((double) x)/(1lu << __a); \
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} \
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double \
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dulfoo##__a (unsigned long long x) \
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{ \
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return ((double) x)/(1lu << __a); \
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}
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FUNC_DEFS (4)
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */
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FUNC_DEFD (4)
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */
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FUNC_DEFS (8)
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */
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FUNC_DEFD (8)
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */
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FUNC_DEFS (16)
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */
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FUNC_DEFD (16)
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */
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FUNC_DEFS (32)
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */
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FUNC_DEFD (32)
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */
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#define FUNC_TESTS(__a, __b) \
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do \
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{ \
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if (fsfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \
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__builtin_abort (); \
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if (fusfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \
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__builtin_abort (); \
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if (fslfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \
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__builtin_abort (); \
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if (fulfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \
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__builtin_abort (); \
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} while (0)
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#define FUNC_TESTD(__a, __b) \
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do \
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{ \
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if (dsfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \
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__builtin_abort (); \
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if (dusfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \
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__builtin_abort (); \
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if (dslfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \
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__builtin_abort (); \
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if (dulfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \
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__builtin_abort (); \
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} while (0)
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int
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main (void)
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{
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int i;
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for (i = 0; i < 32; i ++)
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{
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FUNC_TESTS (4, i);
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FUNC_TESTS (8, i);
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FUNC_TESTS (16, i);
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FUNC_TESTS (32, i);
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FUNC_TESTD (4, i);
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FUNC_TESTD (8, i);
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FUNC_TESTD (16, i);
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FUNC_TESTD (32, i);
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}
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return 0;
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}
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