constraints.md: New file.
* config/sparc/constraints.md: New file. * config/sparc/sparc.md: Include it. * config/sparc/sparc-protos.h (memory_ok_for_ldd): Declare. (sparc_extra_constraint_check): Delete. * config/sparc/sparc.c (register_ok_for_ldd): Minor tweaks. (memory_ok_for_ldd): New predicate. (sparc_extra_constraint_check): Delete. * config/sparc/sparc.h (REG_CLASS_FROM_LETTER): Likewise. (CONST_OK_FOR_LETTER_P): Likewise. (CONST_DOUBLE_OK_FOR_LETTER_P): Likewise. (EXTRA_CONSTRAINT): Likewise. From-SVN: r140619
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
8179c2f253
commit
157891a301
6 changed files with 193 additions and 157 deletions
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@ -1,3 +1,17 @@
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2008-09-23 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/constraints.md: New file.
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* config/sparc/sparc.md: Include it.
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* config/sparc/sparc-protos.h (memory_ok_for_ldd): Declare.
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(sparc_extra_constraint_check): Delete.
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* config/sparc/sparc.c (register_ok_for_ldd): Minor tweaks.
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(memory_ok_for_ldd): New predicate.
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(sparc_extra_constraint_check): Delete.
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* config/sparc/sparc.h (REG_CLASS_FROM_LETTER): Likewise.
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(CONST_OK_FOR_LETTER_P): Likewise.
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(CONST_DOUBLE_OK_FOR_LETTER_P): Likewise.
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(EXTRA_CONSTRAINT): Likewise.
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2008-08-23 Steve Ellcey <sje@cup.hp.com>
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* regrename.c (do_replace): Copy REG_POINTER value to new reg.
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143
gcc/config/sparc/constraints.md
Normal file
143
gcc/config/sparc/constraints.md
Normal file
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@ -0,0 +1,143 @@
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;; Constraint definitions for SPARC.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;; Unused letters:
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;;; ABCD P Z
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;;; a jkl q tuvwxyz
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;; Register constraints
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(define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
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"Any floating-point register in VIS mode")
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(define_register_constraint "c" "FPCC_REGS"
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"Floating-point condition code register")
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(define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
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"Lower floating-point register in VIS mode")
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;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
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;; MD file for V8 and V9.
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(define_register_constraint "e" "TARGET_V9 ? EXTRA_FP_REGS : FP_REGS"
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"Any floating-point register")
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(define_register_constraint "f" "FP_REGS"
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"Lower floating-point register")
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(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
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"64-bit global or out register in V8+ mode")
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;; Floating-point constant constraints
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(define_constraint "G"
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"The floating-point zero constant"
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(and (match_code "const_double")
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(match_test "const_zero_operand (op, mode)")))
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;; Integer constant constraints
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(define_constraint "H"
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"Valid operand of double arithmetic operation"
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(and (match_code "const_double")
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(match_test "arith_double_operand (op, DImode)")))
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(define_constraint "I"
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"Signed 13-bit integer constant"
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(and (match_code "const_int")
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(match_test "SPARC_SIMM13_P (ival)")))
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(define_constraint "J"
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"The integer zero constant"
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(and (match_code "const_int")
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(match_test "ival == 0")))
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(define_constraint "K"
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"Signed 32-bit constant that can be loaded with a sethi instruction"
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(and (match_code "const_int")
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(match_test "SPARC_SETHI32_P (ival)")))
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(define_constraint "L"
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"Signed 11-bit integer constant"
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(and (match_code "const_int")
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(match_test "SPARC_SIMM11_P (ival)")))
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(define_constraint "M"
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"Signed 10-bit integer constant"
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(and (match_code "const_int")
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(match_test "SPARC_SIMM10_P (ival)")))
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(define_constraint "N"
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"Signed constant that can be loaded with a sethi instruction"
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(and (match_code "const_int")
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(match_test "SPARC_SETHI_P (ival)")))
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(define_constraint "O"
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"The 4096 constant"
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(and (match_code "const_int")
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(match_test "ival == 4096")))
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;; Extra constraints
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;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
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;; i.e. accept pseudo-registers during reload.
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(define_constraint "Q"
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"Floating-point constant that can be loaded with a sethi instruction"
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(and (match_code "const_double")
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(match_test "fp_sethi_p (op)")))
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(define_constraint "R"
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"Floating-point constant that can be loaded with a move instruction"
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(and (match_code "const_double")
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(match_test "fp_mov_p (op)")))
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(define_constraint "S"
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"Floating-point constant that can be loaded with a high/lo_sum sequence"
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(and (match_code "const_double")
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(match_test "fp_high_losum_p (op)")))
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;; Not needed in 64-bit mode
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(define_constraint "T"
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"Memory reference whose address is aligned to 8-byte boundary"
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(and (match_test "TARGET_ARCH32")
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(match_code "mem,reg")
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(match_test "memory_ok_for_ldd (op)")))
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;; Not needed in 64-bit mode
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(define_constraint "U"
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"Pseudo-register or hard even-numbered integer register"
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(and (match_test "TARGET_ARCH32")
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(match_code "reg")
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(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
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(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
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(match_test "register_ok_for_ldd (op)")))
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;; Equivalent to 'T' but available in 64-bit mode
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(define_constraint "W"
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"Memory reference for 'e' constraint floating-point register"
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(and (match_code "mem,reg")
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(match_test "memory_ok_for_ldd (op)")))
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(define_constraint "Y"
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"The vector zero constant"
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(and (match_code "const_vector")
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(match_test "const_zero_operand (op, mode)")))
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@ -107,13 +107,13 @@ extern int mem_min_alignment (rtx, int);
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extern int pic_address_needs_scratch (rtx);
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extern int reg_unused_after (rtx, rtx);
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extern int register_ok_for_ldd (rtx);
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extern int memory_ok_for_ldd (rtx);
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extern int registers_ok_for_ldd_peep (rtx, rtx);
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extern int v9_regcmp_p (enum rtx_code);
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/* Function used for V8+ code generation. Returns 1 if the high
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32 bits of REG are 0 before INSN. */
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extern int sparc_check_64 (rtx, rtx);
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extern rtx gen_df_reg (rtx, int);
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extern int sparc_extra_constraint_check (rtx, int, int);
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extern void sparc_expand_compare_and_swap_12 (rtx, rtx, rtx, rtx);
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#endif /* RTX_CODE */
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@ -6744,21 +6744,49 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
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return 1;
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}
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/* Return 1 if reg is a pseudo, or is the first register in
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a hard register pair. This makes it a candidate for use in
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/* Return 1 if reg is a pseudo, or is the first register in
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a hard register pair. This makes it suitable for use in
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ldd and std insns. */
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int
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register_ok_for_ldd (rtx reg)
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{
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/* We might have been passed a SUBREG. */
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if (GET_CODE (reg) != REG)
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if (!REG_P (reg))
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return 0;
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if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
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return (REGNO (reg) % 2 == 0);
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else
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return 1;
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return 1;
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}
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/* Return 1 if OP is a memory whose address is known to be
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aligned to 8-byte boundary, or a pseudo during reload.
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This makes it suitable for use in ldd and std insns. */
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int
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memory_ok_for_ldd (rtx op)
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{
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if (MEM_P (op))
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{
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/* In 64-bit mode, we assume that the address is word-aligned. */
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if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
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return 0;
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if ((reload_in_progress || reload_completed)
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&& !strict_memory_address_p (Pmode, XEXP (op, 0)))
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return 0;
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}
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else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
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{
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if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
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return 0;
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}
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else
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return 0;
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return 1;
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}
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/* Print operand X (an rtx) in assembler syntax to file FILE.
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@ -8356,68 +8384,6 @@ sparc_fold_builtin (tree fndecl, tree arglist, bool ignore)
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return NULL_TREE;
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}
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int
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sparc_extra_constraint_check (rtx op, int c, int strict)
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{
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int reload_ok_mem;
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if (TARGET_ARCH64
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&& (c == 'T' || c == 'U'))
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return 0;
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switch (c)
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{
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case 'Q':
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return fp_sethi_p (op);
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case 'R':
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return fp_mov_p (op);
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case 'S':
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return fp_high_losum_p (op);
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case 'U':
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if (! strict
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|| (GET_CODE (op) == REG
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&& (REGNO (op) < FIRST_PSEUDO_REGISTER
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|| reg_renumber[REGNO (op)] >= 0)))
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return register_ok_for_ldd (op);
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return 0;
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case 'W':
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case 'T':
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break;
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case 'Y':
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return const_zero_operand (op, GET_MODE (op));
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default:
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return 0;
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}
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/* Our memory extra constraints have to emulate the
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behavior of 'm' and 'o' in order for reload to work
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correctly. */
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if (GET_CODE (op) == MEM)
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{
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reload_ok_mem = 0;
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if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
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&& (! strict
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|| strict_memory_address_p (Pmode, XEXP (op, 0))))
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reload_ok_mem = 1;
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}
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else
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{
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reload_ok_mem = (reload_in_progress
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&& GET_CODE (op) == REG
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&& REGNO (op) >= FIRST_PSEUDO_REGISTER
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&& reg_renumber [REGNO (op)] < 0);
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}
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return reload_ok_mem;
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}
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/* ??? This duplicates information provided to the compiler by the
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??? scheduler description. Some day, teach genautomata to output
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??? the latencies and then CSE will just use that. */
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@ -1210,42 +1210,6 @@ extern char leaf_reg_remap[];
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/* Local macro to handle the two v9 classes of FP regs. */
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#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
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/* Get reg_class from a letter such as appears in the machine description.
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In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
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.md file for v8 and v9.
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'd' and 'b' are used for single and double precision VIS operations,
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if TARGET_VIS.
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'h' is used for V8+ 64 bit global and out registers. */
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#define REG_CLASS_FROM_LETTER(C) \
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(TARGET_V9 \
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? ((C) == 'f' ? FP_REGS \
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: (C) == 'e' ? EXTRA_FP_REGS \
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: (C) == 'c' ? FPCC_REGS \
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: ((C) == 'd' && TARGET_VIS) ? FP_REGS\
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: ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
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: ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
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: NO_REGS) \
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: ((C) == 'f' ? FP_REGS \
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: (C) == 'e' ? FP_REGS \
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: (C) == 'c' ? FPCC_REGS \
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: NO_REGS))
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/* The letters I, J, K, L, M, N, O, P in a register constraint string
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can be used to stand for particular ranges of CONST_INTs.
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This macro defines what the ranges are.
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C is the letter, and VALUE is a constant value.
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Return 1 if VALUE is in the range specified by C.
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`I' is used for the range of constants an insn can actually contain.
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`J' is used for the range which is just zero (since that is R0).
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`K' is used for constants which can be loaded with a single sethi insn.
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`L' is used for the range of constants supported by the movcc insns.
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`M' is used for the range of constants supported by the movrcc insns.
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`N' is like K, but for constants wider than 32 bits.
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`O' is used for the range which is just 4096.
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`P' is free. */
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/* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
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#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
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#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
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@ -1272,24 +1236,6 @@ extern char leaf_reg_remap[];
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#define SPARC_SETHI32_P(X) \
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(SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
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: (C) == 'J' ? (VALUE) == 0 \
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: (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
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: (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
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: (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
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: (C) == 'N' ? SPARC_SETHI_P (VALUE) \
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: (C) == 'O' ? (VALUE) == 4096 \
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: 0)
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/* Similar, but for CONST_DOUBLEs, and defining letters G and H.
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Here VALUE is the CONST_DOUBLE rtx itself. */
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#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
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: (C) == 'H' ? arith_double_operand (VALUE, DImode) \
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: 0)
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/* Given an rtx X being reloaded into a reg required to be
|
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in class CLASS, return the class of reg to actually use.
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In general this is just CLASS; but on some machines
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|
|
@ -1888,28 +1834,6 @@ do { \
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After reload, it makes no difference, since pseudo regs have
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been eliminated by then. */
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/* Optional extra constraints for this machine.
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'Q' handles floating point constants which can be moved into
|
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an integer register with a single sethi instruction.
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|
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'R' handles floating point constants which can be moved into
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an integer register with a single mov instruction.
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'S' handles floating point constants which can be moved into
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an integer register using a high/lo_sum sequence.
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'T' handles memory addresses where the alignment is known to
|
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be at least 8 bytes.
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`U' handles all pseudo registers or a hard even numbered
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integer register, needed for ldd/std instructions.
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'W' handles the memory operand when moving operands in/out
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of 'e' constraint floating point registers.
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|
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'Y' handles the zero vector constant. */
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#ifndef REG_OK_STRICT
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||||
/* Nonzero if X is a hard reg that can be used as an index
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|
|
@ -1923,15 +1847,6 @@ do { \
|
|||
or if it is a pseudo reg. */
|
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#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
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|
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/* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
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'W' is like 'T' but is assumed true on arch64.
|
||||
|
||||
Remember to accept pseudo-registers for memory constraints if reload is
|
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in progress. */
|
||||
|
||||
#define EXTRA_CONSTRAINT(OP, C) \
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sparc_extra_constraint_check(OP, C, 0)
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||||
|
||||
#else
|
||||
|
||||
/* Nonzero if X is a hard reg that can be used as an index. */
|
||||
|
|
@ -1939,9 +1854,6 @@ do { \
|
|||
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
||||
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
|
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|
||||
#define EXTRA_CONSTRAINT(OP, C) \
|
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sparc_extra_constraint_check(OP, C, 1)
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||||
|
||||
#endif
|
||||
|
||||
/* Should gcc use [%reg+%lo(xx)+offset] addresses? */
|
||||
|
|
|
|||
|
|
@ -320,9 +320,10 @@
|
|||
(include "niagara2.md")
|
||||
|
||||
|
||||
;; Operand and operator predicates.
|
||||
;; Operand and operator predicates and constraints
|
||||
|
||||
(include "predicates.md")
|
||||
(include "constraints.md")
|
||||
|
||||
|
||||
;; Compare instructions.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue