arm.c (cortexa7_extra_costs): New table.
2013-10-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.c (cortexa7_extra_costs): New table. (arm_cortex_a7_tune): New. * config/arm/arm-cores.def: Use cortex_a7 tuning for cortex-a7. From-SVN: r204157
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Kyrylo Tkachov
Kyrylo Tkachov
parent
cd216fbfb4
commit
1375873827
3 changed files with 124 additions and 1 deletions
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@ -1,3 +1,9 @@
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2013-10-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.c (cortexa7_extra_costs): New table.
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(arm_cortex_a7_tune): New.
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* config/arm/arm-cores.def: Use cortex_a7 tuning for cortex-a7.
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2013-10-29 Eric Botcazou <ebotcazou@adacore.com>
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* expr.c (expand_expr_real_1) <MEM_EXPR>: Eliminate small redundancy.
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@ -125,7 +125,7 @@ ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2)
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ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
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ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
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ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
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ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
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ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
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ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
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@ -1152,6 +1152,107 @@ const struct cpu_cost_table cortexa9_extra_costs =
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};
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const struct cpu_cost_table cortexa7_extra_costs =
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{
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/* ALU */
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{
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0, /* Arith. */
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0, /* Logical. */
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COSTS_N_INSNS (1), /* Shift. */
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COSTS_N_INSNS (1), /* Shift_reg. */
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COSTS_N_INSNS (1), /* Arith_shift. */
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COSTS_N_INSNS (1), /* Arith_shift_reg. */
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COSTS_N_INSNS (1), /* Log_shift. */
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COSTS_N_INSNS (1), /* Log_shift_reg. */
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COSTS_N_INSNS (1), /* Extend. */
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COSTS_N_INSNS (1), /* Extend_arith. */
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COSTS_N_INSNS (1), /* Bfi. */
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COSTS_N_INSNS (1), /* Bfx. */
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COSTS_N_INSNS (1), /* Clz. */
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0, /* non_exec. */
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true /* non_exec_costs_exec. */
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},
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{
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/* MULT SImode */
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{
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0, /* Simple. */
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COSTS_N_INSNS (1), /* Flag_setting. */
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COSTS_N_INSNS (1), /* Extend. */
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COSTS_N_INSNS (1), /* Add. */
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COSTS_N_INSNS (1), /* Extend_add. */
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COSTS_N_INSNS (7) /* Idiv. */
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},
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/* MULT DImode */
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{
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0, /* Simple (N/A). */
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0, /* Flag_setting (N/A). */
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COSTS_N_INSNS (1), /* Extend. */
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0, /* Add. */
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COSTS_N_INSNS (2), /* Extend_add. */
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0 /* Idiv (N/A). */
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}
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},
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/* LD/ST */
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{
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COSTS_N_INSNS (1), /* Load. */
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COSTS_N_INSNS (1), /* Load_sign_extend. */
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COSTS_N_INSNS (3), /* Ldrd. */
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COSTS_N_INSNS (1), /* Ldm_1st. */
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1, /* Ldm_regs_per_insn_1st. */
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2, /* Ldm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Loadf. */
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COSTS_N_INSNS (2), /* Loadd. */
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COSTS_N_INSNS (1), /* Load_unaligned. */
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COSTS_N_INSNS (1), /* Store. */
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COSTS_N_INSNS (3), /* Strd. */
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COSTS_N_INSNS (1), /* Stm_1st. */
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1, /* Stm_regs_per_insn_1st. */
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2, /* Stm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (2), /* Storef. */
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COSTS_N_INSNS (2), /* Stored. */
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COSTS_N_INSNS (1) /* Store_unaligned. */
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},
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{
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/* FP SFmode */
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{
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COSTS_N_INSNS (15), /* Div. */
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COSTS_N_INSNS (3), /* Mult. */
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COSTS_N_INSNS (7), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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COSTS_N_INSNS (3), /* Fpconst. */
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COSTS_N_INSNS (3), /* Neg. */
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COSTS_N_INSNS (3), /* Compare. */
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COSTS_N_INSNS (3), /* Widen. */
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COSTS_N_INSNS (3), /* Narrow. */
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COSTS_N_INSNS (3), /* Toint. */
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COSTS_N_INSNS (3), /* Fromint. */
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COSTS_N_INSNS (3) /* Roundint. */
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},
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/* FP DFmode */
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{
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COSTS_N_INSNS (30), /* Div. */
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COSTS_N_INSNS (6), /* Mult. */
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COSTS_N_INSNS (10), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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COSTS_N_INSNS (3), /* Fpconst. */
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COSTS_N_INSNS (3), /* Neg. */
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COSTS_N_INSNS (3), /* Compare. */
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COSTS_N_INSNS (3), /* Widen. */
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COSTS_N_INSNS (3), /* Narrow. */
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COSTS_N_INSNS (3), /* Toint. */
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COSTS_N_INSNS (3), /* Fromint. */
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COSTS_N_INSNS (3) /* Roundint. */
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}
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},
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/* Vector */
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{
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COSTS_N_INSNS (1) /* Alu. */
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}
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};
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const struct cpu_cost_table cortexa15_extra_costs =
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{
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/* ALU */
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@ -1368,6 +1469,22 @@ const struct tune_params arm_cortex_tune =
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false /* Prefer Neon for 64-bits bitops. */
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};
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const struct tune_params arm_cortex_a7_tune =
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{
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arm_9e_rtx_costs,
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&cortexa7_extra_costs,
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NULL,
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1, /* Constant limit. */
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5, /* Max cond insns. */
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ARM_PREFETCH_NOT_BENEFICIAL,
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false, /* Prefer constant pool. */
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arm_default_branch_cost,
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false, /* Prefer LDRD/STRD. */
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{true, true}, /* Prefer non short circuit. */
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&arm_default_vec_cost, /* Vectorizer costs. */
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false /* Prefer Neon for 64-bits bitops. */
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};
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const struct tune_params arm_cortex_a15_tune =
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{
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arm_9e_rtx_costs,
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