[ARC] Update various patterns
gcc/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (movqi_insn): Add stores to save constant long immediates. (movhi_insn): Update store instruction constraint which are saving 6-bit short immediates. (movsi_insn): Consider also short scaled load operations. (zero_extendhisi2_i): Use Usd constraint instead of T. (extendhisi2_i): Add q constraint. (arc_clzsi2): Add type and length attributes. (arc_ctzsi2): Likewise. * config/arc/constraints.md (Usc): Update constraint, the assembler can parse two relocations for a single instruction. gcc/testsuite/ 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/arc.exp: Test also cpp files. * gcc.target/arc/tdelay_slots.cpp: New test. From-SVN: r251587
This commit is contained in:
Claudiu Zissulescu
Claudiu Zissulescu
parent
7cfbf676bd
commit
1370fccf2b
6 changed files with 94 additions and 29 deletions
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@ -1,3 +1,17 @@
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2017-09-01 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.md (movqi_insn): Add stores to save constant long
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immediates.
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(movhi_insn): Update store instruction constraint which are saving
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6-bit short immediates.
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(movsi_insn): Consider also short scaled load operations.
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(zero_extendhisi2_i): Use Usd constraint instead of T.
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(extendhisi2_i): Add q constraint.
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(arc_clzsi2): Add type and length attributes.
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(arc_ctzsi2): Likewise.
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* config/arc/constraints.md (Usc): Update constraint, the
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assembler can parse two relocations for a single instruction.
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2017-09-01 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (arc_use_anchors_for_symbol_p): New function.
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@ -618,8 +618,8 @@
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; The iscompact attribute allows the epilogue expander to know for which
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; insns it should lengthen the return insn.
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(define_insn "*movqi_insn"
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[(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w,???w,h, w,Rcq, S,!*x, r,r, Ucm,m,???m,Usc")
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(match_operand:QI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,?Rac,i,?i, T,Rcq,Usd,Ucm,m,?Rac,c,?Rac,Cm3"))]
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[(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w,???w,h, w,Rcq, S,!*x, r,r, Ucm,m,???m, m,Usc")
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(match_operand:QI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,?Rac,i,?i, T,Rcq,Usd,Ucm,m,?Rac,c,?Rac,Cm3,i"))]
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"register_operand (operands[0], QImode)
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|| register_operand (operands[1], QImode)"
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"@
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@ -641,11 +641,12 @@
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xstb%U0 %1,%0
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stb%U0%V0 %1,%0
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stb%U0%V0 %1,%0
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stb%U0%V0 %1,%0
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stb%U0%V0 %1,%0"
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[(set_attr "type" "move,move,move,move,move,move,move,move,move,move,load,store,load,load,load,store,store,store,store")
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(set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,false,true,true,true,false,false,false,false,false,false")
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(set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,no,no,no,no,no,no,no,no,no")
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(set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
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[(set_attr "type" "move,move,move,move,move,move,move,move,move,move,load,store,load,load,load,store,store,store,store,store")
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(set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,false,true,true,true,false,false,false,false,false,false,false")
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(set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,no,no,no,no,no,no,no,no,no,no")
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(set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "move_dest_operand" "")
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@ -654,8 +655,8 @@
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"if (prepare_move_operands (operands, HImode)) DONE;")
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(define_insn "*movhi_insn"
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[(set (match_operand:HI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w,???w,Rcq#q,h, w,Rcq, S, r,r, Ucm,m,???m,VUsc,VUsc")
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(match_operand:HI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,?Rac, i,i,?i, T,Rcq,Ucm,m,?Rac,c,?Rac, Cm3,i"))]
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[(set (match_operand:HI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w,???w,Rcq#q,h, w,Rcq, S, r,r, Ucm,m,???m, m,VUsc")
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(match_operand:HI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,?Rac, i,i,?i, T,Rcq,Ucm,m,?Rac,c,?Rac,Cm3,i"))]
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"register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode)
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|| (CONSTANT_P (operands[1])
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@ -706,8 +707,8 @@
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; insns it should lengthen the return insn.
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; N.B. operand 1 of alternative 7 expands into pcl,symbol@gotpc .
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(define_insn "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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[(set (match_operand:SI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w, w, w, w, w,???w, ?w, w,Rcq#q, h, w,Rcq, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m,???m,VUsc,VUsc")
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(match_operand:SI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,Crr,Clo,Chi,Cbi,?Rac,Cpc,Clb, ?Cal,Cal,?Cal, T,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, w,!*Rzd,c,?Rac, Cm3, C32"))]
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[(set (match_operand:SI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w,w, w, w, w, w,???w, ?w, w,Rcq#q, h, w,Rcq, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m,???m, m,VUsc")
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(match_operand:SI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL,I,Crr,Clo,Chi,Cbi,?Rac,Cpc,Clb, ?Cal,Cal,?Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, w,!*Rzd,c,?Rac,Cm3, C32"))]
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"register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode)
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|| (CONSTANT_P (operands[1])
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@ -730,10 +731,10 @@
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mov%? %0,%1 ;11
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add %0,%S1 ;12
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add %0,pcl,%1@pcl ;13
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mov%? %0,%S1%& ;14
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mov%? %0,%S1 ;15
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mov%? %0,%S1 ;16
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ld%? %0,%1%& ;17
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mov%? %0,%1 ;14
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mov%? %0,%1 ;15
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mov%? %0,%1 ;16
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ld%?%U1 %0,%1 ;17
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st%? %1,%0%& ;18
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* return arc_short_long (insn, \"push%? %1%&\", \"st%U0 %1,%0%&\");
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* return arc_short_long (insn, \"pop%? %0%&\", \"ld%U1 %0,%1%&\");
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@ -747,13 +748,13 @@
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st%U0%V0 %1,%0 ;28
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st%U0%V0 %1,%0 ;29
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st%U0%V0 %1,%0 ;30
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st%U0%V0 %S1,%0 ;31"
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st%U0%V0 %1,%0 ;31"
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; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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[(set_attr "type" "move, move, move,move,move, move, move,two_cycle_core,shift,shift,shift, move,binary,binary, move, move, move,load,store,store,load,load, load,load,load, load,store,store,store,store,store,store")
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(set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false, false,false,false,false,false, false, false,maybe_limm,maybe_limm,false,true, true, true,true,true,false,true,true,false,false, true,false,false,false,false")
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; Use default length for iscompact to allow for COND_EXEC. But set length
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; of Crr to 4.
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(set_attr "length" "*,*,*,*,*,4,4,4,4,4,4,4,8,8,*,*,*,*,*,*,*,*,4,*,4,*,*,*,*,*,4,8")
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(set_attr "length" "*,*,*,*,*,4,4,4,4,4,4,4,8,8,*,*,*,*,*,*,*,*,4,*,4,*,*,*,*,*,*,8")
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(set_attr "predicable" "yes,no,yes,no,no,yes,no,no,no,no,no,yes,no,no,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no,no,no,no")
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(set_attr "cpu_facility" "av1,av1,av1,av2,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,av2,*,*,av2,*,*,av2,*")])
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@ -1634,7 +1635,7 @@
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)
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(define_insn "*zero_extendqisi2_ac"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r")
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r")
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(zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,T,Usd,Ucm,m")))]
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""
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"@
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@ -1659,19 +1660,19 @@
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(define_insn "*zero_extendhisi2_i"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,q,Rcw,w,!x,Rcqq,r,r")
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(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,Usd,Ucm,m")))]
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(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,T,Ucm,m")))]
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""
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"@
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ext%_%? %0,%1%&
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ext%_%? %0,%1%&
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bmsk%? %0,%1,15
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ext%_ %0,%1
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ld%_%? %0,%1%&
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ld%_%U1 %0,%1
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ld%_%? %0,%1
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ld%_%? %0,%1
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* return TARGET_EM ? \"xldh%U1%V1 %0,%1\" : \"xldw%U1 %0,%1\";
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ld%_%U1%V1 %0,%1"
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[(set_attr "type" "unary,unary,unary,unary,load,load,load,load")
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(set_attr "iscompact" "maybe,true,false,false,true,false,false,false")
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(set_attr "iscompact" "maybe,true,false,false,true,true,false,false")
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(set_attr "predicable" "no,no,yes,no,no,no,no,no")])
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@ -1726,7 +1727,7 @@
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)
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(define_insn "*extendhisi2_i"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcq,r,r")
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcqq,r,r")
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(sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "Rcqq,c,Ucd,Uex,m")))]
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""
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"@
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@ -4524,7 +4525,9 @@
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gen_rtx_GE (VOIDmode, gen_rtx_REG (CC_ZNmode, CC_REG), const0_rtx),
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gen_rtx_SET (operands[0], plus_constant (SImode, operands[0], 1))));
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DONE;
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})
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}
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[(set_attr "type" "unary")
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(set_attr "length" "12")])
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(define_expand "ctzsi2"
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[(match_operand:SI 0 "register_operand" "")
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@ -4567,8 +4570,9 @@
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gen_rtx_SET (operands[0], gen_rtx_MINUS (SImode, GEN_INT (31),
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operands[0]))));
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DONE;
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})
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}
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[(set_attr "type" "unary")
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(set_attr "length" "20")])
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(define_insn "swap"
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[(set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
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@ -357,13 +357,13 @@
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(and (match_code "mem")
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(match_test "compact_sda_memory_operand (op, VOIDmode, true)")))
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; Usc constant is only used for storing long constants, hence we can
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; have only [b,s9], and [b] types of addresses.
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(define_memory_constraint "Usc"
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"@internal
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A valid memory operand for storing constants"
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(and (match_code "mem")
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(match_test "!CONSTANT_P (XEXP (op,0))")
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;; ??? the assembler rejects stores of immediates to small data.
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(match_test "!compact_sda_memory_operand (op, VOIDmode, false)")))
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(match_test "!CONSTANT_P (XEXP (op,0))")))
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(define_constraint "Us<"
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"@internal
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@ -1,3 +1,8 @@
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2017-09-01 Claudiu Zissulescu <claziss@synopsys.com>
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* gcc.target/arc/arc.exp: Test also cpp files.
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* gcc.target/arc/tdelay_slots.cpp: New test.
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2017-09-01 Claudiu Zissulescu <claziss@synopsys.com>
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* gcc.target/arc/pr9001184797.c: New test.
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@ -104,7 +104,7 @@ if ![info exists DEFAULT_CFLAGS] then {
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dg-init
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# Main loop.
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{\[cS\],cpp}]] \
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"" $DEFAULT_CFLAGS
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# All done.
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42
gcc/testsuite/gcc.target/arc/tdelay_slots.cpp
Normal file
42
gcc/testsuite/gcc.target/arc/tdelay_slots.cpp
Normal file
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@ -0,0 +1,42 @@
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/* { dg-do assemble } */
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/* { dg-skip-if "" { ! { clmcpu } } } */
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/* { dg-options "-O2 -mcpu=em" } */
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template <class> struct A;
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int a;
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template <> struct A<char> {
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typedef int int_type;
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static int_type eof();
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};
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template <> struct A<wchar_t> {
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typedef int int_type;
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static int_type eof() { return -1; }
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};
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class basic_streambuf {
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public:
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virtual ~basic_streambuf();
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};
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class B {
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void tie();
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class C {
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C();
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};
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};
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template <typename _CharT, typename _Traits = A<_CharT>>
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class D : basic_streambuf {
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typedef _Traits traits_type;
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typename traits_type::int_type _M_unget_buf;
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public:
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D(void *) : _M_unget_buf(traits_type::eof()) {}
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};
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extern D<wchar_t> b;
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B c;
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void *operator new(unsigned, void *p2) { return p2; }
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B::C::C() {
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new D<char>(&a);
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c.tie();
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new (&b) D<wchar_t>(&a);
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}
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