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vsx-vector-6.p7.c: Update instruction counts and target.

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2019-02-06  Bill Seurer  <seurer@linux.vnet.ibm.com>

	* gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction
	counts and target.
	* gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction
	counts and target.
	* gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction
	counts and target.

From-SVN: r268585
This commit is contained in:
Bill Seurer 2019-02-06 16:29:56 +00:00 • committed by Bill Seurer
parent 2afcc6c3c1
commit 12f82acc9e
4 changed files with 28 additions and 32 deletions
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9
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,12 @@
2019-02-06 Bill Seurer <seurer@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction
counts and target.
* gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction
counts and target.
* gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction
counts and target.
2019-02-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/89182

24
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
View file

@ -1,28 +1,20 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-do compile { target { lp64 && be } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
/* Expected instruction counts for Power 7 */
/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */
/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */
/* { dg-final { scan-assembler-times "xxlnor" 5 } } */
/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */
/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 5 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 1 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 6 } } */
/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */

23
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
View file

@ -1,16 +1,15 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-do compile { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O2 -mcpu=power8" } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* Expected instruction counts for Power 8. */
/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
/* { dg-final { scan-assembler-times "xxlnor" 6 { target le } } } */
/* { dg-final { scan-assembler-times "xxlnor" 5 { target be } } } */
/* We generate xxlor instructions for many reasons other than or'ing vector
operands or calling __builtin_vec_or(), which means we cannot rely on
@ -18,16 +17,12 @@
xxlor instruction was generated. */
/* { dg-final { scan-assembler "xxlor" } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */
/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */
/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */
/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */
/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */
/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 6 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 2 } } */
/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 4 } } */
/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */

4
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
View file

@ -1,4 +1,4 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-do compile { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mvsx -O2 -mcpu=power9" } */
@ -8,7 +8,7 @@
/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
/* { dg-final { scan-assembler-times "xxlnor" 7 } } */
/* { dg-final { scan-assembler-times "xxlnor" 5 } } */
/* We generate xxlor instructions for many reasons other than or'ing vector
operands or calling __builtin_vec_or(), which means we cannot rely on