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sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...

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* config/sparc/sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...
	(movtf_insn_sp32): ...this.
	(movtf_insn_sp64_no_fpu): Consolidate into...
	(movtf_insn_sp64): ...this.
	(movtf_insn_sp64_hq): Do not test TARGET_FPU.
	* config/sparc/sparc.c (sparc_legitimate_address_p): Likewise.

From-SVN: r180831
This commit is contained in:
Eric Botcazou 2011-11-03 16:26:41 +00:00 • committed by Eric Botcazou
parent d0bc53bdb4
commit 12e55ac79d
3 changed files with 21 additions and 37 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2011-11-03 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...
(movtf_insn_sp32): ...this.
(movtf_insn_sp64_no_fpu): Consolidate into...
(movtf_insn_sp64): ...this.
(movtf_insn_sp64_hq): Do not test TARGET_FPU.
* config/sparc/sparc.c (sparc_legitimate_address_p): Likewise.
2011-11-03 Tristan Gingold <gingold@adacore.com>
* config/vms/vms.c (vms_patch_builtins): Fix typo.

2
gcc/config/sparc/sparc.c
View file

@ -3440,7 +3440,7 @@ sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
REG+REG address, then only one of them gets converted to an
offsettable address. */
if (mode == TFmode
&& ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
&& ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
return 0;
/* We prohibit REG + REG on ARCH32 if not optimizing for

47
gcc/config/sparc/sparc.md
View file

@ -2377,45 +2377,30 @@
})
(define_insn "*movtf_insn_sp32"
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o,U, r")
(match_operand:TF 1 "input_operand" " G,oe,GeUr,o,roG"))]
"TARGET_FPU
&& ! TARGET_ARCH64
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r")
(match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set_attr "length" "4")])
;; Exactly the same as above, except that all `e' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `e' reg
;; when -mno-fpu.
(define_insn "*movtf_insn_sp32_no_fpu"
[(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o, r,o")
(match_operand:TF 1 "input_operand" " G,o,U,roG,r"))]
"! TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set_attr "length" "4")])
[(set_attr "length" "4,4,4,4,4,4")
(set_attr "cpu_feature" "fpu,fpu,fpu,*,*,*")])
(define_insn "*movtf_insn_sp64"
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o, r")
(match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r")
(match_operand:TF 1 "input_operand" "G,oe,e,rG,roG"))]
"TARGET_ARCH64
&& ! TARGET_HARD_QUAD
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set_attr "length" "2")])
[(set_attr "length" "2,2,2,2,2")
(set_attr "cpu_feature" "fpu,fpu,fpu,*,*")])
(define_insn "*movtf_insn_sp64_hq"
[(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r")
(match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
"TARGET_ARCH64
&& TARGET_HARD_QUAD
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
@ -2429,16 +2414,6 @@
[(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
(set_attr "length" "2,*,*,*,2,2")])
(define_insn "*movtf_insn_sp64_no_fpu"
[(set (match_operand:TF 0 "nonimmediate_operand" "= r, o")
(match_operand:TF 1 "input_operand" "orG,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set_attr "length" "2")])
;; Now all the splits to handle multi-insn TF mode moves.
(define_split
[(set (match_operand:TF 0 "register_operand" "")