Documentation for vector extensions
From-SVN: r45880
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
86be733d75
commit
1255c85c04
4 changed files with 466 additions and 9 deletions
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@ -1,3 +1,11 @@
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2001-09-29 Bernd Schmidt <bernds@redhat.com>
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* config/i386/i386.c (init_mmx_sse_builtins): Fix type of storelps and
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storehps builtins.
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* doc/extend.texi (Vector Extensions): New node.
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* doc/invoke.texi (Machine Dependent Options): Add documentation for
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i386 -mmmx, -msse, -m3dnow.
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Sat Sep 29 15:08:16 CEST 2001 Jan Hubicka <jh@suse.cz>
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* doc/invoke.texi (Optimize Options): Revert an accidental checkin.
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@ -10989,10 +10989,10 @@ ix86_init_mmx_sse_builtins ()
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tree_cons (NULL_TREE, V4SF_type_node,
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tree_cons (NULL_TREE, pv2si_type_node,
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endlink)));
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tree v4sf_ftype_pv2si_v4sf
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= build_function_type (V4SF_type_node,
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tree_cons (NULL_TREE, V4SF_type_node,
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tree_cons (NULL_TREE, pv2si_type_node,
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tree void_ftype_pv2si_v4sf
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= build_function_type (void_type_node,
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tree_cons (NULL_TREE, pv2si_type_node,
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tree_cons (NULL_TREE, V4SF_type_node,
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endlink)));
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tree void_ftype_pfloat_v4sf
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= build_function_type (void_type_node,
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@ -11151,9 +11151,9 @@ ix86_init_mmx_sse_builtins ()
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for (i = 0, d = bdesc_comi; i < sizeof (bdesc_comi) / sizeof *d; i++, d++)
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def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
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def_builtin (MASK_SSE, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
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def_builtin (MASK_SSE, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
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def_builtin (MASK_SSE, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
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def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
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def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
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def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
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def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
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def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
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@ -11176,8 +11176,8 @@ ix86_init_mmx_sse_builtins ()
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def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
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def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
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def_builtin (MASK_SSE, "__builtin_ia32_storehps", v4sf_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
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def_builtin (MASK_SSE, "__builtin_ia32_storelps", v4sf_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
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def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
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def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
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def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
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def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
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@ -430,6 +430,7 @@ extensions, accepted by GCC in C89 mode and in C++.
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* Function Names:: Printable strings which are the name of the current
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function.
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* Return Address:: Getting the return or frame address of a function.
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* Vector Extensions:: Using vector instructions through built-in functions.
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* Other Builtins:: Other built-in functions.
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* Pragmas:: Pragmas accepted by GCC.
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@end menu
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@ -483,6 +484,7 @@ extensions, accepted by GCC in C89 mode and in C++.
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* Function Names:: Printable strings which are the name of the current
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function.
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* Return Address:: Getting the return or frame address of a function.
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* Vector Extensions:: Using vector instructions through built-in functions.
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* Other Builtins:: Other built-in functions.
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* Pragmas:: Pragmas accepted by GCC.
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@end menu
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@ -4147,6 +4149,75 @@ This function should only be used with a non-zero argument for debugging
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purposes.
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@end deftypefn
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@node Vector Extensions
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@section Using vector instructions through built-in functions
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On some targets, the instruction set contains SIMD vector instructions that
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operate on multiple values contained in one large register at the same time.
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For example, on the i386 the MMX, 3Dnow! and SSE extensions can be used
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this way.
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The first step in using these extensions is to provide the necessary data
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types. This should be done using an appropriate @code{typedef}:
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@example
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typedef int v4si __attribute__ ((mode(V4SI)));
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@end example
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The base type @code{int} is effectively ignored by the compiler, the
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actual properties of the new type @code{v4si} are defined by the
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@code{__attribute__}. It defines the machine mode to be used; for vector
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types these have the form @code{VnB}; @code{n} should be the number of
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elements in the vector, and @code{B} should be the base mode of the
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individual elements. The following can be used as base modes:
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@table @code
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@item QI
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An integer that is as wide as the smallest addressable unit, usually 8 bits.
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@item HI
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An integer, twice as wide as a QI mode integer, usually 16 bits.
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@item SI
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An integer, four times as wide as a QI mode integer, usually 32 bits.
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@item DI
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An integer, eight times as wide as a QI mode integer, usually 64 bits.
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@item SF
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A floating point value, as wide as a SI mode integer, usually 32 bits.
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@item DF
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A floating point value, as wide as a DI mode integer, usually 64 bits.
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@end table
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Not all base types or combinations are always valid; which modes can be used
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is determined by the target machine. For example, if targetting the i386 MMX
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extensions, only @code{V8QI}, @code{V4HI} and @code{V2SI} are allowed modes.
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There are no @code{V1xx} vector modes - they would be identical to the
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corresponding base mode.
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There is no distinction between signed and unsigned vector modes. This
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distinction is made by the operations that perform on the vectors, not
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by the data type.
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The types defined in this manner are somewhat special, they cannot be
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used with most normal C operations (i.e., a vector addition can @emph{not}
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be represented by a normal addition of two vector type variables). You
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can declare only variables and use them in function calls and returns, as
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well as in assignments and some casts. It is possible to cast from one
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vector type to another, provided they are of the same size (in fact, you
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can also cast vectors to and from other datatypes of the same size).
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A port that supports vector operations provides a set of built-in functions
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that can be used to operate on vectors. For example, a function to add two
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vectors and multiply the result by a third could look like this:
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@example
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v4si f (v4si a, v4si b, v4si c)
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@{
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v4si tmp = __builtin_addv4si (a, b);
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return __builtin_mulv4si (tmp, c);
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@}
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@end example
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@node Other Builtins
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@section Other built-in functions provided by GCC
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@cindex built-in functions
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@ -471,6 +471,7 @@ in the following sections.
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-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
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-mno-wide-multiply -mrtd -malign-double @gol
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-mpreferred-stack-boundary=@var{num} @gol
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-mmmx -msse -m3dnow @gol
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-mthreads -mno-align-stringops -minline-all-stringops @gol
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-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
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-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer}
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@ -7600,6 +7601,383 @@ to stack space usage, such as embedded systems and operating system kernels,
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may want to reduce the preferred alignment to
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@option{-mpreferred-stack-boundary=2}.
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@item -mmmx
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@itemx -mno-mmx
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@item -msse
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@itemx -mno-sse
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@item -m3dnow
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@itemx -mno-3dnow
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@opindex mmmx
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@opindex mno-mmx
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@opindex msse
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@opindex mno-sse
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@opindex m3dnow
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@opindex mno-3dnow
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These switches enable or disable the use of built-in functions that allow
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direct access to the MMX, SSE and 3Dnow extensions of the instruction set.
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The following machine modes are available for use with MMX builtins
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(@pxref{Vector Extensions}): @code{V2SI} for a vector of two 32 bit integers,
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@code{V4HI} for a vector of four 16 bit integers, and @code{V8QI} for a
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vector of eight 8 bit integers. Some of the builtins operate on MMX
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registers as a whole 64 bit entity, these use @code{DI} as their mode.
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If 3Dnow extensions are enabled, @code{V2SF} is used as a mode for a vector
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of two 32 bit floating point values.
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If SSE extensions are enabled, @code{V4SF} is used for a vector of four 32 bit
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floating point values. Some instructions use a vector of four 32 bit
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integers, these use @code{V4SI}. Finally, some instructions operate on an
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entire vector register, interpreting it as a 128 bit integer, these use mode
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@code{TI}.
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The following builtins are made available by @option{-mmmx}:
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@table @code
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@item v8qi __builtin_ia32_paddb (v8qi, v8qi)
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Generates the @code{paddb} machine instruction.
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@item v4hi __builtin_ia32_paddw (v4hi, v4hi)
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Generates the @code{paddw} machine instruction.
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@item v2si __builtin_ia32_paddd (v2si, v2si)
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Generates the @code{paddd} machine instruction.
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@item v8qi __builtin_ia32_psubb (v8qi, v8qi)
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Generates the @code{psubb} machine instruction.
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@item v4hi __builtin_ia32_psubw (v4hi, v4hi)
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Generates the @code{psubw} machine instruction.
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@item v2si __builtin_ia32_psubd (v2si, v2si)
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Generates the @code{psubd} machine instruction.
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@item v8qi __builtin_ia32_paddsb (v8qi, v8qi)
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Generates the @code{paddsb} machine instruction.
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@item v4hi __builtin_ia32_paddsw (v4hi, v4hi)
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Generates the @code{paddsw} machine instruction.
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@item v8qi __builtin_ia32_psubsb (v8qi, v8qi)
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Generates the @code{psubsb} machine instruction.
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@item v4hi __builtin_ia32_psubsw (v4hi, v4hi)
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Generates the @code{psubsw} machine instruction.
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@item v8qi __builtin_ia32_paddusb (v8qi, v8qi)
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Generates the @code{paddusb} machine instruction.
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@item v4hi __builtin_ia32_paddusw (v4hi, v4hi)
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Generates the @code{paddusw} machine instruction.
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@item v8qi __builtin_ia32_psubusb (v8qi, v8qi)
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Generates the @code{psubusb} machine instruction.
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@item v4hi __builtin_ia32_psubusw (v4hi, v4hi)
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Generates the @code{psubusw} machine instruction.
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@item v4hi __builtin_ia32_pmullw (v4hi, v4hi)
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Generates the @code{pmullw} machine instruction.
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@item v4hi __builtin_ia32_pmulhw (v4hi, v4hi)
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Generates the @code{pmulhw} machine instruction.
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@item di __builtin_ia32_pand (di, di)
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Generates the @code{pand} machine instruction.
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@item di __builtin_ia32_pandn (di,di)
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Generates the @code{pandn} machine instruction.
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@item di __builtin_ia32_por (di, di)
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Generates the @code{por} machine instruction.
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@item di __builtin_ia32_pxor (di, di)
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Generates the @code{pxor} machine instruction.
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@item v8qi __builtin_ia32_pcmpeqb (v8qi, v8qi)
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Generates the @code{pcmpeqb} machine instruction.
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@item v4hi __builtin_ia32_pcmpeqw (v4hi, v4hi)
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Generates the @code{pcmpeqw} machine instruction.
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@item v2si __builtin_ia32_pcmpeqd (v2si, v2si)
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Generates the @code{pcmpeqd} machine instruction.
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@item v8qi __builtin_ia32_pcmpgtb (v8qi, v8qi)
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Generates the @code{pcmpgtb} machine instruction.
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@item v4hi __builtin_ia32_pcmpgtw (v4hi, v4hi)
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Generates the @code{pcmpgtw} machine instruction.
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@item v2si __builtin_ia32_pcmpgtd (v2si, v2si)
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Generates the @code{pcmpgtd} machine instruction.
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@item v8qi __builtin_ia32_punpckhbw (v8qi, v8qi)
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Generates the @code{punpckhbw} machine instruction.
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@item v4hi __builtin_ia32_punpckhwd (v4hi, v4hi)
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Generates the @code{punpckhwd} machine instruction.
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@item v2si __builtin_ia32_punpckhdq (v2si, v2si)
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Generates the @code{punpckhdq} machine instruction.
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@item v8qi __builtin_ia32_punpcklbw (v8qi, v8qi)
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Generates the @code{punpcklbw} machine instruction.
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@item v4hi __builtin_ia32_punpcklwd (v4hi, v4hi)
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Generates the @code{punpcklwd} machine instruction.
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@item v2si __builtin_ia32_punpckldq (v2si, v2si)
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Generates the @code{punpckldq} machine instruction.
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@item v8qi __builtin_ia32_packsswb (v4hi, v4hi)
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Generates the @code{packsswb} machine instruction.
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@item v4hi __builtin_ia32_packssdw (v2si, v2si)
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Generates the @code{packssdw} machine instruction.
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@item v8qi __builtin_ia32_packuswb (v4hi, v4hi)
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Generates the @code{packuswb} machine instruction.
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@end table
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The following builtins are made available either with @option{-msse}, or
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with a combination of @option{-m3dnow} and @option{-march=athlon}.
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@table @code
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@item v4hi __builtin_ia32_pmulhuw (v4hi, v4hi)
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Generates the @code{pmulhuw} machine instruction.
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@item v8qi __builtin_ia32_pavgb (v8qi, v8qi)
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Generates the @code{pavgb} machine instruction.
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@item v4hi __builtin_ia32_pavgw (v4hi, v4hi)
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Generates the @code{pavgw} machine instruction.
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@item v4hi __builtin_ia32_psadbw (v8qi, v8qi)
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Generates the @code{psadbw} machine instruction.
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@item v8qi __builtin_ia32_pmaxub (v8qi, v8qi)
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Generates the @code{pmaxub} machine instruction.
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@item v4hi __builtin_ia32_pmaxsw (v4hi, v4hi)
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Generates the @code{pmaxsw} machine instruction.
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@item v8qi __builtin_ia32_pminub (v8qi, v8qi)
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Generates the @code{pminub} machine instruction.
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@item v4hi __builtin_ia32_pminsw (v4hi, v4hi)
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Generates the @code{pminsw} machine instruction.
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@item int __builtin_ia32_pextrw (v4hi, int)
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Generates the @code{pextrw} machine instruction.
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@item v4hi __builtin_ia32_pinsrw (v4hi, int, int)
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Generates the @code{pinsrw} machine instruction.
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@item int __builtin_ia32_pmovmskb (v8qi)
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Generates the @code{pmovmskb} machine instruction.
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@item void __builtin_ia32_maskmovq (v8qi, v8qi, char *)
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Generates the @code{maskmovq} machine instruction.
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@item void __buitlin_ia32_movntq (di *, di)
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Generates the @code{movntq} machine instruction.
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@item void __buitlin_ia32_sfence (void)
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Generates the @code{sfence} machine instruction.
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@item void __builtin_ia32_prefetch (char *, int selector)
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Generates a prefetch machine instruction, depending on the value of
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selector. If @code{selector} is 0, it generates @code{prefetchnta}; for
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a value of 1, it generates @code{prefetcht0}; for a value of 2, it generates
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@code{prefetcht1}; and for a value of 3 it generates @code{prefetcht2}.
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@end table
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The following builtins are available when @option{-msse} is used.
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@table @code
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@item int __buitlin_ia32_comieq (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs an equality
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comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_comineq (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs an inequality
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comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_comilt (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs a ``less than''
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comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_comile (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs a ``less or
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equal'' comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_comigt (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs a ``greater than''
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comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_comige (v4sf, v4sf)
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Generates the @code{comiss} machine instruction and performs a ``greater or
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equal'' comparison. The return value is the truth value of that comparison.
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@item int __buitlin_ia32_ucomieq (v4sf, v4sf)
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Generates the @code{ucomiss} machine instruction and performs an equality
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comparison. The return value is the truth value of that comparison.
|
||||
@item int __buitlin_ia32_ucomineq (v4sf, v4sf)
|
||||
Generates the @code{ucomiss} machine instruction and performs an inequality
|
||||
comparison. The return value is the truth value of that comparison.
|
||||
@item int __buitlin_ia32_ucomilt (v4sf, v4sf)
|
||||
Generates the @code{ucomiss} machine instruction and performs a ``less than''
|
||||
comparison. The return value is the truth value of that comparison.
|
||||
@item int __buitlin_ia32_ucomile (v4sf, v4sf)
|
||||
Generates the @code{ucomiss} machine instruction and performs a ``less or
|
||||
equal'' comparison. The return value is the truth value of that comparison.
|
||||
@item int __buitlin_ia32_ucomigt (v4sf, v4sf)
|
||||
Generates the @code{ucomiss} machine instruction and performs a ``greater than''
|
||||
comparison. The return value is the truth value of that comparison.
|
||||
@item int __buitlin_ia32_ucomige (v4sf, v4sf)
|
||||
Generates the @code{ucomiss} machine instruction and performs a ``greater or
|
||||
equal'' comparison. The return value is the truth value of that comparison.
|
||||
|
||||
@item v4sf __buitlin_ia32_addps (v4sf, v4sf)
|
||||
Generates the @code{addps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_addss (v4sf, v4sf)
|
||||
Generates the @code{addss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_subps (v4sf, v4sf)
|
||||
Generates the @code{subps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_subss (v4sf, v4sf)
|
||||
Generates the @code{subss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_mulps (v4sf, v4sf)
|
||||
Generates the @code{mulps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_mulss (v4sf, v4sf)
|
||||
Generates the @code{mulss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_divps (v4sf, v4sf)
|
||||
Generates the @code{divps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_divss (v4sf, v4sf)
|
||||
Generates the @code{divss} machine instruction.
|
||||
|
||||
@item v4si __buitlin_ia32_cmpeqps (v4sf, v4sf)
|
||||
Generates the @code{cmpeqps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmplts (v4sf, v4sf)
|
||||
Generates the @code{cmpltps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpleps (v4sf, v4sf)
|
||||
Generates the @code{cmpleps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpgtps (v4sf, v4sf)
|
||||
Generates the @code{cmpgtps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpgeps (v4sf, v4sf)
|
||||
Generates the @code{cmpgeps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpunordps (v4sf, v4sf)
|
||||
Generates the @code{cmpunodps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpneqps (v4sf, v4sf)
|
||||
Generates the @code{cmpeqps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpnltps (v4sf, v4sf)
|
||||
Generates the @code{cmpltps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpnleps (v4sf, v4sf)
|
||||
Generates the @code{cmpleps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpngtps (v4sf, v4sf)
|
||||
Generates the @code{cmpgtps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpngeps (v4sf, v4sf)
|
||||
Generates the @code{cmpgeps} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpordps (v4sf, v4sf)
|
||||
Generates the @code{cmpunodps} machine instruction.
|
||||
|
||||
@item v4si __buitlin_ia32_cmpeqss (v4sf, v4sf)
|
||||
Generates the @code{cmpeqss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpltss (v4sf, v4sf)
|
||||
Generates the @code{cmpltss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpless (v4sf, v4sf)
|
||||
Generates the @code{cmpless} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpgtss (v4sf, v4sf)
|
||||
Generates the @code{cmpgtss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpgess (v4sf, v4sf)
|
||||
Generates the @code{cmpgess} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpunordss (v4sf, v4sf)
|
||||
Generates the @code{cmpunodss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpneqss (v4sf, v4sf)
|
||||
Generates the @code{cmpeqss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpnlts (v4sf, v4sf)
|
||||
Generates the @code{cmpltss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpnless (v4sf, v4sf)
|
||||
Generates the @code{cmpless} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpngtss (v4sf, v4sf)
|
||||
Generates the @code{cmpgtss} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpngess (v4sf, v4sf)
|
||||
Generates the @code{cmpgess} machine instruction.
|
||||
@item v4si __buitlin_ia32_cmpordss (v4sf, v4sf)
|
||||
Generates the @code{cmpunodss} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_maxps (v4sf, v4sf)
|
||||
Generates the @code{maxps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_maxsss (v4sf, v4sf)
|
||||
Generates the @code{maxss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_minps (v4sf, v4sf)
|
||||
Generates the @code{minps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_minsss (v4sf, v4sf)
|
||||
Generates the @code{minss} machine instruction.
|
||||
|
||||
@item ti __buitlin_ia32_andps (ti, ti)
|
||||
Generates the @code{andps} machine instruction.
|
||||
@item ti __buitlin_ia32_andnps (ti, ti)
|
||||
Generates the @code{andnps} machine instruction.
|
||||
@item ti __buitlin_ia32_orps (ti, ti)
|
||||
Generates the @code{orps} machine instruction.
|
||||
@item ti __buitlin_ia32_xorps (ti, ti)
|
||||
Generates the @code{xorps} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_movps (v4sf, v4sf)
|
||||
Generates the @code{movps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_movhlps (v4sf, v4sf)
|
||||
Generates the @code{movhlps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_movlhps (v4sf, v4sf)
|
||||
Generates the @code{movlhps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_unpckhps (v4sf, v4sf)
|
||||
Generates the @code{unpckhps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_unpcklps (v4sf, v4sf)
|
||||
Generates the @code{unpcklps} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_cvtpi2ps (v4sf, v2si)
|
||||
Generates the @code{cvtpi2ps} machine instruction.
|
||||
@item v2si __buitlin_ia32_cvtps2pi (v4sf)
|
||||
Generates the @code{cvtps2pi} machine instruction.
|
||||
@item v4sf __buitlin_ia32_cvtsi2ss (v4sf, int)
|
||||
Generates the @code{cvtsi2ss} machine instruction.
|
||||
@item int __buitlin_ia32_cvtss2si (v4sf)
|
||||
Generates the @code{cvtsi2ss} machine instruction.
|
||||
@item v2si __buitlin_ia32_cvttps2pi (v4sf)
|
||||
Generates the @code{cvttps2pi} machine instruction.
|
||||
@item int __buitlin_ia32_cvttss2si (v4sf)
|
||||
Generates the @code{cvttsi2ss} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_rcpps (v4sf)
|
||||
Generates the @code{rcpps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_rsqrtps (v4sf)
|
||||
Generates the @code{rsqrtps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_sqrtps (v4sf)
|
||||
Generates the @code{sqrtps} machine instruction.
|
||||
@item v4sf __buitlin_ia32_rcpss (v4sf)
|
||||
Generates the @code{rcpss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_rsqrtss (v4sf)
|
||||
Generates the @code{rsqrtss} machine instruction.
|
||||
@item v4sf __buitlin_ia32_sqrtss (v4sf)
|
||||
Generates the @code{sqrtss} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_shufps (v4sf, v4sf, int)
|
||||
Generates the @code{shufps} machine instruction.
|
||||
|
||||
@item v4sf __buitlin_ia32_loadaps (float *)
|
||||
Generates the @code{movaps} machine instruction as a load from memory.
|
||||
@item void __buitlin_ia32_storeaps (float *, v4sf)
|
||||
Generates the @code{movaps} machine instruction as a store to memory.
|
||||
@item v4sf __buitlin_ia32_loadups (float *)
|
||||
Generates the @code{movups} machine instruction as a load from memory.
|
||||
@item void __buitlin_ia32_storeups (float *, v4sf)
|
||||
Generates the @code{movups} machine instruction as a store to memory.
|
||||
@item v4sf __buitlin_ia32_loadsss (float *)
|
||||
Generates the @code{movss} machine instruction as a load from memory.
|
||||
@item void __buitlin_ia32_storess (float *, v4sf)
|
||||
Generates the @code{movss} machine instruction as a store to memory.
|
||||
|
||||
@item v4sf __buitlin_ia32_loadhps (v4sf, v2si *)
|
||||
Generates the @code{movhps} machine instruction as a load from memory.
|
||||
@item v4sf __buitlin_ia32_loadlps (v4sf, v2si *)
|
||||
Generates the @code{movlps} machine instruction as a load from memory
|
||||
@item void __buitlin_ia32_storehps (v4sf, v2si *)
|
||||
Generates the @code{movhps} machine instruction as a store to memory.
|
||||
@item void __buitlin_ia32_storelps (v4sf, v2si *)
|
||||
Generates the @code{movlps} machine instruction as a store to memory.
|
||||
|
||||
@item void __buitlin_ia32_movntps (float *, v4sf)
|
||||
Generates the @code{movntps} machine instruction.
|
||||
@item int __buitlin_ia32_movmskps (v4sf)
|
||||
Generates the @code{movntps} machine instruction.
|
||||
|
||||
@item void __buitlin_ia32_storeps1 (float *, v4sf)
|
||||
Generates the @code{movaps} machine instruction as a store to memory.
|
||||
Before storing, the value is modified with a @code{shufps} instruction
|
||||
so that the lowest of the four floating point elements is replicated
|
||||
across the entire vector that is stored.
|
||||
@item void __buitlin_ia32_storerps (float *, v4sf)
|
||||
Generates the @code{movaps} machine instruction as a store to memory.
|
||||
Before storing, the value is modified with a @code{shufps} instruction
|
||||
so that the order of the four floating point elements in the vector is
|
||||
reversed.
|
||||
@item v4sf __buitlin_ia32_loadps1 (float *)
|
||||
Generates a @code{movss} machine instruction to load a floating point
|
||||
value from memory, and a @code{shufps} instruction to replicate the
|
||||
loaded value across all four elements of the result vector.
|
||||
@item v4sf __buitlin_ia32_loadrps (float *)
|
||||
Generates a @code{movaps} machine instruction to load a vector from
|
||||
memory, and a @code{shufps} instruction to reverse the order of the
|
||||
four floating point elements in the result vector.
|
||||
@item v4sf __builtin_ia32_setps (float, float, float, float)
|
||||
Constructs a vector from four single floating point values. The return
|
||||
value is equal to the value that would result from storing the four
|
||||
arguments into consecutive memory locations and then executing a
|
||||
@code{movaps} to load the vector from memory.
|
||||
@item v4sf __builtin_ia32_setps1 (float)
|
||||
Constructs a vector from a single floating point value by replicating
|
||||
it across all four elements of the result vector.
|
||||
@end table
|
||||
|
||||
@item -mpush-args
|
||||
@itemx -mno-push-args
|
||||
@opindex mpush-args
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue